JP2004199836A - Control method of nonvolatile memory, and nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method of nonvolatile memory capable of exactly performing read operation without necessitating verification operation. <P>SOLUTION: A memory cell array is provided with a pair of reference cells 10a, 10b for each same control word line CWL to which a plurality of memory cells 10 are connected. Complementary data are written in each reference cell 10a, 10b, and data are each re-written so as to be inverted in the polarity at each erase/write operation of the memory cells 10. Therefore, the written state of each memory cell 10 is exactly reflected on each reference cell 10a, 10b. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for controlling a nonvolatile memory and a nonvolatile memory, and more particularly, to a method for controlling an electrically erasable / writable flash memory.
[0002]
2. Description of the Related Art In recent years, flash memories for logic embedding have been widely used in semiconductor integrated circuit devices (LSIs) such as ASICs. Flash memory is capable of electrically erasing and writing data in a batch.Even if power is turned off, data can be retained even if the power is turned off by holding charges in an electrically isolated area called a floating gate embedded in the gate oxide film. It is a non-volatile memory that does not disappear. There is a demand for shortening the erasing / writing time in such flash memories.
[0003]
[Prior art]
Writing to the flash memory consists of two operations, erasing and programming. Erase is an operation of lowering the threshold of a memory cell (cell transistor), and programming is an operation of raising the threshold. Generally, a low threshold state corresponds to data “1”, and a high threshold state corresponds to data “0”. Let it. In this case, the read current increases in the cell with the low threshold data “1”, and conversely, the read current decreases in the cell with the high threshold data “0”.
[0004]
Conventionally, in such a flash memory, in order to distribute the threshold value of a cell after an erase operation / write operation within an appropriate range in which a read operation can be performed stably, an operation called preprogram and verify is performed. Be done.
[0005]
The pre-programming is an operation in which a cell is once programmed before an erasing operation, and a threshold distribution of the cell before erasing is made high (set to a threshold value on the data “0” side). This pre-program operation prevents the threshold distribution of the erased cell from being excessively widened.
[0006]
Verification is an operation of determining whether or not the threshold value of a cell after erasing / writing is within a target range (for example, see Patent Documents 1 and 2). Specifically, it is determined whether the threshold value after erasing (erase) has not become too low due to excessive erasing or whether the threshold value after writing (programming) has reached a sufficient value. If the verification operation results in NG (the threshold value has not reached the target range), the cell is re-erased / written.
[0007]
The reason why the re-erase / write operation is necessary is that, for example, a sufficient difference between the threshold value of the cell to be read and the threshold value as a read determination criterion cannot be obtained, so that the read operation cannot be performed correctly.
[0008]
However, the execution of the pre-program operation, the verify operation, and the subsequent re-erase / write operation as described above has a problem that the time (total time) until the erase / write operation is completed as a whole increases. .
[0009]
In recent years, logic circuits (state machines) for controlling pre-program operations and verify operations have become increasingly complicated (higher functions) due to reasons such as improved reliability of nonvolatile memories, and the circuit area (number of gates) has been increased. Are also increasing.
[0010]
For this reason, the ratio of those layout areas to the die size is increasing, which is a factor of increasing the die size. Such a problem becomes particularly remarkable in the case of a nonvolatile memory intended for small-capacity memory applications.
[0011]
Therefore, conventionally, a configuration has been proposed in which the verify operation is performed only on some of the memory cells in the memory cell array, thereby simplifying the verify operation (for example, see Patent Document 3).
[0012]
Further, as another conventional example, two reference cells in which complementary data of data “0” and data “1” are written are provided, and a read reference current generated by weighted averaging the read current of each reference cell is provided. There has been proposed a configuration in which the verify operation can be omitted by determining data based on the data (for example, see Patent Document 4).
[0013]
Further, as another configuration including such two reference cells, a configuration in which the data determination is performed based on a read reference current generated to be an intermediate value of the read current of each reference cell so that the verify operation can be omitted. Have also been proposed (for example, see Patent Documents 5 and 6).
[0014]
[Patent Document 1]
JP-A-5-36288
[Patent Document 2]
JP-A-5-54683
[Patent Document 3]
JP-A-8-180696
[Patent Document 4]
JP-A-8-190797
[Patent Document 5]
JP-A-8-274282
[Patent Document 6]
JP-A-10-208476
[0015]
[Problems to be solved by the invention]
By the way, in the configuration shown in each of the documents 3 to 6 as described above, each reference cell to which the data “0” and the data “1” are written is predetermined (fixed). For this reason, if the circuits for the pre-program function and the verify function are reduced for reasons such as a reduction in the circuit area, and neither of them is performed, data "0" is repeatedly written in the reference cell of data "0". As a result, data "1" is repeatedly written in the reference cell of data "1".
[0016]
As a result, the threshold value of the reference cell of data “0” gradually increases with each writing, and the threshold value of the reference cell of data “1” gradually decreases with each writing. There is a problem that the written state (cell deterioration, temperature, process conditions, etc.) is not correctly reflected on the reference cell.
[0017]
For this reason, a read reference current in which a write state is appropriately reflected cannot be generated from each reference cell, and data determination of a memory cell cannot be performed accurately. Therefore, in the conventional configuration, the verify function is still indispensable for the erasing operation / writing operation in order to ensure the accuracy of reading, and it cannot be applied to a nonvolatile memory not equipped with the same function.
[0018]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile memory control method and a nonvolatile memory that can accurately perform a read operation without requiring a verify operation. It is in.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a pair of reference cells connected to the same word line as the plurality of memory cells are written or erased for each of the plurality of memory cells. In each operation, complementary data is inverted and written so that the polarity of the data currently written in the pair of reference cells is opposite to that of the data currently written. Then, for each read operation of the plurality of memory cells, a read reference current is generated so as to have a substantially intermediate value between the read currents read from the pair of reference cells. Therefore, the threshold value of each reference cell is prevented from shifting in only one direction for each erase / write operation, and the write state of the memory cell can be accurately reflected on each reference cell. Therefore, it is possible to sufficiently ensure the accuracy of the read operation while eliminating the need for the verify operation.
[0020]
According to the second aspect of the present invention, the read reference current is a first reference current read from a reference cell of data “0” and a second reference current read from a reference cell of data “1” is a constant j. (Where 0 <j <1) is generated as a sum current with a current multiplied by 0 <j <1). Therefore, by setting the value of the constant j, it is possible to generate a read reference current having a substantially intermediate value between the first and second reference currents.
[0021]
According to the third aspect of the present invention, prior to a write operation of the pair of reference cells, data currently written to the pair of reference cells is read, and the polarity of each data is determined based on the determination result. Data to be written to a pair of reference cells is generated. Therefore, data is inverted and written into the pair of reference cells every time the write operation is performed.
[0022]
According to the invention as set forth in claim 4, prior to generation of the read reference current, the pair of reference cells are set such that a ratio of each read current read from the pair of reference cells becomes a predetermined target value. The voltage applied to the word line connected to the reference cell or the voltage applied to the source line connected to the pair of reference cells is adjusted. Therefore, a stable read operation can be performed while increasing the ratio of the read currents, regardless of the distribution of the threshold value of the pair of reference cells (the threshold value is distributed high / the threshold value is distributed low).
[0023]
According to the fifth aspect of the present invention, when the threshold value of the pair of reference cells is low, the read current of each reference cell is reduced by increasing the voltage applied to the source line to achieve the target. It can be close to the ratio.
[0024]
According to the invention described in claim 6, when the threshold value of the pair of reference cells is high, the read current of each reference cell is increased by increasing the voltage applied to the word line, and is targeted. It can be close to the ratio.
[0025]
According to the seventh aspect of the present invention, the reference cell read circuit reads the data of the pair of reference cells for each erase operation or write operation of a plurality of memory cells, determines the polarity of each data, and determines the polarity signal. Is output. The reference cell write data generating circuit, based on the polarity signal, mutually complementary data to be written to the pair of reference cells so that the data has the opposite polarity to the data currently written to the pair of reference cells. Generate The source voltage supply circuit supplies a source voltage according to data output from the reference cell write data generation circuit.
[0026]
According to the invention described in claim 8, the read reference current generation circuit includes the first and second current-voltage converters. The first current / voltage converter generates a first reference signal corresponding to the first reference current read from the reference cell of data “0”, and the second current / voltage converter generates the first reference signal of data “1”. And generates a second reference signal corresponding to the second reference current read from the second reference current. The sense amplifier generates a read reference current based on the first and second reference signals so as to have a substantially intermediate value between the first and second reference currents, and reads the read reference current and the read reference current from the memory cell. The data of the memory cell is determined by comparing the read current with the read current.
[0027]
According to the ninth aspect of the present invention, the read reference current generation circuit includes a read voltage generation unit for supplying a read voltage to the word line during a read operation, and the read voltage generation unit includes the first read voltage generation unit. A first voltage-current converter that generates a first control current that is a predetermined multiple of the first reference current based on a reference signal; and a second control that generates a second multiple of the second reference current based on the second reference signal. And a second voltage-current converter for generating a current. The read voltage generator is configured to determine a ratio between the first reference current and the second reference current to a predetermined target value based on a current difference between the first control current and the second control current. To generate a read voltage.
[0028]
According to the invention as set forth in claim 10, the read reference current generation circuit includes a source voltage generation unit for supplying a source supply power to be supplied to the source line at the time of a read operation. A voltage-current converter for generating a reference control current based on the first reference signal. The source voltage generator is configured to determine a ratio between the first reference current and the second reference current to a predetermined target value based on a current difference between the first reference current and the reference control current. Generate source supply power.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0030]
FIG. 1 is an explanatory diagram illustrating a nonvolatile memory cell according to the first embodiment.
In the present embodiment, the nonvolatile memory cell 10 is a flash memory cell having a single-layer polysilicon structure, and includes three elements of a memory transistor 11, a select transistor 12, and a MOS capacitor 13.
[0031]
As shown in FIGS. 1A to 1C, the memory transistor 11 is formed of, for example, an NMOS transistor having a floating gate 15 as a gate on a P-type substrate 14, and a source thereof is connected to a source line SL.
[0032]
The select transistor 12 is formed of an NMOS transistor (not shown in FIGS. 1B and 1C) having a select gate 16 as a gate on a substrate 14, the source of which is connected to the bit line BL, and the select gate 16 Connected to selected word line SWL. The drains of the memory transistor 11 and the select transistor 12 are connected to each other.
[0033]
The MOS capacitor 13 is formed by forming an N-type diffusion layer as a control gate 17 on a substrate 14 and forming the floating gate 15 on the control gate 17 with an insulating layer therebetween. The control gate 17 is formed in the triple well of the substrate 14 (in the P well 19 formed in the N well 18 in the figure). Control gate 17 is connected to control word line CWL. Incidentally, in the memory cell 10 having the single-layer polysilicon structure according to the present embodiment, a simple word line means the control word line CWL.
[0034]
In such a memory cell 10, in the present embodiment, the state where electrons are accumulated in the floating gate 15 (state with a high threshold) is data "0", and conversely, the state where electrons are not accumulated in the floating gate 15 (state with a threshold). It is assumed that writing is performed in such a manner that the “low state” corresponds to data “1”.
[0035]
Writing to the memory cell 10 includes two operations of erasing and programming.
Erase is an operation of extracting electrons from the floating gate 15 to lower the threshold value of the memory cell 10 (memory transistor 11). In other words, erasing is an operation of rewriting data in the memory cell 10 from data “0” to data “1”.
[0036]
As shown in FIG. 1B, in the erasing, a high voltage (for example, 6.0 V) as a first source voltage is applied to the source of the memory transistor 11, and a negative voltage (a first control voltage) is applied to the control gate 17. For example, -9.3 V) is applied. Here, the P well 19 is set to the same potential as the control gate 17 (for example, -9.3 V), and the N well 18 is set to, for example, 6.0 V.
[0037]
In this case, the potential of the floating gate 15 is reduced to about -8.2 V by capacitive coupling, and a high voltage of about 14.2 V is applied between the source and the floating gate 15. As a result, an FN tunnel current (indicated by an arrow in the figure) flows, electrons are extracted from the floating gate 15, and the threshold value of the memory cell 10 (memory transistor 11) decreases. Therefore, the memory cell 10 is rewritten from data “0” to data “1”.
[0038]
On the other hand, the program is an operation of injecting electrons into the floating gate 15 to increase the threshold value of the memory cell 10 (memory transistor 11). In other words, the program is an operation of rewriting data in the memory cell 10 from data “1” to data “0”.
[0039]
As shown in FIG. 1C, in the program, a ground voltage (0.0 V) as a second source voltage is applied to the source of the memory transistor 11 and a high voltage (for example, a second control voltage) is applied to the control gate 17. 9.5 V). Here, the P well 19 is set to the ground voltage (0.0V), and the N well 18 is set to, for example, 6.0V.
[0040]
In this case, the potential of the floating gate 15 is raised to about 11.3 V by capacitive coupling, and a high voltage of about 11.3 V is applied between the source and the floating gate 15. As a result, an FN tunnel current (indicated by an arrow in the figure) flows, electrons are injected into the floating gate 15, and the threshold value of the memory cell 10 (memory transistor 11) increases. Therefore, the memory cell 10 is rewritten from data “1” to data “0”.
[0041]
Although the present embodiment is embodied in the memory cell 10 having a single-layer polysilicon structure, the memory cell 10 has a two-layer polysilicon structure (a floating gate is electrically separated and embedded in a gate oxide film, and a floating gate and a control gate are connected to each other. (A stacked structure; also referred to as a stack type).
[0042]
Although the memory cell 10 having a single-layer structure has a larger cell area than a memory cell having a two-layer structure (stack type), it is possible to reduce the number of process steps involved in forming a single-layer polysilicon. Therefore, this structure is suitable for a small-capacity memory application and has a small ratio of the memory cell to the die size.
[0043]
Next, the principle of the writing method of the memory cell 10 of the present embodiment will be described.
As shown in FIG. 2, the memory cell array 20 is formed by arranging a plurality of memory cells 10 in an array.
[0044]
The source of each memory cell 10 is separated for each column-by-column cell, and connected to a source line SL (SL0 to SL3 in the figure). The control gate 17 of each memory cell 10 is connected to a common control word line CWL (CWL0, CWL1 in the figure) for each row-by-row cell. Note that the select transistor 12 is omitted in FIG.
[0045]
In such a memory cell array 20, writing (erasing / programming) to the memory cells 10 is performed collectively for the row-wise memory cells 10 connected to any one selected control word line CWL. .
[0046]
Explaining the principle, at the time of writing, voltages corresponding to the write data (“1” or “0”) of each memory cell 10 are supplied to the source lines SL0 to SL3. Here, the first source voltage of a high voltage (for example, 6.0 V) corresponding to the data “1” is supplied to the source lines SL1 and SL3, and the ground voltage (0) corresponding to the data “0” is supplied to the source lines SL0 and SL2. 0.0V) is supplied.
[0047]
In this state, first, a first control voltage of a negative voltage (for example, -9.3 V) is supplied to any one of the selected control word lines CWL (here, for example, CWL0). Then, in the memory cell 10 to which the first source voltage corresponding to the write data "1" is applied to the source, a tunnel current flows, electrons are extracted from the floating gate 15, and erased (see FIG. 1B). ). That is, the memory cell 10 to which the second source voltage corresponding to the write data “0” is applied to the source is not erased.
[0048]
Next, a second control voltage of a high voltage (for example, 9.3 V) is supplied to the control word line CWL0 while maintaining the respective voltages supplied to the source lines SL0 to SL3.
[0049]
Then, in the memory cell 10 in which the second source voltage corresponding to the write data "0" is applied to the source, a tunnel current flows, electrons are injected into the floating gate 15, and the memory cell 10 is programmed (see FIG. 1C). ). That is, the memory cell 10 to which the first source voltage corresponding to the write data “1” is applied to the source is not programmed.
[0050]
Therefore, in such a method, all of the sources connected to the same control word line CWL0 are preliminarily determined based on the voltages supplied to the source lines SL0 to SL3 in accordance with the write data ("1" or "0"). Writing (erase / program) is performed on the memory cell 10 at a time.
[0051]
Hereinafter, the configuration of the nonvolatile memory of the present embodiment will be described in detail.
FIG. 3 is a block diagram showing a schematic configuration of a flash memory (nonvolatile memory), and FIG. 4 is a block diagram showing a detailed configuration thereof. FIG. 4 shows some memory cells 10 connected to one control word line CWL.
[0052]
The flash memory 30 includes the memory cell array 20, first to third voltage generation circuits 31 to 33, an address control circuit 34, an X decoder 35, a Y decoder 36, a write driver 37, a reference control circuit 38, a Y pass gate 39, and a read. It includes an amplifier 40 and a read / write control circuit 41.
[0053]
In the memory cell array 20, the above-mentioned plurality of memory cells 10 are arranged in an array, and a pair of reference cells 10a and 10b (see FIG. 4) are arranged for each row-by-row cell. The reference cells 10a and 10b are cells for generating a current serving as a reference for determining read data when reading the memory cell 10.
[0054]
The first voltage generating circuit 31 is a negative voltage generating circuit, and generates a negative voltage (for example, -9.3 V in the present embodiment) as a first control voltage to be supplied to the control word line CWL to generate an X decoder 35. To supply.
[0055]
The second voltage generating circuit 32 is a high voltage generating circuit that generates a high voltage (for example, 9.5 V in the present embodiment) as a second control voltage to be supplied to the control word line CWL and outputs the generated high voltage to the X decoder 35. Supply.
[0056]
The third voltage generating circuit 33 is a high voltage generating circuit that generates a high voltage (for example, 6.0 V in this embodiment) as a first source voltage to be supplied to the source line SL and supplies it to the write driver 37. I do.
[0057]
The first to third voltage generation circuits 31 to 33 are driven by an oscillator 42 and generate the respective voltages based on a reference voltage supplied from a reference voltage generation circuit 43.
[0058]
The address control circuit 34 includes an address buffer 34a and an address counter 34b.
The address buffer 34a takes in the externally supplied write address WD-ADDR in byte units [0: 7] and outputs it to the X decoder 35 and the Y decoder 36, respectively.
[0059]
More specifically, the address buffer 34a outputs the upper 5 bits of the write address WD-ADDR used for selecting the control word line CWL at the time of writing to the X decoder 35 as a row address. X decoder 35 decodes the selected word and selects one of the plurality of control word lines CWL.
[0060]
The address buffer 34a outputs the lower three bits of the write address WD-ADDR used for selecting the source line SL at the time of writing to the Y decoder 36 as a column address. The Y decoder 36 decodes the data, takes in the write data in corresponding source voltage supply circuits 44, 45a, 45b (see FIG. 4) in a write driver 37 described later, and outputs a decode signal for setting the source voltage. Generate.
[0061]
The address counter 34b generates a 3-bit internal address for selecting the memory cell 10 corresponding to the 8-bit read data R-MDATA [0: 7] on a bit-by-bit basis. Therefore, the Y decoder 36 sequentially selects the memory cells 10 to be read based on the address output from the address counter 34b, and stores the 1-bit read data read by the read amplifier 40 into a read data latch (not shown). 8 bits).
[0062]
The reference control circuit 38 includes a reference cell read circuit 46, a reference cell write data generation circuit 47, and a reference cell Y decoder 48.
The reference cell reading circuit 46 reads the data written in the two reference cells 10a and 10b, respectively, via the bit lines BLref (0) and BLref (1) connected thereto, and determines the polarity of each data. judge.
[0063]
More specifically, at the time of writing to the memory cell 10, data “0” and data “1” are written to the reference cells 10a and 10b, respectively, so as to have inverted polarities. Prior to writing to the memory cell 10, the reference cell read circuit 46 latches data read from each of the reference cells 10a and 10b, determines which data "1" is written, and determines the polarity of the data. Output the indicated polarity signal REF-REV.
[0064]
Based on the polarity signal REF-REV from the reference cell read circuit 46, the reference cell write data generation circuit 47 performs writing to each of the reference cells 10a and 10b with a polarity opposite to that of the currently written data. As described above, the reference cell write data WDBref (0) and WDBref (1) are generated.
[0065]
Therefore, data is written into the reference cells 10a and 10b so that the polarity is opposite to the current data every time the memory cell 10 is written. The reason for inverting the data every time it is written is that it is desirable to keep the distribution of the threshold values of the reference cells 10a and 10b for generating the reference current within a predetermined range.
[0066]
The reference cell Y decoder 48 decodes the data ("1" or "0") currently written in the reference cells 10a and 10b based on the polarity signal REF-REV from the reference cell read circuit 46. The signals YD0ref (0) and YD0ref (1) are generated.
[0067]
The write driver 37 includes source voltage supply circuits 44, 45a, and 45b corresponding to source lines SL connected to the cells (memory cells 10, reference cells 10a, 10b) in the column direction, respectively. I have. The source voltage supply circuits 44, 45a, and 45b have the same configuration.
[0068]
More specifically, the source voltage supply circuits 44 are provided corresponding to the source lines SL connected to the memory cells 10, respectively, and write the write data W-MDATA externally supplied in byte units [0: 7]. The address is fetched based on the result of decoding the address by the Y decoder 36. Then, the first or second source voltage corresponding to the captured data (“0” or “1”) is supplied to the source line SL.
[0069]
The source voltage supply circuits 45a and 45b are provided corresponding to the source lines SL connected to the reference cells 10a and 10b, respectively, and the reference cell write data WDBref (0) supplied from the reference cell write data generation circuit 47. , WDBref (1) (data having polarities opposite to each other). Then, the first or second source voltage corresponding to the captured data (“0” or “1”) is supplied to each source line SL.
[0070]
The Y pass gate 39 includes a Y selection gate 49 and a reference cell Y selection gate 50.
The Y selection gate 49 selects any one of the plurality of bit lines BL at the time of reading, and outputs a read signal RDB read from the memory cell 10 via the bit line BLx.
[0071]
The reference cell Y selection gate 50 decodes each bit line BLref (0), BLref (1) based on the decode signals YD0ref (0), YD0ref (1) from the reference cell Y decoder 48, and A read signal RDBref (0) from the reference cell of “0” and a read signal RDBref (1) from the reference cell of data “1” are output.
[0072]
The read amplifier 40 includes a read reference current generation circuit 51 and a sense amplifier 52.
The read reference current generation circuit 51 receives the read signals RDBref (0) and RDBref (1) output from the reference cell Y selection gate 50, and reads the read current (first reference current) of the reference cell of data “0”. ) And a second reference signal SAref, which is a read current (second reference current) of a reference cell of data “1”.
[0073]
The sense amplifier 52 compares a read reference current generated based on the first and second reference signals SAref0 and SAref with a read current generated based on a read signal RDB output from the Y selection gate 49. Then, it determines whether the data of the memory cell 10 is “1” or “0” based on the comparison result, and outputs read data RDATAB.
[0074]
The X decoder 35 includes a word line applied voltage selection circuit 53 and a word line driver 54.
The word line applied voltage selection circuit 53 selects and outputs an applied voltage VCWL supplied to the control word line CWL. Specifically, at the time of erasing, the first control voltage of the negative voltage supplied from the first voltage generating circuit 31 is selected, and at the time of reading, the read voltage VCWL-RD supplied from the read reference current generating circuit 51 is selected. And outputs it to the word line driver 54.
[0075]
At the time of writing, the word line driver 54 selects one of the control word lines CWL based on the result of decoding the write address WD-ADDR by the Y decoder 36. Then, a first control voltage of a negative voltage is supplied at the time of erasing, a second control voltage of a high voltage generated by the second voltage generating circuit 32 is supplied at the time of programming, and a read voltage VCWL-RD is supplied at the time of reading.
[0076]
Further, at the time of reading, one of the selected word lines SWL connected to the memory cell 10 to be read and a reference cell for data determination are read based on the decoding result of a read address (not shown). One of the reference cell selection word lines SWLref connected to 10a and 10b is selected.
[0077]
Writing / reading of the memory cell 10 and the reference cells 10a and 10b as described above is controlled by the read / write control circuit 41.
More specifically, at the time of writing, the read / write control circuit 41 shifts to a write operation in response to a write mode signal WRITE-MODE, and captures the write data W-MDATA in response to a data transfer signal WRITE-MDATA. Start.
[0078]
Then, after fetching all the data of the memory cell 10 to be written, writing to the memory cells 10 connected to the same control word line CWL is started collectively in response to the write start signal WRITE-START.
[0079]
On the other hand, at the time of reading, the read / write control circuit 41 starts reading in response to the read request signal RD-REQ. Then, the read data R-MDATA read from the memory cell 10 to be read is output from the read amplifier 40 in byte units [0: 7].
[0080]
Hereinafter, details of each circuit will be described.
FIG. 5 is a circuit diagram of the memory cell 10. The description of the same components as those in FIG. 1 described above is omitted. The reference cells 10a and 10b have the same configuration as the memory cell 10.
[0081]
To the source of the memory cell 10 (memory transistor 11), a corresponding source voltage ARVSS is supplied from a source voltage supply circuit 44 via a source line SL at the time of writing / reading.
[0082]
The floating gate potential FG is set to around 3.0 V for data “1” and around 0.0 V for data “0” according to the data written in the memory cell 10. The N-well potential VNW is set to, for example, 6.0 V at the time of writing. The P-well potential VPW is set to the same potential as the control gate at the time of erasing and to the ground potential at the time of programming according to the time of erasing / programming.
[0083]
FIG. 6 is a circuit diagram showing a configuration example of the memory cell array 20.
As described above, the memory cell array 20 is configured by arranging a plurality of memory cells 10 each including the memory transistor 11, the select transistor 12, and the MOS capacitor 13.
[0084]
In the present embodiment, a bit line BL (BL0, BL1, BL2 in the figure) is shared between two memory cells 10 (Ce0a, Ce0b, Ce1a, Ce1b, Ce2a, Ce2b in the figure) adjacent in the column direction. ing.
[0085]
In each memory cell 10, the source lines SL (SL0a to SL2a and SL0b to SL2b in the drawing) are separated for each column unit, and the same control word line CWL (CWL0 to CWL2 in the drawing) for each row unit. )It is connected to the.
[0086]
In each of the memory cells 10 for each row, one of the two cells sharing the bit line BL with each other (the cell on the Ce0a, Ce1a, and Ce2a side in the figure) is connected to the first selected word line. Are connected to the same selected word line SWL (SWL0a to SWL2a in the figure). The other cells (cells on the Ce0b, Ce1b, and Ce2b side in the figure) are connected to the same selected word line SWL (SWL0b to SWL2b in the figure) as a second selected word line.
[0087]
Here, one of the first and second selected word lines (Ce0a, Ce0b, Ce1a, Ce1b, Ce2a, Ce2b) connected to the memory cells 10 on each of the control word lines CWL0 to CWL2 is read. Is selected (activated).
[0088]
Therefore, in each of the two memory cells 10 sharing the bit lines BL0, BL1, and BL2 with each other, only the select transistor 12 of one of the two cells is turned on to read data, and the other cell ( In a non-selected cell, the select transistor 12 is turned off so that a read current does not flow.
[0089]
Although not shown in FIG. 6, as described above, the memory cell array 20 is provided with a pair of reference cells 10a and 10b to which complementary data is written for each control word line CWL (CWL0 to CWL2). Each of the reference cells 10a and 10b is connected to the same selected word line SWLref (see FIG. 4).
[0090]
FIG. 7 is a circuit diagram showing a configuration example of the source voltage supply circuit 44. The source voltage supply circuits 45a and 45b provided corresponding to the reference cells 10a and 10b have the same configuration.
[0091]
The source voltage supply circuit 44 includes a latch circuit 44a, and takes in the data WDBj obtained by inverting the write data W-MDATA supplied from the outside based on a decode signal YTi from the Y decoder 36 which decodes the write address WD-ADDR. , Latched by the latch circuit 44a.
[0092]
The output signal of the latch circuit 44a is input to the gates of the transistor Tp1 (PMOS transistor) and the transistor Tn1 (NMOS transistor). The source of the transistor Tp1 is connected to the power supply VS, and the source of the transistor Tn1 is connected to the source supply power ARGND (ground voltage in the present embodiment).
[0093]
A transistor Tp2 (PMOS transistor) is interposed in series between the transistors Tp1 and Tn1, and a reference voltage ARVREF is input to the gate of the transistor Tp2. The source voltage ARVSS is output from the connection point between the transistors Tp2 and Tn1.
[0094]
The power supply VS is set to, for example, 3.0 V when the data WDBj is taken in by the latch circuit 44a, and at the time of writing (after the data WDBj is latched), the high voltage generated by the third voltage generating circuit 33 (for example, 6.V). 0V). The transistor Tp2 controls the amount of current flowing to the memory cell 10 at the time of writing based on the reference voltage ARVREF.
[0095]
In this configuration, the source voltage supply circuit 44 supplies the source voltage ARVSS corresponding to the data WDBj (inverted signal) taken into the latch circuit 44a. That is, when the taken data WDBj is data "0", a high-voltage first source voltage (power supply VS in the figure) is supplied. (Source power supply ARGND in the figure).
[0096]
FIG. 8 is a circuit diagram showing a configuration example of the reference cell read circuit 46, and FIG. 9 is an operation waveform diagram thereof.
Reference cell read circuit 46 includes a latch circuit 46a and data output circuits 46b and 46c.
[0097]
One node a of the latch circuit 46a is connected to the bit line BLref (0) via the transistor Tn2 (NMOS transistor) and to the data output circuit 46b. The other node b of the latch circuit 46a is connected to the bit line BLref (1) via the transistor Tn3 (NMOS transistor) and to the data output circuit 46c.
[0098]
Each of the transistors Tn2 and Tn3 is formed of a transistor having a low threshold, and a gate thereof is supplied with a bias signal NBIAS when reading the reference cells 10a and 10b. (Hereinafter, transistors for which similar threshold values are set are similarly shown in the drawings).
[0099]
A power supply VC-CAM and a source supply power supply ARGND are supplied to the latch circuit 46a. The latch circuit 46a reads the potentials of the nodes a and b based on the latch signal LATCH, that is, the potentials read from the reference cells 10a and 10b. Latch complementary read data.
[0100]
The read operation will be described in detail. As shown in FIG. 9, the reference cell read circuit 46 first releases the latch state of the latch circuit 46a in accordance with the latch signal LATCH. Next, the selected word line SWLref (see FIG. 4) connected to the reference cells 10a and 10b is selected (activated), and at the same time, the data output circuits 46b and 46c are deactivated based on the control signal RDcam.
[0101]
Next, the nodes a and b are equalized (equal potentials) based on a short signal SRT for short-circuiting the drains of the transistors Tn2 and Tn3, and then released, thereby reading the reference cells 10a and 10b. Amplify the data. That is, a potential difference is gradually generated between the nodes a and b due to the read current of the reference cells 10a and 10b flowing through the bit lines BLref (0) and BLref (1).
[0102]
Thereafter, the read data of each of the reference cells 10a and 10b latched in the latch circuit 46a by the latch signal LATCH is converted into a decision signal DB-CAM (polarity signal REF-REV) and D-CAM based on the control signal RDcam, respectively. Output from 46b and 46c.
[0103]
The reference cell reading circuit 46 reads data from each of the reference cells 10a and 10b prior to writing into the memory cell 10. This is because, as described above, the data in each of the reference cells 10a and 10b is inverted and written each time the memory cell 10 is written.
[0104]
FIG. 10 is a circuit diagram showing one configuration example of the reference cell write data generation circuit 47. The reference cell write data generation circuit 47 responds to the control signal WM at the time of writing to the memory cell 10 so that the polarity of the data is opposite to that of the data currently written in the reference cells 10a and 10b. The reference cell write data WDBref (0) and WDBref (1) are generated based on the signal REF-REV.
[0105]
The generator 47 generates a decode signal YT-REF in response to the control signal WS, and outputs the decode signal YT-REF to the source voltage supply circuits 45a and 45b. Therefore, at the time of writing, each of the source voltage supply circuits 45a and 45b takes in data having polarities opposite to those of the data currently written in the reference cells 10a and 10b.
[0106]
FIG. 11 is a circuit diagram showing a configuration example of the reference cell Y decoder 48.
The reference cell Y decoder 48 responds to a control signal RDmem which becomes active at the time of reading, and a decode signal YD0ref (0) based on the polarity signal REF-REV (data currently written in each of the reference cells 10a and 10b). , YD0ref (1) are generated and output to the reference cell Y selection gate 50.
[0107]
Note that a circuit 48a shown by a broken line in the figure is provided corresponding to a test mode for testing the read current of the reference cells 10a and 10b, and switching between the test mode and the normal mode (during normal reading) is performed by the control signal SEL. Performed based on -REF. In the test mode, decode signals YD1ref (0) and YD1ref (1) are generated based on input signals YD0 (0) and YD0 (1) supplied from outside.
[0108]
FIG. 12 is a circuit diagram showing a configuration example of the reference cell Y selection gate 50.
The reference cell Y selection gate 50 includes selection circuits 50a and 50b. Based on the decode signals YD0ref (0) and YD0ref (1) from the reference cell Y decoder 48, the bit lines BLref (0) and BLref ( 1), and outputs a read signal RDBref (0) of data “0” and a read signal RDBref (1) of data “1”.
[0109]
Note that a circuit 50c shown by a broken line in the figure is provided corresponding to the above-described test mode, and the decode signals YD1ref (0) and YD1ref (1) supplied from the reference cell Y decoder 48 in the test mode are provided. On the basis of this, the read signal RDBref of one of the reference cells 10a and 10b is output.
[0110]
FIG. 13 is a circuit diagram showing a configuration example of the read reference current generation circuit 51.
The read reference current generation circuit 51 includes first and second reference current generators 51a and 51b and a read voltage generator 51c.
[0111]
The first reference current generator 51a includes a first current-voltage converter 61. The converter 61 reads a reference cell read signal RDBref (0) of data “0” output from the reference cell Y selection gate 50. ), A first reference signal SAref0 having the value of the first reference current Iref0 is generated.
[0112]
The second reference current generator 51b includes a second current / voltage converter 62. The converter 62 reads the reference cell read signal RDBref (1) of data “1” output from the reference cell Y selection gate 50. ), A second reference signal SAref having the value of the second reference current Iref1 is generated.
[0113]
As described above, the read voltage generator 51c is a circuit that generates the read voltage VCWL-RD to be supplied to the control word line CWL at the time of reading. The read voltage generator 51c controls the read voltage VCWL-RD to a floating state during programming.
[0114]
In the test mode, the first and second reference current generators 51a and 51b and the read voltage generator 51c are inactive based on various test signals T-MRW and T-AC.
[0115]
FIG. 14 is a circuit diagram showing a configuration example of the Y selection gate 49.
The Y selection gate 49 is connected to an 8-bit bit line BL in the present embodiment, and via one of the bit lines BL based on decode signals YD0 [7: 0] and YD1 obtained by decoding a read address (not shown). A read signal RDB read from the memory cell 10 is output.
[0116]
More specifically, the Y selection gate 49 includes eight transistors Tn4a to Tn4h for bit selection and one transistor Tn5 (each NMOS transistor) for byte selection. Then, the Y selection gate 49 outputs a read signal RDB via one of the transistors Tn4a to Tn4h and the transistor Tn5 based on the decode signals YD0 [7: 0], YD1.
[0117]
FIG. 15 is a circuit diagram showing a configuration example of the sense amplifier 52.
The sense amplifier 52 includes a read reference current generator 52a that generates a read reference current Irefj based on the first and second reference signals SAref0 and SAref from the read reference current generator 51, and a read from the Y selection gate 49. A read current generator 52b for generating a read current Iref based on the signal RDB.
[0118]
More specifically, the read reference current generation unit 52a includes a constant current unit 71 and first to fourth constant current units 72 to 75, and based on the first reference signal SAref0 input to the constant current unit 71, Generate one reference current Iref0.
[0119]
The first to fourth constant current sections 72 to 75 differ in the size of the transistors constituting them. For example, in the present embodiment, the driving capacity of the first constant current section 72 is twice that of the second constant current section 73. , The third constant current section 74 has four times the driving capability, and the fourth constant current section 75 has the eight times driving capability.
[0120]
The read reference current generation unit 52a drives at least one of the first to fourth constant current units 72 to 75 by a plurality of selection signals TRIM-IREF [0: 3] and inputs the second constant current units 72 to 75 to the second reference current generation unit 52a. Based on the reference signal SAref, a current is generated by multiplying the second reference current Iref1 by a constant j (0 <j <1). Therefore, the read reference current generator 52a generates the read reference current Irefj as a sum current of “first reference current Iref0 + second reference current Iref1 × constant j”.
[0121]
The sense amplifier 52 thus configured compares the read reference current Irefj flowing into the node c with the read current Iref flowing from the node c to determine whether the data of the memory cell 10 to be read is “1”. It is determined whether it is “0”. That is, data detection is performed by detecting the potential (H level or L level) of the node c that changes according to the read current Iref of the memory cell 10 flowing from the node c, and read data RDATAB indicating the determination result is output.
[0122]
Note that a circuit 52c shown by a broken line in the figure is provided corresponding to the test mode, and outputs the read data RDATAB to the outside as a read signal R-ANA-OUT in the test mode.
[0123]
FIG. 16 is a circuit diagram showing one configuration example of the word line applied voltage selection circuit 53, and FIG. 17 is an operation waveform diagram thereof.
At the time of erasing, the negative voltage from the first voltage generation circuit 31 is applied to the source and back gate (P well) of the transistor Tn6 (NMOS transistor) and the back gates (P well) of the transistors Tn7 and Tn8 (NMOS transistor). (-9.3V) first control voltage R-NEGP is supplied.
[0124]
The control signal NGNDB is supplied to the gates of the transistors Tn6 and Tn7. The control signal NGNDB is generated based on a plurality of control signals RDmem, ENVPXGD, NEGPL. Here, the control signal RDmem is a signal that goes high at the time of reading, the control signal ENVPXGD is a signal that goes high at the time of programming, and the control signal NEGPL is that the first control voltage R-NEGP is equal to or lower than a predetermined voltage during erasing (for example, −3). (Less than or equal to .0 V).
[0125]
Therefore, at the time of erasing, the control signal NGNDB becomes L level (specifically, the ground voltage), and the transistors Tn6 and Tn7 are turned on based on the supply of the first control voltage R-NEGP.
[0126]
At this time, the drain potential of the transistor Tn7, that is, the control signal NEGPGND becomes substantially equal to the negative first control voltage R-NEGP, and the control signal NEGPGND turns off the transistor Tn8. Therefore, at the time of erasing, the word line applied voltage selection circuit 53 outputs the first control voltage R-NEGP of the negative voltage (−9.3 V) as the applied voltage VCWL.
[0127]
At this time, as described above, since the control signal NGNDB input to the gate of the transistor Tn6 is at the ground voltage, a high voltage exceeding the breakdown voltage is not applied between the source and the gate of the transistor Tn6.
[0128]
At the time of programming, the control signal NGNDB becomes L level (ground voltage) based on the H level control signal ENVPXGD. At this time, the first control voltage R-NEGP becomes 0 V, and the transistors Tn6 and Tn7 are turned off.
[0129]
Further, since the control signal NEGPGND becomes H level, the transistor Tn8 is turned on. At this time, the read voltage VCWL-RD is controlled by the read reference current generating circuit 51 so as to be in a floating state, and the applied voltage VCWL Becomes a floating potential (for example, about 2.5 V) as shown in FIG.
[0130]
At the time of reading, the control signal NGNDB is similarly set to the ground voltage based on the control signal RDmem, and the transistors Tn6 and Tn7 are turned off and the transistor Tn8 is turned on as at the time of programming. Therefore, at the time of reading, the word line applied voltage selection circuit 53 outputs the read voltage VCWL-RD supplied from the read reference current generation circuit 51 as the applied voltage VCWL.
[0131]
Note that a circuit 53a indicated by a broken line in the figure is provided corresponding to a test mode for measuring a read current. In the test mode, the transfer gate TG1 is turned off and the transfer gate TG2 is turned off based on the test signal T-AC. Turned on. Then, a test input signal R-ANA-IN is supplied from outside, and the input signal R-ANA-IN is output as an applied voltage VCWL.
[0132]
FIG. 18 is a circuit diagram showing a configuration example of the word line driver 54, and FIG. 19 is an operation waveform diagram thereof.
The word line driver 54 selects any one of the control word lines CWLi according to predecode signals XD0 to XD2 generated based on the write address WD-ADDR (see FIG. 3) at the time of writing (erase / program). At the time of reading, any one selected word line SWLi and any one reference cell selected word line SWLrefi are selected by decode signals YD2 and YD2ref generated based on a read address (not shown).
[0133]
The word line driver 54 includes a latch circuit 54a, to which a control signal NPS and a first control voltage R-NEGP are supplied. The latch circuit 54a latches the control signal NEN based on the control signal NENB generated by the predecode signals XD0 to XD2. Specifically, a control signal NEN having the voltage level of the control signal NPS is generated.
[0134]
As described above, the control signal NEGPL becomes L level when the first control voltage R-NEGP drops below a predetermined voltage (for example, −3.0 V or less) at the time of erasing, and the control signal NPS is changed based on the control signal NEGPL. It becomes L level (specifically, ground voltage). Therefore, the latch circuit 54a generates the control signal NEN which becomes the ground voltage based on the control signal NPS. Incidentally, at this time, since the voltage level of the control signal NGND is equal to the first control voltage R-NEGP, the latch state of the latch circuit 54a is maintained.
[0135]
The control signal NEN generated by such a latch circuit 54a is input to the gate of the transistor Tn9 (NMOS transistor) as the first transistor. The applied voltage VCWL is supplied to the source of the transistor Tn9, and the first control voltage R-NEGP of the negative voltage (-9.3V) is supplied to the back gate (P well) of the transistor Tn9.
[0136]
Therefore, at the time of erasing, the transistor Tn9 is turned on, and as shown in FIG. 19, the applied voltage VCWL (specifically, the first control voltage) is applied to any one of the control word lines CWLi selected by the predecode signals XD0 to XD2. R-NEGP) is supplied.
[0137]
At this time, as described above, since the gate voltage (control signal NEN) input to the gate of the transistor Tn9 is the ground voltage, a high voltage exceeding the breakdown voltage is not applied between the source and the gate of the transistor Tn9. Absent.
[0138]
During such an erase operation, the transistor Tn10 is turned on by the control signal NEGPL-ER, and the P-well potential VPWi (see FIG. 5) of the memory cell 10 becomes the applied voltage VCWL (-9.3 V).
[0139]
During programming, a high voltage (+9.5 V) second control voltage VPX is supplied to the word line driver 54 from the second voltage generation circuit 32. This second control voltage VPX is supplied to the source of a transistor Tp3 (PMOS transistor) as a second transistor.
[0140]
The control signal XINBT is supplied to the gate of the transistor Tp3. The control signal XINBT becomes L level during programming by the predecode signals XD0 to XD2.
[0141]
Accordingly, during programming, the transistor Tp3 is turned on, and as shown in FIG. 19, a high voltage (+9.5 V) second control voltage is applied to any one of the control word lines CWLi selected by the predecode signals XD0 to XD2. VPX is supplied.
[0142]
At this time, the transistor Tn9 is also turned on, but as described above, the applied voltage VCWL is controlled to the floating potential (for example, about 2.5 V) during programming (see FIG. 17), so that an abnormal current flows to the control word line CWLi. It does not flow.
[0143]
At the time of such a program, the transistor Tn11 is turned on by the control signal NGND, so that the P-well potential VPWi (see FIG. 5) of the memory cell 10 becomes the ground voltage.
[0144]
Next, the write operation of the flash memory 30 configured as described above will be described in detail with reference to FIG.
FIG. 20A shows an operation when data “0” is written to the memory cell 10 in which data “0” is currently written. In this case, the source of the memory cell 10 is supplied with the second source voltage of the ground voltage (0.0 V) corresponding to the data “0” to be written.
[0145]
In this state, first, a first control voltage of a negative voltage (-9.3 V) is supplied to the control word line CWL. At this time, the potential difference between the source and the floating gate is about 8.2 V, and no FN tunnel current flows. Therefore, the memory cell 10 is not erased, and the charge amount of the floating gate does not change.
[0146]
Next, while the source voltage is maintained at 0.0 V, a high voltage (+9.5 V) second control voltage is supplied to the control word line CWL. At this time, the potential difference between the source and the floating gate is about 8.2 V, and no FN tunnel current flows. Therefore, the charge amount of the floating gate does not change. Therefore, in this case, data “0” of the memory cell before writing is held.
[0147]
FIG. 20B shows an operation when data “1” is written to the memory cell 10 in which data “0” is currently written. In this case, the first source voltage of the high voltage (6.0 V) corresponding to the data “1” to be written is supplied to the source of the memory cell 10.
[0148]
In this state, first, a first control voltage of a negative voltage (-9.3 V) is supplied to the control word line CWL. At this time, a voltage of about 14.2 V is applied between the source and the floating gate, and an FN tunnel current flows. Therefore, the electrons of the floating gate are extracted, and the memory cell 10 is erased.
[0149]
Next, while the source voltage is maintained at 6.0 V, the second control voltage of a high voltage (+9.5 V) is supplied to the control word line CWL. At this time, the potential difference between the source and the floating gate is about 5.3 V, and no FN tunnel current flows. Therefore, the memory cell 10 is not programmed, and the charge amount of the floating gate does not change. Therefore, in this case, only erasing is performed, and data “0” of the memory cell before writing is rewritten to data “1”.
[0150]
FIG. 20C shows an operation when data “0” is written in the memory cell 10 in which data “1” is currently written. In this case, the source of the memory cell 10 is supplied with the second source voltage of the ground voltage (0.0 V) corresponding to the data “0” to be written.
[0151]
In this state, first, a first control voltage of a negative voltage (-9.3 V) is supplied to the control word line CWL. At this time, the potential difference between the source and the floating gate is about 5.3 V, and no FN tunnel current flows. Therefore, the charge amount of the floating gate does not change.
[0152]
Next, while the source voltage is maintained at 0.0 V, a high voltage (+9.5 V) second control voltage is supplied to the control word line CWL. At this time, a voltage of about 11.3 V is applied between the source and the floating gate, and an FN tunnel current (between the source and the channel) flows. Accordingly, electrons are injected into the floating gate, and the memory cell 10 is programmed. Therefore, in this case, only programming is performed, and data “1” of the memory cell before writing is rewritten to data “0”.
[0153]
FIG. 20D shows an operation when data “1” is written in the memory cell 10 in which data “1” is currently written. In this case, the first source voltage of the high voltage (6.0 V) corresponding to the data “1” to be written is supplied to the source of the memory cell 10.
[0154]
In this state, first, a first control voltage of a negative voltage (-9.3 V) is supplied to the control word line CWL. At this time, a voltage of about 11.3 V is applied between the source and the floating gate, and a small amount of FN tunnel current flows (actually, almost no flow). Therefore, the charge amount of the floating gate does not substantially change.
[0155]
Next, while the source voltage is maintained at 6.0 V, the second control voltage of a high voltage (+9.5 V) is supplied to the control word line CWL. At this time, the potential difference between the source and the floating gate is about 5.6 V, and no FN tunnel current flows. Therefore, the memory cell 10 is not programmed, and the charge amount of the floating gate does not change. Therefore, in this case, data “1” of the memory cell before writing is held.
[0156]
Next, the characteristics of the reference cells 10a and 10b of the present embodiment will be described in detail.
FIG. 21 is an explanatory diagram of a read reference current generated from each of the reference cells 10a and 10b.
[0157]
As described above, the read reference current Irefj is the first reference current Iref0 which is the read current of the reference cell to which the data “0” is written, and the read current of the reference cell to which the data “1” is written. It is generated as a sum current with a current obtained by multiplying the second reference current Iref1 by a constant j (0 <j <1).
[0158]
More specifically, the read reference current Irefj is larger than the read current k1 of the cell having the lowest threshold Vth among the plurality of memory cells 10 of data “0” ((a) in the figure), and the data “1”. Are generated so as to be smaller than the read current k2 of the cell having the highest threshold value Vth ((b) in the figure).
[0159]
At this time, the write state of the memory cell 10 of data “0” corresponding to the condition (a) in the drawing corresponds to that of the reference cell in which the data “0” is currently written among the reference cells 10a and 10b. . The write state of the memory cell 10 of the data “1” corresponding to the condition (b) in the drawing corresponds to that of the reference cell in which the data “1” is currently written among the reference cells 10a and 10b.
[0160]
This is because, as described above, each of the reference cells 10a and 10b is rewritten by inverting the data so that the data has the opposite polarity each time the data is written. Because there is.
[0161]
Accordingly, the reference cell of the data “0” has a threshold distribution similar to that of the memory cell 10 having a lower threshold Vth among all the memory cells 10 of the data “0” ((c) in the figure), and the reference cell of the data “1”. The cells have the same threshold distribution as the memory cells 10 having the higher threshold Vth among all the memory cells 10 of data "1" ((d) in the figure).
[0162]
That is, by inverting the data of the reference cells 10a and 10b every writing, the threshold value Vth of the reference cell of data "0" gradually increases every writing, or conversely, the reference cell of data "1" Is prevented from gradually decreasing every time writing is performed.
[0163]
In each of the reference cells 10a and 10b, it is possible to accurately reflect the writing state of the memory cell 10 (cell deterioration, power supply, temperature, process conditions, and the like) at that time. In other words, the rewrite characteristics and the storage retention characteristics of the memory cell 10 and the reference cells 10a and 10b can be made substantially the same.
[0164]
In such a pair of reference cells 10a and 10b, in the present embodiment, the read reference current Irefj is set to be substantially the intermediate value of the read current of each of the reference cells 10a and 10b, that is, the value of the constant j is set to 0.5. (E in the figure). Then, the data of the memory cell 10 is determined based on the read reference current Irefj.
[0165]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The memory cell array 20 is provided with a pair of reference cells 10a and 10b for each same control word line CWL to which the plurality of memory cells 10 are connected. Complementary data is written to each of the reference cells 10a and 10b, and each data is inverted and rewritten so as to have the opposite polarity each time the memory cell 10 is erased / written. Therefore, the threshold value of each of the reference cells 10a and 10b is prevented from shifting in only one direction for each erase / write, and the write state of each memory cell 10 can be accurately reflected on each of the reference cells 10a and 10b. As a result, it is not necessary to perform a verify operation for monitoring whether or not the threshold values of the reference cells 10a and 10b are within an appropriate range, but it is possible to sufficiently ensure the accuracy of the read operation.
[0166]
(2) In the present embodiment, the data of the memory cell 10 is determined based on the read reference current Irefj generated from the pair of reference cells 10a and 10b whose data are inverted each time the memory cell 10 is erased / written. You. With this configuration, the verify operation can be made unnecessary, and the pre-program operation can be made unnecessary. Therefore, it is possible to shorten the time until the erase operation / write operation is completed.
[0167]
(3) Since the pre-program operation and the verify operation are unnecessary, the subsequent re-erase operation / write operation is naturally unnecessary. Therefore, it is possible to shorten the time until the erase operation / write operation is completed.
[0168]
(4) Since the pre-program operation and the verify operation are not required, the power consumption associated therewith can be reduced.
(5) Since the pre-program operation and the verify operation are not required, the layout area associated with them can be reduced, and the die size can be reduced.
[0169]
(6) Since the memory cell 10 and the reference cells 10a and 10b of the present embodiment have a single-layer polysilicon structure, the number of process steps can be reduced when the memory cell 10 is used for a small-capacity memory. it can.
[0170]
(7) By using the memory cell 10 having the select transistor 12 and the reference cells 10a and 10b, it is possible to reliably prevent a current from flowing to a cell to be read out (a cell in which the select transistor 12 is turned off) at the time of reading. can do. Therefore, the reading operation can be performed accurately.
[0171]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
In the present embodiment, as shown in FIG. 23, the read control in the case where the threshold values of the reference cells 10a and 10b (that is, the threshold values of the memory cells 10) are distributed at a higher level will be described.
[0172]
Here, when the read voltage VCWL-RD applied to the control word line CWL is, for example, at the ground voltage level (0 V), the reference cell for data “1” is turned on, but the reference cell for data “0” is turned on. Assume a situation where it is not turned on.
[0173]
In this case, it is necessary to adjust the read current of the data “0” to a predetermined value or more so that a small amount of current flows to the reference cell of the data “0”. At this time, specifically, the ratio n between the read current of data "0" (first reference current Iref0) and the read current of data "1" (second reference current Iref1) becomes a predetermined target value. Then, the currents of the first reference current Iref0 and the second reference current Iref1 are increased.
[0174]
Here, when the current value of the second reference current Iref1 is k, the ratio n is
n = Iref1 / Iref0 = k / (k / n)
(Where n is a natural number), and the larger the ratio n, the more stable the reading operation can be performed.
[0175]
Hereinafter, a specific configuration for adjusting the first reference current Iref0 will be described.
FIG. 22 is a circuit diagram showing the read reference current generation circuit 81 of the present embodiment.
The generation circuit 81 is obtained by partially changing the configuration of the above-described read reference current generation circuit 51 (FIG. 13), and the same components are denoted by the same reference numerals.
[0176]
The read reference current generation circuit 81 generates a first reference current generator 51a that generates a first reference signal SAref0 corresponding to the first reference current Iref0, and a second reference signal SAref that generates a second reference signal SAref corresponding to the second reference current Iref1. It includes a two-reference current generator 51b and a read voltage generator 81a that generates a read voltage VCWL-RD. The read voltage generator 81a includes a first voltage / current converter 91 and a second voltage / current converter 92.
[0177]
The first voltage-to-current converter 91 receives the first reference signal SAref0 output from the first reference current generator 51a. For example, in the present embodiment, the first voltage-to-current converter 91 becomes twice as large as the first reference current Iref0. Generates a first control current I0p.
[0178]
The second voltage-to-current converter 92 receives the second reference signal SAref output from the second reference current generator 51b. For example, in the present embodiment, the second voltage-to-current converter 92 outputs a current value that is 2/16 times the second reference current Iref1. To generate the second control current I1p.
[0179]
Note that the current value of the first control current I0p generated by the first voltage-to-current converter 91 and the current value of the second control current I1p generated by the second voltage-to-current converter 92 are the values of the target ratio n. It is set according to.
[0180]
The read voltage generator 81a having the first and second voltage-current converters 91 and 92 provides a current difference between the second control current I1p and the control current I0n flowing as the current mirror current of the first control current I0p. Generates and outputs a read voltage VCWL-RD having a voltage level corresponding to.
[0181]
More specifically, as shown in FIG. 24, when the read operation is started in response to the H-level control signal en (L-level control signal enb), the read voltage generator 81a outputs the ground voltage level (0 V). The read voltage VCWL-RD is output, and in response to this, only the reference cell of data “1” is turned on in this embodiment (time t1).
[0182]
At this time, a read current (second reference current Iref1) for data "1" flows, and a second control current I1p having a current value that is 2/16 times the second reference current Iref1 is generated. The read voltage VCWL-RD is gradually increased from the ground voltage (0 V) by the second control current I1p, and when the voltage level is increased to the threshold voltage level of the reference cell of data “0”, the data “0” is read. Is turned on (time t2).
[0183]
At this time, a read current (first reference current Iref0) for data “0” flows, and a control current I0n (= first control current I0p) having a current value twice as large as the first reference current Iref0 is generated. The read voltage VCWL-RD is output at a voltage level corresponding to the current difference between the control currents I1p and I0n. When the current values of the control currents I1p and I0n become equal (time t3), the rise of the read voltage VCWL-RD stops, and the voltage level is maintained.
[0184]
Therefore, in the present embodiment, even when the threshold value Vth of each of the reference cells 10a and 10b is distributed high, a (small) current equal to or more than a predetermined value corresponding to the target ratio n is used as the reference value of the data "0". By increasing the read voltage VCWL-RD applied to the control word line CWL so as to flow through the cells, a stable read operation can be performed.
[0185]
(Third embodiment)
Hereinafter, a third embodiment of the invention will be described with reference to FIGS.
In the present embodiment, as shown in FIG. 26, the read control in the case where the thresholds of the reference cells 10a and 10b (that is, the thresholds of the memory cells 10) are distributed lower is described.
[0186]
In this case, when the read voltage VCWL-RD applied to the control word line CWL is, for example, at the ground voltage level (0 V), the current flowing through the reference cell of data “0” is too large, so that the read operation is stabilized. Suppose a situation that cannot be performed.
[0187]
In this case, the ratio n (= Iref1 / Iref0 = k / (k / n)) between the first reference current Iref0 and the second reference current Iref1 described in the second embodiment is an extremely small value. . Therefore, the read current (first reference current Iref0) for data "0" is reduced to a predetermined value or less so that the ratio n increases to the target value.
[0188]
Hereinafter, a specific configuration for adjusting the first reference current Iref0 will be described.
FIG. 25 is a circuit diagram showing a read reference current generation circuit 101 according to the third embodiment. The generation circuit 101 is obtained by partially changing the configuration of the above-described read reference current generation circuit 51 (FIG. 13), and the same components are denoted by the same reference numerals.
[0189]
The read reference current generation circuit 101 includes a first reference current generation unit 51a that generates a first reference signal SAref0 according to the first reference current Iref0, and a second reference signal SAref that generates a second reference signal SAref according to the second reference current Iref1. It includes a two-reference current generator 51b, a read voltage generator 51c that generates a read voltage VCWL-RD, and a source voltage generator 101a.
[0190]
The first reference current generator 51a generates a control current I1p0 based on the first reference current Iref0, and generates a first reference signal SAref0 based on the control current I1p0 flowing into the node d and the first reference current Iref0 flowing out of the node d. Generate
[0191]
The source voltage generation unit 101a includes a voltage-current conversion unit 111, and a voltage level (potential of the node d) of the first reference signal SAref0 is input to a gate between the voltage-current conversion unit 111 and a ground power supply. The transistor Tn12 (NMOS transistor) is connected in series.
[0192]
The voltage-current converter 111 receives the voltage level of the first reference signal SAref0 (potential of the node d) and generates a reference control current I1p1 having the same current value as the control current I1p0. The reference control current I1p1 (= control current I1p0) is set according to the target value of the ratio n. For example, in the present embodiment, the current value is 1/16 times the second reference current Iref1. Is set to
[0193]
Such a source voltage generation unit 101a supplies each of the source voltage supply circuits 44, 45a, and 45b (FIG. 4) based on a control signal arc generated according to the voltage level of the first reference signal SAref0 (potential of the node d). Generate the source power supply ARGND to be supplied to the
[0194]
More specifically, as shown in FIG. 27, immediately after the read operation is started in response to the H-level control signal en (L-level control signal enb) (time t1), the read current of data “0” ( When the first reference current Iref0) is larger than the control current I1p0, the voltage level of the first reference signal SAref0 (potential of the node d) becomes 0V.
[0195]
At this time, since the transistor Tn12 is turned off, the control signal arc becomes H level, and the voltage level of the source power supply ARGND is gradually raised. That is, the voltage supplied to the source line SL via each of the source voltage supply circuits 44, 45a, 45b (see FIG. 4) is raised, whereby the read current (first reference current Iref0) for data "0" is gradually increased. To decrease.
[0196]
When the first reference current Iref0 decreases to a current amount substantially equal to the control current I1p0, the voltage level of the first reference signal SAref0 (potential of the node d) starts to increase (time t2), and the potential of the node d becomes the threshold value of the transistor Tn12. When the voltage reaches the voltage level, the transistor Tn12 is turned on, and the voltage level of the control signal arc starts to decrease (time t3). Then, when the amount of the first reference current Iref0 and the amount of the control current I1p0 become equal (time t4), the rise of the source power supply ARGND stops, and the voltage level is maintained.
[0197]
Therefore, in the present embodiment, even when the threshold value Vth of each of the reference cells 10a and 10b is distributed low, a current equal to or less than a predetermined value corresponding to the target ratio n flows to the reference cell of data "0". By raising the source supply power ARGND applied to the source line SL as described above, a stable read operation can be performed.
[0198]
Each of the above embodiments may be implemented in the following manner.
In each embodiment, at the time of writing, a first negative control voltage is first applied to the control word line CWL, and then a second high control voltage is applied to the control word line CWL. Is also good. That is, after the program is executed by applying the second control voltage of a high voltage, the erase may be performed by applying the first control voltage of the negative voltage.
[0199]
In each of the embodiments, the memory cell 10 has a single-layer polysilicon structure. However, the memory cell 10 may have a two-layer polysilicon structure (stack type) having no selected word line. Incidentally, in the stack type memory cell, only one word line (selected word line) connected to the control gate shares the control word line CWL and the selected word line SWL of the present embodiment.
[0200]
In each embodiment, the memory cell 10 having the single-layer polysilicon structure may be a cell having a two-element structure without the select transistor 12.
In each of the embodiments, all the memory cells 10 connected to the same control word line CWL are collectively written as write targets, but they may be selectively written.
[0201]
In each embodiment, a circuit having both the function of the read reference current generation circuit 81 in the second embodiment and the function of the read reference current generation circuit 101 in the third embodiment may be provided.
[0202]
In the second embodiment, when the threshold values of the reference cells 10a and 10b are distributed high, the read voltage supplied to the control word line CWL until the read current of data "0" becomes a value corresponding to the target ratio n Although the control for raising the VCWL-RD is performed, the control for lowering the source supply power ARGND supplied to the source line SL may be performed.
[0203]
In the third embodiment, when the thresholds of the reference cells 10a and 10b are distributed low, the source supply power supplied to the source line SL until the read current of the data “0” becomes a value corresponding to the target ratio n. Although the control for raising the ARGND is set, the control for lowering the read voltage VCWL-RD supplied to the control word line CWL may be performed.
[0204]
The features of each of the above embodiments are summarized as follows.
(Supplementary Note 1) A method of controlling a nonvolatile memory in which a plurality of memory cells and a pair of reference cells are connected to the same word line,
For each erase operation or write operation of the plurality of memory cells, data complementary to each other is written to the pair of reference cells so that the data has the opposite polarity to the data currently written to the pair of reference cells. One step,
A second step of generating a read reference current such that the read reference current is substantially an intermediate value between read currents read from the pair of reference cells, for each read operation of the plurality of memory cells;
A method for controlling a non-volatile memory, comprising:
(Supplementary Note 2) Each of the read currents read from the pair of reference cells is a first reference current read from the reference cell of data “0” and a second reference current read from the reference cell of data “1”. ,
The nonvolatile memory according to claim 1, wherein the read reference current is generated as a sum current of the first reference current and a current obtained by multiplying the second reference current by a constant j (provided that 0 <j <1). Control method for non-volatile memory.
(Supplementary Note 3) The constant j is determined based on a plurality of selection signals such that the read reference current is substantially an intermediate value between the first reference current and the second reference current. The control method of the nonvolatile memory described in the above.
(Supplementary Note 4) The control of the nonvolatile memory according to any one of Supplementary Notes 1 to 3, wherein a read current read from the memory cell is compared with the read reference current to determine data of the memory cell. Method.
(Supplementary Note 5) Prior to the writing operation of the pair of reference cells, data currently written to the pair of reference cells should be read, and the data should be written to the pair of reference cells based on the result of determining the polarity of each data. 5. The method for controlling a nonvolatile memory according to any one of supplementary notes 1 to 4, wherein data is generated.
(Supplementary note 6) The nonvolatile memory according to any one of Supplementary notes 1 to 5, wherein the write operation of the pair of reference cells is performed simultaneously with the write operation of the plurality of memory cells connected to the same word line. Memory control method.
(Supplementary Note 7) Prior to generation of the read reference current, a word line connected to the pair of reference cells is connected to the pair of reference cells such that a ratio of each read current read from the pair of reference cells becomes a predetermined target value. 7. The method for controlling a nonvolatile memory according to any one of supplementary notes 1 to 6, wherein a voltage to be applied or a voltage to be applied to a source line connected to the pair of reference cells is adjusted.
(Supplementary note 8) The nonvolatile memory according to supplementary note 7, wherein the voltage applied to the source line or the voltage applied to the word line is adjusted based on a current difference between read currents read from the pair of reference cells. Control method for non-volatile memory.
(Supplementary note 9) The non-volatile memory control method according to supplementary note 7 or 8, wherein a voltage applied to the source line is increased when a threshold value of the pair of reference cells is low.
(Supplementary note 10) The method of controlling a nonvolatile memory according to supplementary note 7 or 8, wherein a voltage applied to the source line is decreased when a threshold value of the pair of reference cells is high.
(Supplementary note 11) The supplementary note 9 or 10, wherein a voltage applied to the source line is maintained when a ratio of each read current read from the pair of reference cells reaches a predetermined target value. Non-volatile memory control method.
(Supplementary Note 12) The method according to Supplementary Note 7 or 8, wherein the voltage applied to the word line is decreased when the threshold value of the pair of reference cells is low.
(Supplementary Note 13) The method according to Supplementary Note 7 or 8, wherein the voltage applied to the word line is increased when a threshold value of the pair of reference cells is high.
(Supplementary note 14) The supplementary note 12 or 13, wherein the voltage applied to the word line is maintained when the ratio of each read current read from the pair of reference cells reaches a predetermined target value. Non-volatile memory control method.
(Supplementary Note 15) A plurality of memory cells and a pair of reference cells are connected to the same word line, and source lines are separately connected to each of the memory cells and each of the reference cells along the word line direction. In a nonvolatile memory,
A reference cell read circuit that reads data of the pair of reference cells, determines a polarity of each data, and outputs a polarity signal, for each erase operation or write operation of the plurality of memory cells;
A reference cell write data generator for generating complementary data to be written to the pair of reference cells based on the polarity signal so as to have opposite polarities to data currently written to the pair of reference cells. Circuit and
A source voltage supply circuit provided corresponding to each of the source lines connected to the pair of reference cells, and supplying source voltages respectively corresponding to data output from the reference cell write data generation circuit;
A nonvolatile memory, comprising:
(Supplementary Note 16) Each read current read from the pair of reference cells is a first reference current read from the reference cell of data “0” and a second reference current read from the reference cell of data “1”. ,
A read including a first current-voltage converter that generates a first reference signal according to the first reference current, and a second current-voltage converter that generates a second reference signal according to the second reference current A reference current generating circuit;
A read reference current is generated based on the first and second reference signals so as to have a substantially intermediate value between the first and second reference currents, and the read reference current is compared with a read current read from the memory cell. A sense amplifier for determining the data of the memory cell
16. The nonvolatile memory according to claim 15, further comprising:
(Supplementary Note 17) A Y decoder for a reference cell that generates a decode signal corresponding to data written to the pair of reference cells based on the polarity signal,
A reference cell for outputting a read signal from a reference cell from which the first reference current is read and a read signal from a reference cell from which the second reference current is read to the read reference current generating circuit based on the decode signal. Y select gate and
17. The non-volatile memory according to claim 16, further comprising:
(Supplementary Note 18) The read reference current generation circuit includes:
A first voltage-current converter that generates a first control current obtained by multiplying the first reference current by a predetermined multiple based on the first reference signal; and a second multiple of the second reference current based on the second reference signal. A second voltage-current converter for generating a second control current, wherein the first control current and the second control current are controlled such that a ratio between the first reference current and the second reference current becomes a predetermined target value. 18. The non-volatile memory according to claim 16, further comprising: a read voltage generator for supplying a read voltage generated based on a current difference from the second control current to the word line.
(Supplementary note 19) The non-volatile memory according to supplementary note 18, wherein the read voltage generated by the read voltage generation unit is fed back to a word line applied voltage selection circuit that selects an applied voltage to be supplied to the word line. .
(Supplementary Note 20) The read reference current generation circuit includes:
A voltage-current converter configured to generate a reference control current based on the first reference signal, wherein the first reference current is controlled such that a ratio between the first reference current and the second reference current becomes a predetermined target value. 20. The nonvolatile memory according to claim 16, further comprising: a source voltage generation unit configured to supply a source supply power generated based on a current difference between the source line and the reference control current to the source line. Sex memory.
(Supplementary note 21) The nonvolatile memory according to supplementary note 20, wherein the source supply power generated by the source voltage generation unit is output to the source voltage supply circuit.
(Supplementary Note 22) The plurality of memory cells and the pair of reference cells are cells having a single-layer polysilicon structure,
22. The semiconductor device according to claim 15, further comprising a capacitor connected to the word line, a memory transistor connected to the source line, and a select transistor connected to the selected word line. Non-volatile memory.
[0205]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to provide a nonvolatile memory control method and a nonvolatile memory that can accurately perform a read operation without requiring a verify operation.
[Brief description of the drawings]
FIGS. 1A and 1B are explanatory diagrams showing a configuration of a nonvolatile memory cell according to a first embodiment. FIG. 1A is a circuit diagram, and FIGS. 1B and 1C are cross-sectional structural diagrams.
FIG. 2 is a principle explanatory diagram showing a writing method of a memory cell.
FIG. 3 is a block diagram illustrating a schematic configuration of a nonvolatile memory.
FIG. 4 is a block diagram showing a detailed configuration of a nonvolatile memory.
FIG. 5 is a circuit diagram of a memory cell.
FIG. 6 is a circuit diagram showing a memory cell array.
FIG. 7 is a circuit diagram showing a source voltage supply circuit.
FIG. 8 is a circuit diagram showing a reference cell read circuit.
FIG. 9 is an operation waveform diagram of the reference cell read circuit.
FIG. 10 is a circuit diagram showing a reference cell write data generation circuit.
FIG. 11 is a circuit diagram showing a reference cell Y decoder.
FIG. 12 is a circuit diagram showing a reference cell Y selection gate.
FIG. 13 is a circuit diagram showing a read reference current generation circuit.
FIG. 14 is a circuit diagram showing a Y selection gate.
FIG. 15 is a circuit diagram showing a sense amplifier.
FIG. 16 is a circuit diagram showing a word line applied voltage selection circuit.
FIG. 17 is an operation waveform diagram of the word line applied voltage selection circuit.
FIG. 18 is a circuit diagram showing a word line driver.
FIG. 19 is an operation waveform diagram of the word line driver.
FIGS. 20A and 20B are waveform diagrams showing a write operation, in which FIG. 20A shows writing of data “0” → “0”, FIG. 20B shows writing of data “0” → “1”, and FIG. “→” is written, and (d) indicates writing of data “1” → “1”.
FIG. 21 is an explanatory diagram illustrating a read reference current.
FIG. 22 is a circuit diagram illustrating a read reference current generation circuit according to a second embodiment.
FIG. 23 is an explanatory diagram showing a case where threshold values are distributed high.
FIG. 24 is an operation waveform diagram of the read reference current generation circuit of the second embodiment.
FIG. 25 is a circuit diagram illustrating a read reference current generation circuit according to a third embodiment.
FIG. 26 is an explanatory diagram showing a case where threshold values are distributed low.
FIG. 27 is an operation waveform diagram of the read reference current generation circuit of the third embodiment.
[Explanation of symbols]
Control word line as CWL word line
SL source line
REF-REV polarity signal
Irefj Read reference current
Iref0 1st reference current
Iref1 Second reference current
SAref0 1st reference signal
SAref 2nd reference signal
I0p 1st control current
I1p Second control current
I1p1 Reference control current
ARVSS source voltage
ARGND Source supply power
VCWL-RD read voltage
n ratio
10 memory cells
10a, 10b Reference cells
30 Flash memory as non-volatile memory
44, 45a, 45b source voltage supply circuit
46 Reference cell readout circuit
47 Reference Cell Write Data Generation Circuit
51, 81, 101 read reference current generation circuit
51c, 81a Read voltage generator
52 sense amplifier
61 first current-voltage converter
62 second current-voltage converter
91 First voltage-current converter
92 Second voltage-current converter
101a Source voltage generator
111 Voltage-current converter

Claims (10)

A method of controlling a nonvolatile memory in which a plurality of memory cells and a pair of reference cells are connected to the same word line,
For each erase operation or write operation of the plurality of memory cells, data complementary to each other is written to the pair of reference cells so that the data has the opposite polarity to the data currently written to the pair of reference cells. One step,
A second step of generating a read reference current so as to have a substantially intermediate value between read currents read from the pair of reference cells for each read operation of the plurality of memory cells. Memory control method. Each of the read currents read from the pair of reference cells is a first reference current read from a data “0” reference cell and a second reference current read from a data “1” reference cell.
2. The read reference current according to claim 1, wherein the read reference current is generated as a sum current of the first reference current and a current obtained by multiplying the second reference current by a constant j (where 0 <j <1). A method for controlling a nonvolatile memory. Prior to the write operation of the pair of reference cells, data currently written to the pair of reference cells is read, and data to be written to the pair of reference cells is generated based on a result of determining the polarity of each data. 3. The method for controlling a nonvolatile memory according to claim 1, wherein: Prior to the generation of the read reference current, a voltage applied to a word line connected to the pair of reference cells or a voltage applied to a word line connected to the pair of reference cells so that a ratio of each read current read from the pair of reference cells becomes a predetermined target value. 4. The method according to claim 1, wherein a voltage applied to a source line connected to the pair of reference cells is adjusted. 5. 5. The method according to claim 4, wherein when a threshold value of the pair of reference cells is low, a voltage applied to the source line is increased. 5. The method according to claim 4, wherein when a threshold value of the pair of reference cells is high, a voltage applied to the word line is increased. In a nonvolatile memory, a plurality of memory cells and a pair of reference cells are connected to the same word line, and a source line is separately connected to each of the memory cells and each of the reference cells along the word line direction. ,
A reference cell read circuit that reads data of the pair of reference cells, determines a polarity of each data, and outputs a polarity signal, for each erase operation or write operation of the plurality of memory cells;
A reference cell write data generator for generating complementary data to be written to the pair of reference cells based on the polarity signal so as to have opposite polarities to data currently written to the pair of reference cells. Circuit and
A source voltage supply circuit that is provided corresponding to each of the source lines connected to the pair of reference cells and supplies source voltages respectively corresponding to data output from the reference cell write data generation circuit. Characteristic nonvolatile memory. Each of the read currents read from the pair of reference cells is a first reference current read from a data “0” reference cell and a second reference current read from a data “1” reference cell.
A read including a first current-voltage converter that generates a first reference signal according to the first reference current, and a second current-voltage converter that generates a second reference signal according to the second reference current A reference current generating circuit;
A read reference current is generated based on the first and second reference signals so as to have a substantially intermediate value between the first and second reference currents, and the read reference current is compared with a read current read from the memory cell. 8. The nonvolatile memory according to claim 7, further comprising: a sense amplifier for determining data of said memory cell. The read reference current generation circuit includes:
A first voltage-current converter that generates a first control current obtained by multiplying the first reference current by a predetermined multiple based on the first reference signal; and a second multiple of the second reference current based on the second reference signal. A second voltage-current converter for generating a second control current, wherein the first control current and the second control current are so controlled that a ratio between the first reference current and the second reference current becomes a predetermined target value. 9. The non-volatile memory according to claim 8, further comprising: a read voltage generator for supplying a read voltage generated based on a current difference from the second control current to the word line. The read reference current generation circuit includes:
A voltage-current converter for generating a reference control current based on the first reference signal, wherein the first reference current is controlled such that a ratio of the first reference current to the second reference current becomes a predetermined target value. 10. The non-volatile memory according to claim 8, further comprising: a source voltage generator for supplying a source supply power generated based on a current difference between the reference voltage and the reference control current to the source line.

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