JPH0921879A - Radiation plane detection device and radiation image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a device small and lighten a burden of an operator by inputting a plurality of signal charges as a pair in parallel, integrating output values outputted from a means which converts the charges into series signals in time sequence, and forming a pixel signal. SOLUTION: When a pixel signal is read out from all read lines R1-R2000 through each of multiplexers 15a1-15a16, all image signals corresponding to one image screen are memorized in a frame memory 18. All image signals corresponding to the lines R1-R2000 are amplified through integration circuits 16a1-16a16. The image signal is displayed through an image processing circuit and a monitoring circuit. Although the number of the integration circuits is 16, which is a sharp decrees compared with the conventional device, pixel signals amplified every line with these integration circuits are obtained, and fixed pattern noise appearing in the image signal is reduced. Adjustment of different characteristics between integration circuits is made very easy, and installation of a compensation circuit is made unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radiation flat panel detector and a radiation image pickup apparatus which are arranged in a matrix and have a radiation detecting section for detecting radiation as a signal charge.

[0002]

2. Description of the Related Art As a means for picking up an X-ray image transmitted through a human body in medical diagnosis, one using an X-ray film or an image intensifier (II) / TV camera system is known. In particular, a transmission X-ray image can be obtained by I. I. image signal is generated by converting the optical image into an optical image through a camera and capturing the optical image with a TV camera such as a CCD. I. An X-ray fluoroscopic (imaging) system (digital fluorography) using a / TV camera system is still actively used.

On the other hand, in recent years, as a means for converting a radiation image such as an X-ray image into an image signal, a radiation plane detector (2
Dimensional detectors) have been proposed. This radiation plane detector is composed of a thin fluorescent screen for converting an X-ray image into an optical image and an optical image capturing section for converting an optical image emitted from the fluorescent screen into an image signal. I. / It can be made thinner than the X-ray imaging means using a TV camera (hereinafter, the radiation plane detector is simply referred to as a plane detector).

As such a flat panel detector, for example, U
The one disclosed in S Patent No. 5,184,018 is known. A schematic configuration of this flat panel detector is shown in FIG. The flat panel detector 51 has a sensor group arranged in a matrix of 2000 × 2000, for example.

According to this plane detector 51, the X-ray device 5
Radiation from 2 etc. (transmitted X-ray Xr transmitted through the object Ob)
Is incident on the photodiode 53, the incident X
The charges accumulated in the capacitor 54 based on the lines are read out for each row by the operation of the TFT 55 under the control of the digital decoder 56, and read lines R1, R2, ..., R128.
, ... are read.

For example, the sensor group of the first row (sensor S1,1
, Sensors S1,2, ..., Sensors S1,128, ...) are stored in the respective TFs of the sensor group.
By the operation of T5, the read lines R1, R2,
, R128, ..., and amplifiers 57a, 58a, ..., 59a ,.
, 59, ... After being integrated through integration circuits 57, 58 ,.
The charges input at the same time by the multiplexer 60 are sent to a processing circuit (not shown) as a DC signal (image signal). Thereafter, the charges are sequentially read out for each row such as the second row, the third row, ... And the charges accumulated in all the rows are read out as an image signal.

[0007]

However, in the above-mentioned configuration, since the integrating circuit including the amplifier is provided for each read line, the circuit configuration becomes large in scale. For this reason,
This leads to an increase in the size of the entire device equipped with this flat detector and a reduction in the effective space of the entire device.

Further, since an integrator circuit including an amplifier is provided for each read line, an image signal obtained by a difference (deviation) in various characteristics such as the gain factor and C (capacitance) of the amplifier in each integrator circuit. In this case, fixed pattern noise (also called field pattern noise) appeared due to the difference in the characteristics. Therefore, the image quality of the display image is deteriorated and the visibility is deteriorated accordingly. In order to reduce the fixed pattern noise, for example, (1) adjustment of each integrating circuit by an operator and (2) a compensating circuit for compensating for differences in characteristics of individual integrating circuits (for example, a plurality of compensating circuits corresponding to the number of read lines) Compensation amplifier, memory, etc.) of
With the method (1), it is difficult to maintain a constant image quality due to misalignment due to the passage of time. Further, the method (2) has a problem that the circuit configuration becomes complicated.

On the other hand, in an image capturing apparatus using a TV camera, an X-ray image capturing apparatus, etc., it is required to change the total number of pixels and the frame rate according to the usage condition of the object to be imaged.
However, the above-described pixel (charge) reading method using the flat panel detector does not support changes in the total number of pixels and the frame rate. For this reason, the range of application for photography is limited, which is unsatisfactory for users.

The present invention has been made in view of these circumstances, and it is a first object of the present invention to reduce fixed pattern noise appearing in an image signal while reducing the number of compensation circuits and further reducing the adjustment of the integrating circuit to a necessary minimum. To aim. Also,
A second object is to increase the range of imaging applications and meet user needs by making it possible to change the total number of pixels and the frame rate using a flat panel detector.

[0011]

In order to achieve the above object, in the radiation flat panel detector according to the first aspect of the present invention, the radiation detection is such that sensors for accumulating signal charges corresponding to the intensity of the incident radiation are arranged in a matrix. In the radiation flat panel detector, the plurality of readout lines for reading the signal charges provided for each column of the plurality of sensors of the radiation detection unit, and the signals detected by each sensor of the radiation detection unit Read-out means for reading out electric charges in parallel through the plurality of read-out lines and a plurality of signal charges read out from a plurality of set lines among the plurality of read-out lines are input in parallel as one set and the parallel input signal thereof Of at least one conversion means for converting the signal into a time-series serial signal, and an output path of each conversion means inserted into and output from each of the conversion means. By integrating the serial signal and a integration means for forming a pixel signal.

Particularly, in the radiation plane detector according to the second aspect of the present invention, each of the conversion means is provided with a multiple input and single output type multiplexer corresponding to the multiple lines.

Further, in particular, in the radiation flat panel detector according to the third aspect, the read-out means includes a switching element for each of the sensors, and the signal charge is read out from each of the sensors by driving the switching element. I am trying.

Further, in the radiation plane detector according to claim 4, each of the sensors has a fluorescent screen which receives the radiation and converts it into an optical signal, a photodiode which detects the optical signal as a signal charge, and A capacitor for accumulating signal charges is provided, and the switching element and the sensor are formed by thin film technology.

Furthermore, in the radiation plane detector according to a fifth aspect of the present invention, the plurality of lines correspond to all the plurality of read lines, and the number of the multiplexer is one.

Particularly, in the radiation plane detector according to the sixth aspect, each of the multiplexers simultaneously outputs the signal charge of the first input line in response to a predetermined output timing, and hereinafter, in accordance with the output timing. Therefore, the second and subsequent input lines are sequentially output.

Further, in particular, in the radiation flat panel detector according to the seventh aspect, a control signal is sent to each of the multiplexers so as to switch a plurality of signal charges input to each of the multiplexers to a plurality of adjacent signal charges. A switching control means is provided.

Further, in the radiation plane detector according to the eighth aspect, the read-out means reads the signal charges detected by the respective sensors by driving the respective switching elements in a plurality of rows and the switching control. The means sends to each of the multiplexers a control signal that causes the plurality of signal charges input to each of the multiplexers to be switched by outputting a plurality of adjacent signal charges corresponding to the number of rows.

Furthermore, in the radiation plane detector according to a ninth aspect of the invention, each of the integrating means inserted in the output path of each of the multiplexers is controlled according to the timing when a predetermined number of signal charges are output from each of the multiplexers. Reset control means for sending a reset signal for resetting to each integration means.

In addition, in order to achieve the above-mentioned object
In the radiation flat panel detector described in (1), a radiation detecting section in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix, and a plurality of sensors of the radiation detecting section are provided for each column. And a plurality of read lines for reading the signal charges, a switching element provided for each sensor of the radiation detection unit, and a drive pulse is supplied to each of the switching elements to drive the switching element. Read-out control means for reading out the signal charge detected by each sensor through the read-out line, and signal conversion means for converting a pixel signal obtained based on the signal charge read by the read-out means into a digital image signal A radiation plane detector comprising: a plurality of read lines, each of which is provided for each of the read lines. And a frame rate changing means for changing the frame rate and integrating the signal charges read in parallel to form the pixel signal, and the read control means changes the frame rate. A means for controlling the peak value of the drive pulse is provided accordingly.

Further, in order to achieve the above object, in the radiation flat panel detector according to the eleventh aspect of the present invention, there is provided a radiation detecting section in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix. A plurality of readout lines for reading the signal charges provided for each column of the plurality of sensors of the radiation detection unit, a switching element provided for each sensor of the radiation detection unit, and each of the switching elements. Read control means for reading the signal charges detected by the respective sensors in parallel via the plurality of read lines by supplying a drive pulse to drive the switching element, and a signal read by the read means. The pixel signal obtained based on the electric charge is sampled at a predetermined frame rate and converted into a digital image signal. And a signal conversion means for converting the parallel input signal into a plurality of signal charges read out from a plurality of set read lines among the plurality of read lines in parallel. At least one conversion means for converting into a time-series serial signal, and an integration means for forming the pixel signal by integrating a serial signal inserted in each output path of the conversion means and output from the conversion means. And a frame rate changing unit that changes the frame rate, and the read control unit includes a unit that controls the peak value of the drive pulse according to the change of the frame rate.

Particularly, in the radiation plane detector according to the twelfth aspect, the switching element is a thin film transistor.

Further, in the radiation plane detector according to the thirteenth aspect, the crest value control means, when the frame rate is changed to a rate higher than the current frame rate by the frame rate changing means, The peak value of the drive pulse is set higher than the current peak value.

Furthermore, in order to achieve the above object, the radiation plane detector according to claim 14 is provided with a radiation detecting section in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix. In the radiation flat panel detector, a plurality of readout lines for reading the signal charges provided for each column of the plurality of sensors of the radiation detection unit, and a switching element provided for each sensor of the radiation detection unit. A read control means for reading the signal charge detected by each sensor through the read line by supplying a drive pulse to each of the switching elements to drive the switching element; and a read control unit provided for each read line. , Integrating means for integrating the signal charges read through the read line to form a pixel signal. In addition, the read control means includes means for controlling the peak value of the drive pulse according to the distance from each row of the plurality of sensors of the radiation detecting section to the integrating means, and the integration is performed by controlling the peak value. The time constant of the signal charge of each radiation detector sent to the means is set to a substantially constant value.

Further, in order to achieve the above object, the present invention is defined in claim 15.
In the radiation plane detector described in 1 above, in a radiation plane detector including a radiation detection unit in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix, a plurality of sensors of the radiation detection unit are provided. A plurality of readout lines provided for each column for reading out the signal charges, a switching element provided for each sensor of the radiation detection unit, and a switching element by supplying a drive pulse to each switching element. Are driven to read the signal charges detected by the respective sensors in parallel via the plurality of read lines, and a plurality of read lines read from a plurality of set read lines of the plurality of read lines. At least inputting signal charges in parallel as one set and converting the parallel input signal into a time-series serial signal. The read control means is provided with one conversion means and an integration means which is inserted into each output path of the conversion means and which integrates the serial signals output from the conversion means to form a pixel signal. A means for controlling the crest value of the drive pulse according to the distance from each row of the plurality of sensors of the radiation detecting section to the integrating means is provided, and the radiation detecting section of each radiation detecting section sent to the integrating means by controlling the crest value. The time constant of the signal charge is set to a substantially constant value.

Particularly, in the radiation plane detector according to claim 16, the switching element is a thin film transistor.

Further, in order to achieve the above-mentioned object, claim 17
The radiation imaging apparatus described in (1) includes a radiation detection unit in which sensors for accumulating signal charges corresponding to the intensity of radiation such as X-rays transmitted through an incident subject are arranged in a matrix, and based on the signal charges. In the radiation imaging apparatus configured to image the inside of the subject based on the obtained pixel signals, a plurality of read lines for reading the signal charges provided for each column of the plurality of sensors of the radiation detection unit, Reading means for reading in parallel the signal charges detected by the respective sensors of the radiation detecting section via the plurality of read lines, and a plurality of signal charges read from a plurality of set lines of the plurality of read lines 1
At least one conversion means for inputting in parallel as a set and converting the parallel input signal into a time-series serial signal, and a serial signal inserted in each output path of the conversion means and output from the conversion means Is integrated to form the pixel signal.

[0028]

In the radiation plane detector according to any one of claims 1 to 9 and the radiation image pickup device according to claim 17, radiation such as X-rays is incident on the sensors arranged in a matrix of the radiation detecting portion, and the incident radiation. Corresponding to the radiation intensity, it is detected as a signal charge by the sensor. Further, a switching element is provided for each sensor of the radiation detection unit, and a drive pulse is supplied to the switching element from the read control means to drive the switching element, whereby the signal charge detected by each sensor is Are read in parallel by the reading means via a plurality of reading lines provided corresponding to each column of the plurality of sensors of the radiation detecting unit. The signal charges are read in parallel by the reading means via a plurality of reading lines provided corresponding to each column of the plurality of sensors of the radiation detecting section.

Among a plurality of signal charges read in parallel via a plurality of read lines, a plurality of signal charges read out from a plurality of set lines are set as one set in parallel and at least one converter such as a multiplexer. , And the parallel input signal is converted into a time series serial signal. For example, when the plurality of lines correspond to all the plurality of read lines, the number of multiplexers is one, and the signal charges sent through the plurality of read lines are converted into a single serial signal by the multiplexer. If there are a plurality of sets of a plurality of lines, there are as many multiplexers as the number of the plurality of sets, and the signal charges sent via the plurality of lines of each set are converted into serial signals by the respective multiplexers.

The serial signal output from each of the at least one multiplexer is integrated by the integrating means inserted in the output path of each multiplexer to form a pixel signal. That is, the plurality of signal charges read in parallel via the plurality of read lines are sent to the integrator as a serial signal for each of the set plurality of lines by at least one multiplexer so that they are integrated. Therefore, the number of integrating means is significantly reduced as compared with the case where integrating means is provided for each read line.

In particular, according to the radiation plane detector of the seventh aspect, the switching control means sends a control signal to each multiplexer, and a plurality of multiplexers are input by the operation of each multiplexer according to this control signal. The signal charges of (1) are switched to adjacent ones and output to the integrating means. That is, the signal charges output to the integrating means are added together by a plurality of adjacent multiplexors and output. Further, according to the radiation plane detector of the eighth aspect, the read-out means drives each switching element to read out the signal charges detected by each sensor in a plurality of rows. At this time, the switching control means
A control signal is sent to each multiplexer, and by the operation of each multiplexer according to this control signal, a plurality of input signal charges are switched to each adjacent plurality corresponding to the number of rows and output to the integrating means. To be done. That is,
Since a plurality of adjacent signal charges corresponding to the number of rows read by the reading means are read out, the integration means is added with the signal charges of “the number of read rows × the number of read by the multiplexer” and output. ing.

Further, in the radiation plane detector according to the ninth aspect of the invention, each of the integrating means inserted in the output path of each of the multiplexers receives a predetermined number of signal charges from each of the multiplexers in response to a reset signal from the reset control means. Is reset in accordance with the timing at which is output, the pixel signals integrated and formed by the integrating means are added with the signal charges of the number output from each multiplexer.

On the other hand, in the radiation flat panel detector according to the tenth to fourteenth aspects, radiation such as X-rays is incident on the sensors arranged in a matrix of the radiation detecting section, and the sensor is corresponding to the incident radiation intensity. Are detected as signal charges by. Further, a switching element, for example, a thin film transistor is provided for each sensor of the radiation detection unit, and a driving pulse is supplied to the thin film transistor from the read control unit to drive the thin film transistor, thereby detecting a signal detected by each sensor. The electric charge is read by the read control means via a read line provided corresponding to each column of the plurality of sensors of the radiation detection unit.

The plurality of read signal charges are integrated by an integrating means provided for each of the plurality of read lines, or converted into a serial signal by at least one converting means and then integrated by the integrating means. Integrated. Then, the pixel signal obtained by integrating by the integrating means is sampled by the converting means at a predetermined frame rate, for example, and converted into a digital image signal.

At this time, when the frame rate changing means changes the frame rate to, for example, a fast rate, the crest value control means changes the crest value of the drive pulse for driving the thin film transistor in accordance with the change in the frame rate. It is set to be higher than the peak value corresponding to the frame rate.

Due to the change of the peak value, the resistance RDS between the drain and the source of the thin film transistor is reduced, so that the time constant of the integrating means becomes small and the movement of the signal charge to the integrating means becomes faster.

Furthermore, according to the radiation flat panel detector of the fourteenth to sixteenth aspects, radiation such as X-rays is made incident on the sensors arranged in a matrix of the radiation detection section, and the radiation intensity is corresponding to the incident radiation intensity. It is detected as a signal charge by the sensor. In addition, a switching element, for example, a thin film transistor is provided for each sensor of the radiation detection unit, and a driving pulse is supplied to the thin film transistor from the read control unit, but the thin film transistor is driven, and the thin film transistor is detected by each sensor. The signal charge is read by the read control means via a read line provided corresponding to each column of the plurality of sensors of the radiation detection unit.

The plurality of signal charges read through the read lines are integrated by the integrating means provided for each of the plurality of read lines, or converted into a serial signal by at least one converting means. Then, integration is performed by the integrating means to form a pixel signal.

At this time, by the read control means,
Since the crest value of the drive pulse for driving the thin film transistor is controlled according to the distance from each row of the plurality of sensors of the radiation detection unit to the integration unit, the signal charge of each radiation detection unit sent to the integration unit is controlled. The time constant of is set to a substantially constant value. That is, since the time constant is maintained substantially constant regardless of the difference in the distance from each row of the radiation detecting unit to the integrating means, the difference in the moving speed of the signal charges to the integrating means due to the difference in the time constant is eliminated. It

[0040]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In this embodiment, an X-ray detector used in an X-ray imaging apparatus that images the inside of the subject based on the X-rays that have passed through the subject will be described in particular.

(First Embodiment) FIG. 1 shows a part of an X-ray diagnostic apparatus according to the present invention.

The X-ray source 2 irradiates the object Ob with X-rays. The X-ray detector 1 captures an X-ray Xr (X-ray image) that has passed through the subject, converts it into an image signal, and outputs the image signal. A fluorescent screen that converts the incident X-ray into light (see FIG. (Not shown), a photosensor group (sensor group) that converts light output from the phosphor screen into electric charges and stores the electric charges, a digital decoder 10 and a readout circuit 12 for reading the electric charges accumulated in the photosensor group. ing.

The sensor group is arranged in a matrix of rows and columns. The sensor matrix in this embodiment is composed of, for example, 2000 (rows) × 2000 (columns) (only a part of which is shown in FIG. 1).

In the first row of the matrix in FIG. 1, the sensors S1,1 and S1,2 are shown. In this first row, following the sensors S1,2, another sensor group (not shown) (in FIG. 1, the 128th sensor S in the first row is shown).
1,128 are shown), and there are approximately 2000 sensors in the entire first row.

In the second row of the matrix as well as the first row, the sensors S2,1, S2,2 and S2,128 are shown. And about 2000 sensors are provided in the entire second row.

Subsequent to these two rows of sensor groups, other rows of sensor groups (not shown) are provided. In FIG. 1, the sensor group in the last row (2000th row) is shown. The first sensor in this line 2000 is S20
This is shown as 00,1 and the second sensor is shown as S2000,2. Then, as in the first and second rows, as shown in FIG.
Does not show all the sensor elements in the 2000th row, but shows the 128th S2000,128. The first group of sensors in each row collectively constitutes the first column of the matrix, the second group of sensors in each row collectively constitutes the second column of the matrix, and so on.
The 000th sensor group is the 2000th matrix in total.
It constitutes a row of sensors.

Each sensor has a photo sensor element. As shown in FIG. 1, a photodiode (PD) 3 is used for this photo sensor element. Further, each sensor has the storage capacitor 4 for storing the charge and the switching field effect transistor 5 for reading the stored charge. The anode of the PD 3 and one electrode of the capacitor 4 are both connected to a DC voltage source 6 that gives a negative bias. The cathode of the PD 3 and the other electrode of the capacitor 4 are both connected to the source terminal of the switching field effect transistor 5.

As described above, all the sensors forming the matrix (hereinafter, this sensor is also referred to as a pixel) are
Each sensor has a PD 3, a storage capacitor 4, and a switching field effect transistor 5, and these sensors are manufactured by, for example, spraying amorphous silicon on a glass substrate and depositing the silicon (hereinafter, this manufacturing method). That is called thin film technology). The field effect transistor manufactured by the thin film technology is hereinafter referred to as a thin film transistor (TFT) 5.

A switching line is provided in each row of the sensor matrix. As shown in FIG. 1, the switching line L1 is provided for the first row sensor group, the switching line L2 is provided for the second row sensor group, and the switching lines L2000 and 2000 are provided. Provided for the row sensor group. These switching lines are connected to the gate terminals of the TFTs 5 of the corresponding sensor group. The switching line is adapted to activate the TFT 5 of the associated row. For example, switching line L1
Activates all the TFTs 5 in the first row of the matrix.

The switching lines L1, L2, L2000 and other switching lines (not shown) are controlled by the digital decoder 10 and the microprocessor 11. The microprocessor 11 is connected to the digital decoder 10, a reading circuit 12 described below, and an input unit 13. The input unit 13 can input information such as the number of read pixels and the frame rate to the microprocessor 11.

The microprocessor 11 is adapted to carry out overall control for the read operation of the sensor group, such as reading pixel signals from the sensor group at a predetermined read timing (ON timing of the TFT 5).

The digital decoder 10 and the microprocessor 11 have a function of continuously operating each row of the sensor matrix during the read operation of the charges accumulated in the sensor group. For example, in response to a control signal from the microprocessor 11, the digital decoder 10 sends a drive pulse to a line based on the control signal (here, the first switching line L1). This drive pulse activates the first switching line L1 for the sensor group of the first row of the matrix, so that the TFT5 of that first row becomes conductive, and subsequently the sensor line of the second row of sensor groups is activated. Switching line L to operate the TFT5
2 is activated. Thereafter, the same operation is performed, and finally the TFT 5 of the sensor group in the 2000th row is operated.

On the other hand, a read line is provided in each column of the matrix partially shown in FIG. For example, the sensor group in the first row (S1,1, S2,1, in the figure,
And S2000, 1) are equipped with a read line R1.
Similarly, the second row of sensor groups (S1,2, S2,2, and S2000,2 in the figure) comprises a read line R2, and the 128th row of sensor groups (S1,128, S2, in the figure). 128, and S
2000, 128) has a read line R128. Further, the sensor groups in the other columns (not shown) are also provided with read lines. All read lines R1 ~
The R2000s are both connected to the drain terminal of the TFT 5 in the corresponding row. For example, the read line R1 in the first column is connected to the drain terminals of the TFTs 5 of all the sensor groups in the first column. The output side of these read lines R1 to R2000 is connected to the read circuit 12.

A schematic structure of the read circuit 12 is shown in FIG.

The read circuit 12 includes a plurality of (16 in this embodiment) analog multiplexers 15a1 to 15a1.
It is equipped with 5a16. The integrating circuits 16a1 to 16a16 are connected to the output side of each multiplexer. The outputs of the integrating circuits 16a1 to 16a16 are A / D converters 17
a1 to 17a16, each A / D converter 17a1 to
The output of 17a16 is connected to the frame memory 18. Further, the read circuit 12 includes the multiplexer 15a.
The microprocessor 19 for controlling the operations of 1 to 15a16 and the integrating circuits 16a1 to 16a16 is provided. The microprocessor 19 is mutually connected to the microprocessor 11 and can transmit / receive control commands to / from each other. An input unit 13 is connected to the microprocessor 19, and information such as the number of read pixels and the frame rate (sampling rate) can be input to the microprocessor 19 via the input unit 13. There is.

16 multiplexers 15a1 to 15a
16 are provided corresponding to the read lines divided into 16 groups from the first read line R1. That is, of the multiplexers 15a1 to 15a16, the multiplexer 15a1 has read lines R1 to R128.
, The read lines R129 to R256 are connected to the multiplexer 15a2, and the read lines R1921 to R2000 are similarly connected to the multiplexer 15a16. These multiplexers 15a1 to 1
The microprocessor 19 is connected to each control input terminal of 5a16.
The control output terminal is connected, and the control signal such as the mode signal, the clock signal C, and the reset signal Re1 is input from the microprocessor 19 through the control input terminal.

The multiplexer 15a1 also has switching elements sw1 to sw128 such as transistors connected to the read lines R1 to R128, and a selection control signal (clock signal C based on a predetermined sequence sent from the microprocessor 19). (Or an address signal) and a mode signal (in this embodiment, there are two kinds of signals of LOW level and HIGH level)), ON (conduction state) / OFF (cutoff state) of each of the switching elements sw1 to sw128. ), The signal output from the multiplexer 15a1 is switched to a part of the read lines R1 to R128. Particularly, in this embodiment, the multiplexer 15a1
When a LOW-level mode signal is input, the signal of the read line R1 is output as an output signal at the falling edge of a certain clock pulse of the clock signal C, and so on. The output is sequentially read out according to the lines R2 to R
It is designed to switch to 128. Also, HIG
When the H-level mode signal is input, the signals on the read lines R1 and R2 (the signals on the two lines) are output as output signals at the falling timing of the clock pulse, for example. The output is read out according to the falling lines R3, R4,
.., R127 and R128 are sequentially switched every two lines. The other multiplexers 15a2 to 15a16 have the same configuration and operate in the same manner. For example, the multiplexer 15a2 has switching elements sw129 to sw256, and the multiplexer 15a16 has the switching element sw.
It has w1921 to sw2000. Then, when the LOW level mode signal is input, the multiplexer 15a2 reads out the read line R in synchronization with, for example, the falling timing of a certain clock pulse of the clock signal C.
The signal 129 is output as an output signal, and thereafter, the output is sequentially switched to the read lines R130 to R256 according to the falling edge of the clock pulse.
When a HIGH-level mode signal is input, the signals on the read lines R129 and R130 (the signals on the two lines) are output as output signals at the falling edge of the clock pulse, for example. The output of the read lines R129, R130, R131, R132, ..., R255, R in response to the falling edge of
It is designed such that 256 lines and 2 lines are sequentially switched.

The multiplexers 15a1 to 15a16 are also provided.
In terms of power consumption, circuit space, noise ratio, etc., it is considered effective to use an IC, but in order to support many types of thin detectors with different numbers of pixels, each IC must be operated independently. Not only that, it is good to have a function to use several in synchronization.

The integrating circuits 16a1 to 16a16 are provided according to the number of multiplexers 15a1 to 15a16. That is, the integrating circuit 16a1 is the multiplexer 1
An amplifier 20a1 connected to the output line of 5a1, a first capacitor 21a1 connected in parallel to this amplifier 20a1, and a second capacitor 22a1 and a first capacitor 22a1 connected in parallel to this amplifier 20a1.
Switch 23a1 and a second switch 24a1 connected in parallel to the amplifier 20a1.
In addition, the first switch 23a1 and the second switch 24
The control outputs of the microprocessor 19 are connected to a1 respectively, and the microprocessor 19 turns on / off the first switch 23a1 and the second switch 24a1.
Is controlled. Other integration circuit 16a
2 to 16a16 have the same configuration as that of the integrating circuit 16a1,
For example, the integrating circuit 16a2 includes an amplifier 20a2, a first capacitor 21a2, a second capacitor 22a2, a first capacitor
Switch 23a2 and second switch 24a2, and the integration circuit 16a16 includes an amplifier 20a16 and a first switch 24a2.
21a16, a second 22a16, a first switch 23a16, and a second switch 24a16.

In the integrating circuit 16a1, when the first switch 23a1 is ON, the entire integrating circuit 16a1 includes the amplifier 20a1 and the read line selected by the multiplexer 15a1 and the resistance value of the TFT corresponding to the read line. , The first capacitor 21a1 and the second capacitor
And an integrated circuit composed of the combined capacitance of the capacitors 22a1 of
When is OFF, the whole integrating circuit 16a1 is composed of the amplifier 20a1, the read line selected by the multiplexer 15a1 and the resistance value of the TFT corresponding to the read line, and the capacitance of the first capacitor 21a1. It serves as an integrating circuit and integrates and outputs a signal to be sent according to a time constant determined by the resistance value and the capacitance (composite capacitance or capacitance of the first capacitor 21a2). That is, by controlling ON / OFF of the first switch 23a1 by the microprocessor 15a1, the time constant, output signal amplitude, etc. of the integrating circuit 16a1 can be switched. The second switch 24a1 is provided for resetting the integrating circuit.
That is, the second switching element 2 is controlled by the control signal (reset signal Re2) from the microprocessor 19.
When 4a1 is turned on, the electric charge stored in at least one of the first capacitor 21a1 and the second capacitor 22a1 is discharged to return to the initial state. The other integrating circuits 16a2 to 16a16 are also integrated circuit 1
The same operation as 6a1 is performed.

The control outputs from the microprocessor 19 are connected to the A / D converters 17a1 to 17a16,
In response to the control of the microprocessor 19 based on the frame rate sent from the input unit 13, each integrating circuit 16a1
The output signals (image signals) from 16a16 are converted into digital signals. The image signals converted into digital signals are stored in predetermined storage areas of the frame memory 18, respectively. Then, this image signal is subjected to image processing by an image processing circuit (not shown) or the like as necessary, and then displayed by a monitor circuit (not shown).

Next, the overall operation of this embodiment will be described, focusing on the operations of the multiplexer 15a1 and the integrating circuit 16a1.

The object O is emitted by the X-ray fluoroscope 2.
When the transmitted X-ray Xr transmitted through b is incident on the PD3 of the sensor group, the PD3 receives visible light based on the incident X-ray. The electric charge generated by this visible light is sent to the storage capacitor 4 by the negative bias given by the DC voltage source 6 and stored therein. The amount of this accumulated charge (charge amount) depends on the intensity of the radiation incident on the PD 3. Therefore, the charge stored in the storage capacitor 4 after a given time period represents the degree (rate) of the radiation intensity. Under the control of the digital decoder 10 and the microprocessor 11, the charges are independently read sequentially for each row via the TFT 5 of each sensor group.

The charges (pixel signals) read out from the PD 3 in this manner are passed through the read lines R1 to R2000 and the multiplexers 15a1 to 15a of the read circuit 12 are read.
Sent to 16.

Here, the multiplexers 15a1 to 15a
16 and the operation of the integrating circuits 16a1 to 16a16.
This will be described with reference to FIG. Here, the multiplexer 15a1 and the integrating circuit 16a1 shown in FIG.
Will be described. 4 is a diagram showing the ON / OFF states of the switching elements sw1 to sw128, and FIG. 5 is a clock signal C in the signal charge reading process, the first switching element sw1 to the third switching element sw1, and the resetting. The waveform diagram of the signal Re2 and the signal charge (pixel signal) is shown.

Now, for the multiplexer 15a1 shown in FIG. 3, the mode signal "L" (L
OW level signal), the read line R1 is synchronized with the operation of the multiplexer 15a1 in synchronization with, for example, the fall of the clock pulse c1 having the clock signal C, as shown in FIGS. The first switching element sw1 corresponding to
The ON time is one cycle of the clock signal).

When the switching element sw1 is turned on, the first pixel signal is transferred to the integrating circuit 16 via the read line R1 connected to the first switching element sw1.
a1 (switch 23a1 is open). The first pixel signal corresponds to the first capacitor 21a.
It is integrated based on the time constant T determined by the capacitance Ca1 of 1 and the resistance value r corresponding to the read line R1 and saturates after a certain period of time (see FIG. 5). The signal amplitude at this time becomes a signal corresponding to one pixel and is stored in the corresponding storage area of the frame memory 18 via the A / D converter 17a1. Then, after the signal charges reach saturation, a reset signal Re2 (from the microprocessor 19) sent from the microprocessor 19 (after a sufficient time for performing post-processing such as the sampling time of the A / D converter 17a1) after a lapse of some time. The first capacitor 21 according to the timing required before the fall of the clock pulse c2 of the next stage).
The electric charge accumulated in a1 is discharged. As a result, the integrator circuit 16a1 becomes ready to read the next signal charge, and thereafter, by the processing of the multiplexer 15a1, the first signal is synchronized with the falling edge of the clock pulse c2 of the clock signal C.
Of the second switching element sw1 corresponding to the read line R2 while the switching element sw1 of
2 turns ON (see FIGS. 4 and 5). That is, ON of the switching element is switched to the next-stage switching element. Hereinafter, the switching elements sw3 to sw in the next stage are sequentially arranged.
The above process is repeated while ON / OFF of 128 (elements corresponding to the read lines R3 to R128) is sequentially switched in synchronization with the falling edge of the clock pulse of the clock signal C. As a result, the pixel signals sent via the read lines R2 to R128 are sequentially stored in the frame memory 18 via the A / D converter. By sending the reset signal Re1 from the microprocessor 19 to the multiplexer 15a1 at a predetermined timing, the switching element to be turned on can be set to the first switching element sw1 at any time. Normally, as shown in FIG. 4, after the switching element sw128 corresponding to the read line R128 is turned on, the read line R1 is read.
Is set in the first switching element sw1 corresponding to.

The above-described processing is performed by the other multiplexer 1.
Since 5a2 to 15a16 and the integrating circuits 16a2 to 16a16 are simultaneously performed (parallel processing), all the multiplexers 15a are read from all the read lines R1 to R2000.
When the pixel signals are read out through 1 to 15a16, it means that all the pixel signals (image signals) corresponding to one screen are stored in the frame memory 18. Moreover, the read lines R1 ...
The image signals corresponding to R2000 are all integrated circuits 16a1 ...
It is amplified through 16a16. This image signal is provided for display via an image processing circuit and a monitor circuit (not shown).

That is, according to the present embodiment, although the number of the integrating circuits is 16 which is drastically reduced as compared with the conventional configuration, the signal charges (amplified by the integrating circuit for each read line ( (Pixel signal) can be obtained, and fixed pattern noise appearing in the image signal can be reduced. Therefore, the adjustment due to the difference in the characteristics between the integrating circuits becomes very easy, and the compensating circuit need not be installed.

The multiplexers 15a1 to 15a16 are provided.
However, the present invention is not limited to this. For example, after first performing the processing of the multiplexer 15a1 (and the integrating circuit 16a1),
It may be sequentially performed with the multiplexer 15a2 (and the integrating circuit 16a2) and the multiplexer 15a3 (and the integrating circuit 16a3).

By the way, in this embodiment, the microprocessor 19 to the multiplexers 15a1 to 15a16 are used.
Pixel addition (two-pixel addition in this embodiment) can be performed by switching the mode signal sent to the signal from "L" to "H" (HIGH level signal).

Hereinafter, description will be given with reference to the drawings. 6 is a diagram showing the multiplexer 15a1 and the integrating circuit 16a1. Further, FIG. 7 shows the switching element sw1.
9 is a diagram showing ON / OFF states of sw128 and FIG.
4 shows waveform diagrams of the clock signal C, the first switching element sw1 to the fourth switching element sw4, the reset signal Re2, and the pixel signal in the signal charge reading process.

Now, when the mode signal "H" is sent from the microprocessor 19, the multiplexer 15a1 processes the clock pulse c1 of the clock signal C, for example, to the falling edge, as shown in FIGS. Synchronously, the first switching element sw1 corresponding to the read line R1 and the second switching element sw2 corresponding to the read line R2 are simultaneously turned on. The read line R1 connected to the first switching element sw1 in response to turning on of the switching elements sw1 and sw2.
And the first pixel signal and the second pixel signal are sent to the integrating circuit 16a1 via the read line Re2 connected to the second switching element sw2. That is, the signal charges corresponding to the pixels in the two adjacent columns are added and sent to the integrating circuit 16a1.

In the following, similar to the signal reading process when the mode signal "L" is sent, the integrating circuit 16a
1, the frame memory 18 through the A / D converter 17a1
Are stored in the corresponding storage areas. Then, in synchronization with the trailing edge of the clock pulse c2 of the clock signal C that is sent subsequently, the first switching element sw is processed by the multiplexer 15a1 as shown in FIGS.
The first and second switching elements sw2 are turned off at the same time, and the third switching element sw3 (the element corresponding to the read line R3) and the fourth switching element sw4 (the element corresponding to the read line R4) are turned on at the same time. Hereinafter, by repeating the above-described processing while simultaneously switching ON / OFF of two adjacent switching elements, the pixel signals corresponding to two adjacent read lines are stored in the frame memory 18 in a state of being added respectively. become.

The above-described processing is performed by the other multiplexer 1.
Since 5a2 to 15a16 and the integrating circuits 16a2 to 16a128 are also performed at the same time, all the read lines R1 to
When the pixel signals are read from R128 through the multiplexers 15a1 to 15a128, the image signals of all the pixels corresponding to one screen are stored in the frame memory 18 in a state in which the pixels of two adjacent columns are added. It will be.

Further, comparing the transmission timing of the clock signal C and the reset signal Re2 (see FIG. 8) in this two-pixel addition signal charge reading process with the case where pixel addition is not performed (see FIG. 5), pixel addition is performed. It can be seen that the timing does not change despite the presence.

As a result, the frame memory 18 stores charges corresponding to ½ of the pixels in the sensor group having a total pixel count of 2000 × 2000. That is, the total number of pixels of the thin detector using the sensor group can be changed to "1/2". That is, according to the present embodiment, it is possible to deal with the change in the number of pixels, which has not been conventionally dealt with in the thin detector.

The digital decoder 1 is controlled by the microprocessor 11 and the microprocessor 19.
While the sensor groups (first row and second row, third row and fourth row, ...) Which are adjacent to each other through 0 are simultaneously switched to read out the signal charge for every two rows, If addition is performed, it is possible to add 2 ² pixels at a time for the entire image. That is, the total number of pixels of the thin detector can be changed to "1/4", and the pixel shape after addition is a square, which makes it easy to execute filter processing in an image processing circuit (not shown). There is also a merit of becoming.

Furthermore, if a plurality of mode signal lines are prepared and the switching elements that are turned on at the same time are changed according to the combination, the number of pixels to be added can be increased by the number of the combination without changing the read timing. You can For example, four mode signal lines (first level to fourth level) are prepared, and the first level: normal one-column reading, the second level: two-column addition reading, the third
By setting level: 8-column addition reading, fourth level: 16-column addition reading, etc., pixel addition according to each level can be executed. Further, at this time, the digital decoder 10
The number of rows read simultaneously by, for example, 1st level: 1 row, 2nd level: 2 rows, 3rd level: 8 rows, 4th level
If the level is switched to 16 rows, pixel addition can be performed while the pixel shape after addition is held in a square shape.

On the other hand, modified examples of the multiplexer 15a1 and the integrating circuit 16a1 capable of executing the pixel addition described above are shown in FIGS. The multiplexer 2 shown in FIG.
5a1 is the multiplexer 15a shown in FIGS.
Compared with 1, the mode cannot be selected (mode signal is not sent). For other configurations,
Since the configuration is the same as that shown in FIGS. 3 to 8 described above, description thereof will be omitted.

Like the multiplexer 15a1 shown in FIG. 3, the multiplexer 25a1 shown in FIG. 9 sequentially turns on / off the switching elements sw1 one by one in synchronization with the falling edge of the clock pulse of the clock signal C.
To switch. Therefore, the microprocessor 19
Reset signal R sent from the multiplexer to the multiplexer 15a1
If the transmission timing of e2 is the same as the timing shown in FIGS. 5 and 8, pixel addition is not performed.

That is, in this modification, pixel addition is performed by changing the transmission timing of the reset signal Re2 sent from the microprocessor 19 to the multiplexer 11. Here, the waveform and output (operation) timing of the clock signal C, the first switching element sw1 to the second switching element sw2, the reset signal Re2, and the signal charge (image signal) in the signal charge reading process of the present modification are described. The time chart shown is shown in FIG.

In this modification, the microprocessor 19 is used.
The reset signal Re2 is sent to the integrating circuit 26a1 every two cycles of the clock pulse of the clock signal C at a timing a predetermined time before the falling edge of the pulse. Now, in synchronization with the fall of the clock pulse c1 having the clock signal C, the first switching element sw1 corresponding to the read line R1 is turned on by the processing of the multiplexer 15a1. This switching element sw
In response to 1 being ON, the first pixel signal is sent to the integrating circuit 26a1 via the read line R1 connected to the first switching element sw1. This first pixel signal is
It is integrated based on the time constant T determined by the capacitance Ca1 of the first capacitor 21a1, the read line and the resistance value r corresponding to that line, and saturates after a certain time. At this time, since the reset signal Re2 has not been sent, the multiplexer 15a1 processes the first switching element sw1 'to OFF and the read line R2 to the read line R2 in synchronism with the falling edge of the clock pulse c2 in the next stage. Corresponding second switching element sw 2 ′
Turns on (see FIG. 10). That is, the integrating circuit 26a1
Is not reset, the signal charge sent via the read line R2 and the second switching element sw2 'is superimposed and integrated on the first pixel signal. Therefore, the signal amplitude when the second pixel signal is sufficiently integrated is the sum of two pixels, as shown in FIG. Here, since the reset signal Re2 is sent to the integration circuit 26a1 a predetermined time before the falling timing of the next clock pulse c3, the electric charge accumulated in the first capacitor 21a1 is discharged in accordance with the reset signal Re2. It

Hereinafter, the pixel signals sent via the third switching element sw 3 ′ and the fourth switching element sw 4 ′ are similarly integrated by the integrating circuit 26a 1,
Hereinafter, the two-pixel addition is realized by sequentially and repeatedly integrating the fifth switching element sw 5 ′ and the sixth switching element sw 6 ′, ...

It should be noted that the transmission timing of the reset signal Re2 is delayed, for example, (1) 1 every 2 ² cycles of the clock signal.
If (1) is set to once in every 2 ³ cycles, 2 ² pixel addition in the case of (1), 2 ³ pixel addition in the case of (2), etc., pixel addition corresponding to the transmission timing of the reset signal Re2 is performed. realizable. Further, as described above, by controlling the digital decoder 10 and the microprocessor 11 in accordance with the number of added pixels in this pixel addition to simultaneously read out a plurality of adjacent rows, the added pixel shape is held in a square shape. As it is, pixel addition can be realized.

In this embodiment and the modification, the read circuit 12 is constructed as shown in FIG. 2. However, when a plurality of multiplexer ICs (16 in this embodiment) are used as a multiplexer, the integrator circuit is also used. Multiple (16
A) for integrating circuits 16a1 to 16a16 in order to use
One / D converter (indicated by 17a in the figure) may be provided, and a new multiplexer 30 may be provided between the integrating circuits 16a1 to 16a16 and the A / D converter 17a (see FIG. 11).
According to the read circuit 12a, the multiplexer 30
Responds to the control signal from the microprocessor 19,
The pixel signals sent from each of the integrating circuits 16a1 to 16a16 are sent to the A / D converter 17a while being sequentially switched. The multiplexers 15a1 to 15a16,
The structures of the integrating circuits 16a1 to 16a16, the A / D converter 17a, and the frame memory 18 are the same as those shown in FIG. Further, in the present embodiment, the read line is divided into 16 groups, a plurality (16) of multiplexers are provided corresponding to this group, and the read line in each group is selected by the multiplexer. The invention is not limited to this. For example, the readout circuit may include one multiplexer and one integration circuit. In this case, the multiplexer selects a single output line (for example, the first line R1) from all the read lines R1 to R2000, and switches to the next line in sequence (line R2, line R3,
…). Then, the integrating circuit integrates the signal output from the multiplexer. That is, in this configuration, it takes time to sequentially read all the read lines, but on the other hand, only one integrating circuit needs to be provided, so that the circuit configuration becomes very small.

When the read circuit includes a plurality of multiplexers and a plurality of integration circuits, the number of the multiplexers (and integration circuits) is 2 ^k (k) when the number of read lines assigned to each multiplexer is 2. = 1,2,
...) may be set.

(Second Embodiment) FIG. 12 shows a sensor (PD3, storage capacitor 4, TFT 5) constituting one pixel in the first embodiment, a read line R1, and an integrating circuit 1.
It is a typical block diagram which shows 6a1. In the figure, Ca is the capacitance of the storage capacitor 4, and RDS is the TFT 5
Is a resistance value between the drain (D) and the source (S) of the. 13 shows a waveform diagram of the drive pulse voltage VGS sent from the microprocessor 11 to the gate terminal (G) of the TFT 5 via the digital decoder 10. The configuration of the other sensor groups is the same as the configuration shown in FIG. 12, and the description thereof will be omitted. The other components are the same as those shown in FIGS. 1 and 2, and the description thereof will be omitted.

According to FIGS. 12 and 13, switching ON / OFF of the TFT 5 is controlled by the drive pulse voltage VGS sent to the gate terminal (G) of the TFT 5. That is, when the voltage value (peak value) of the drive pulse voltage VGS is VON, the TFT 5 is turned on.
When the driving voltage pulse VGS has the voltage value VOFF, the TFT 5 is turned off.

When the TFT 5 is in the ON state, the signal charge (pixel signal) stored in the storage capacitor 4 is an exponential function of the time constant “τ = Ca (RDS + RL)” and the integration circuit 16a1.
Capacitor 21a1 (when RDS is constant). RL is the resistance value of the read line itself.

Since the above-mentioned time constant is generally desired to be small from the viewpoint of noise reduction, it has been set to a value corresponding to the noise reduction request.

On the other hand, when using a thin (X-ray) detector, it is required to change the frame rate according to the movement of the subject. However, in the conventional thin detector, the signal charge has the constant time constant “τ = Ca (RDS + RL)” regardless of the change of the frame rate.
Since the signal charge was sent to a1, the frame rate (sampling rate) is set to a high value, and the A / D converter 17a1 does not move enough to move the signal charge to the integrating circuit 16a1.
Could be sampled by. Due to this problem, the conventional thin detector cannot cope with the change of the frame rate.

In the present embodiment, when the frame rate is changed, the time constant of the integrating circuit 16a1 is switched back according to the change, thereby solving the above-mentioned problem and detecting the X-ray which can cope with the change of the frame rate. To provide a container.

Here, the VGS-RDS characteristics of the TFT 5 are shown in FIG.
It is shown in FIG. According to this FIG. 14, the TFT 5 is
Increase the peak value of drive pulse VGS that turns on T5 (VGS =
When V2) is applied, RDS decreases (RDS = R2a) and the time constant τ can be reduced. Also, when the peak value of VGS is decreased (VGS = V1), RDS increases (RDS =
R1a) and the time constant τ can be increased.

Next, the overall operation of this embodiment using the above characteristics will be described.

Now, in the thin detector 1 during shooting at a certain frame rate (normal relatively slow shooting frame rate), the voltage value of the drive pulse for the normal TFT drive is set to "VGS = V1", and , The drain of TFT5 ~
The resistance value between the sources is “RDS = R1a”. At this time,
When a frame rate change command for setting a frame rate higher than the current frame rate is sent from the input unit 13 to the microprocessor 11 and the microprocessor 19, the microprocessor 11 and the microprocessor 19 are as shown in FIG. To read the frame rate change command sent to each (step S
1). Then, based on the sent frame rate change command, the microprocessor 11 changes the peak value of the drive pulse of the TFT 5 to the optimum value "VGS" for the changed frame rate.
= V2> V1 "(step S2), and the TFT 5 is driven by this drive pulse VGS (step S2).
3). On the other hand, the microprocessor 19 changes (increases) the sampling rate of the A / D converter 17a1 based on the sent frame rate change command (step S).
4). Thereafter, the signal charges are sequentially read out (step S5), and the process ends.

Since the voltage value of the drive pulse is "VGS = V2>V1" by the processing of step S2 described above, the resistance value RDS between the drain and the source at this time is "RDS =
Since R2a <R1a ”(see FIG. 14), the time constant τ can be reduced. Therefore, the signal charge can be moved to the integrating circuit 16a1 faster than during normal photographing, and even if the sampling rate of the A / D converter 17a1 is changed by the process of step S4, the signal charge is not left unread. . When returning the frame rate to the normal rate, the steps S1 to S are performed.
In the process of 3, VGS is changed to "VGS = V1 <V2".
, "RDS = R1a>R2a", and it is possible to return to the normal shooting state.

That is, in the present embodiment, the unread portion of the signal charge can be eliminated by switching to the preset time constant based on the optimum reading corresponding to the change of the frame rate.

Although the other components of the X-ray detector 1 are the same as those shown in FIGS. 1 and 2, the present invention is not limited to this, and the first embodiment can be applied. The same effect can be obtained by using the reading circuit 12 shown in FIG. 18 instead of the reading circuit 12 shown in the related art, in which a integrating circuit is provided for each reading line.

By the way, the resistance value RL of the line itself that contributes to the time constant τ when moving from the storage capacitor 4 to the integrating circuit 16a1 is determined by the read line R1 between each sensor (pixel) and the amplifier 20a1 of the integrating circuit 16a1. Increases in proportion to the distance. Therefore, for example, the read line distance is different between the first row sensor group corresponding to the switching line L1 and the 2000th row sensor group corresponding to the switching line L2000 (see FIG. 16,
The multiplexer 15a1 is omitted.) As a result, the value of RL is different.

The difference in the resistance value RL among the sensor groups in each row causes a variation in the time constant τ between the sensor groups. However, since the sampling rate of the A / D converter 17a1 is a predetermined rate corresponding to the frame rate, the above-mentioned unread portion of the signal charge (pixel charge) has occurred depending on the sensor group.

Therefore, using the points of this embodiment,
In the modification described below, the peak value of the drive pulse of the TFT 5 is changed according to the difference in the distance of the read line, and the resistance value RDS between the drain and source of the TFT 5 is changed according to the change of RL. By keeping the time constant τ constant, the pixel charge is left unread.

This modification will be described below. The configuration of the X-ray detector 1 is the same as that of the second embodiment described above, and therefore the description thereof is omitted.

In the internal memory of the microprocessor 11 of this modification, the difference in resistance value RL due to the difference in the read line distance within the pixel group of each row is stored in advance. In the present modification, for example, when the resistance value RL1 at the distance of the read line of the pixel group of the first row is used as a reference, the resistance value RL1 and the read lines of the second to 2000th rows are set. The difference between the corresponding resistance values RL2 to RL2000 (ΔR1 (| RL1−RL2 |), ΔR2 (| RL1−RL3
.), ..., .DELTA.R1999 (| RL1-RL2000 |) are stored.

The overall operation of this modification will be described below.

When sequentially reading out the pixel group from the first row, the microprocessor 11 sets the peak value of the drive pulse of the TFT 5 to a predetermined value "VGS = V1b" (resistance value between the drain and source of the TFT 5). Also becomes "RDS = R1a")
(FIG. 17, step S10), the TF corresponding to the pixel groups S1,1 to S1,2000 in the first row is generated by this drive pulse VGS.
T5 is driven (step S20). As a result, the first
The signal charge from the pixel groups S1,1 to S1,2000 in the row is TFT5.
Read through. Then, the microprocessor 1
1 reads the resistance value ΔR1 from the internal memory, and the resistance value “RDS
= R1b "is reduced (R1b → R2b) to set the peak value" VGS = V2b "of the drive pulse of the TFT 5 (step S30). Then, the microprocessor 11 uses the drive pulse VGS to set the pixel groups S2,1 to S2,20 in the second row.
The TFT5 corresponding to 00 is driven (step S4
0). At this time, the time constant τ when the signal charges of the pixel groups S2,1 to S2,2000 of the second row are sent to the integrating circuits 16a1 to 16a16 is as much as the resistance value of the readout line ΔR1 increases. Since the resistance value RDS between the drain and the source has decreased, the resistance value RDS is maintained at a constant value as a whole. Hereinafter, T of the pixel group of the third row to the 2000th row
FT stores the resistance values ΔR2 to ΔR1999 stored in the internal memory.
Are sequentially driven by the drive pulse having the peak value according to, the signal charges of the pixel groups of the third row to the 2000th row are read out (step S50), and the process is completed.

That is, since the change in the resistance value due to the difference in the distance of the read line of the pixel group in each row is canceled by changing the peak value of the drive pulse of the TFT, the variation in the time constant due to the change in the resistance value is caused. It is possible to eliminate the unread portion of the pixel charge.

The second embodiment and this modification may be used in combination, and the respective effects can be obtained together. In addition, the second embodiment and this modification are the first
You may use, combining with an Example and its modification, and each effect can be acquired together.

Further, the same effect can be obtained even when this modification is used in the conventional structure (FIG. 18), in which an integrating circuit is provided for each read line.

Although the X-ray detector is used as the radiation plane detector in the embodiments of the present application, the present invention is not limited to this. That is, the radiation is not limited to X-rays and may be other radiation such as γ-rays.

Further, in the present embodiment, the case where an indirect X-ray sensor composed of a fluorescent screen and a photo sensor is used as a sensor for detecting an X-ray source has been described.
It can also be applied when using a direct type X-ray sensor that directly converts the intensity of a line into a charge signal.

[0112]

According to the radiation plane detector described in any one of claims 1 to 9 and the radiation image pickup device described in claim 17, the signal charges read in parallel via a plurality of read lines are at least 1. A plurality of signal charges read from a plurality of lines are converted into serial signals in time series by a multiplexer, which is a component of one conversion means. Then, these serial signals are integrated by the integrating means inserted in the output path of each multiplexer to form a pixel signal. Therefore, it is possible to integrate a plurality of signal charges read in parallel through a plurality of read lines without providing an integrating means for each read line, and an integrating means is provided for each read line. In this case, it is not necessary to adjust a compensating circuit for compensating the occurrence of fixed pattern noise and individual integrating means.
As a result, the entire apparatus equipped with the radiation flat panel detector can be downsized, and the effective space of the entire apparatus can be increased. In addition, it is possible to reduce the burden on the operator and reduce the overall imaging time as the adjustment time is shortened.

In particular, according to the radiation plane detector of the seventh or eighth aspect, each pixel signal obtained by integrating by each integrating means corresponds to the number of adjacent signal charges switched by each multiplexer. , Or “the number of readout rows × the number of readouts of the multiplexer” is added and output. That is, since it is possible to realize the addition of the signal charges detected by the respective sensors of the radiation detection unit, that is, the pixel addition, it is possible to deal with a change in the total number of pixels.

Further, in particular, in the radiation plane detector described in claim 9, since each of the integrators is reset in response to the timing when a predetermined number of signal charges are output from each of the multiplexers, the integrator is integrated. The formed pixel signals are added with the signal charges of the number output from each multiplexer. That is, since it is possible to realize the addition of the signal charges detected by the respective sensors of the radiation detection unit, that is, the pixel addition, it is possible to deal with a change in the total number of pixels.

Further, according to the radiation plane detector of the tenth to fourteenth aspects, when the frame rate is changed to, for example, a high rate, the peak value control means of the read control means responds to the change of the frame rate. Since the crest value of the drive pulse for driving the switching element such as the thin film transistor is set to be higher than the crest value corresponding to the current frame rate, the resistance RDS between the drain and source of the thin film transistor is reduced, and the time constant is reduced. Becomes smaller. As a result, the movement of the signal charge to the integrating means becomes faster, the unread portion of the signal charge, which was a problem associated with the change of the frame rate, is eliminated, and a radiation plane detector capable of coping with the change of the frame rate is provided. be able to.

According to the radiation plane detector of the fourteenth to sixteenth aspects, the drive pulse for driving the switching element such as the thin film transistor is determined according to the distance from each row of the plurality of sensors of the radiation detecting section to the integrating means. Since the crest value is controlled, the time constant of the signal charge of each radiation detecting section sent to the integrating means is set to a substantially constant value. In other words, since the time constant is maintained substantially constant regardless of the difference in the distance from each row of the plurality of sensors of the radiation detecting unit to the integrating means, the difference in the moving speed of the signal charges to the integrating means due to the difference in the time constant is different. Will be resolved. As a result, it is possible to eliminate the unread portion of the signal charges due to the difference in the moving speed.

[Brief description of drawings]

FIG. 1 is a view showing an X-ray image pickup apparatus according to an embodiment of the present invention.
The schematic block diagram which shows a part of X-ray detector which has the sensor element arranged in dimension.

FIG. 2 is a diagram showing a schematic configuration of a read circuit in FIG.

3 is a diagram for explaining a normal operation of a multiplexer and an integrating circuit in FIG.

FIG. 4 is a diagram for explaining an operation of a switching element of the multiplexer in FIG.

FIG. 5 is a time chart showing waveforms and output (operation) timings of the mode signal, the clock signal, the switching element, the reset signal, and the pixel signal in FIGS. 3 and 4.

FIG. 6 is a diagram for explaining the operation of the multiplexer and the integrating circuit in FIG. 2 when adding two pixels.

FIG. 7 is a diagram for explaining the operation of the switching element of the multiplexer in FIG. 2 when adding two pixels.

FIG. 8 is a time chart showing waveforms and output (operation) timings of the mode signal, the clock signal, the switching element, the reset signal, and the pixel signal in FIGS. 6 and 7.

9 is a diagram for explaining the operation of the multiplexer and the integrating circuit in FIG. 2 when adding two pixels.

10 is a time chart showing waveforms and output (operation) timings of the clock signal, the switching element, the reset signal, and the pixel signal in FIG.

11 is a diagram showing another configuration of the read circuit in FIG.

FIG. 12 is a schematic configuration diagram showing a sensor, a read line, and an integrating circuit in an example.

FIG. 13 is a waveform diagram showing a drive pulse voltage for driving a digital decoder.

FIG. 14 is a graph showing VGS-RDS characteristics of TFT.

FIG. 15 is a microprocessor 19 in the second embodiment.
2 is a schematic flowchart showing an example of the above process.

FIG. 16 is a diagram showing a positional relationship between each sensor and an integrating circuit.

FIG. 17 is a schematic flowchart showing an example of processing of a microprocessor 11 according to a modified example.

FIG. 18 is a schematic configuration diagram showing a part of a radiation plane detector having conventional two-dimensionally arranged sensor elements.

[Explanation of symbols]

1 X-ray detector 2 X-ray source 3 Photodiode 4 Storage capacitor 5 Field effect transistor 6 DC voltage source 10 Digital decoder 11 Microprocessor 12 Readout circuit 13 Input section 15a1 to 15a16 Analog multiplexer 16a1 to 16a16 Integration circuit 17a1 to 17a16 A / D converter 18 frame memory 19 microprocessor 20a1 to 20a16 amplifier 21a1 to 21a16 first capacitor 22a1 to 22a16 second capacitor 23a1 to 23a16 first switch 24a1 to 24a16 second switch L1 to L2000 switching line R1 to R2000 reading Line sw1 to sw2000 Switching element S1,1 to S2000,2000 Sensor L, H mode signal C Clock signal c1 Clock pulse c2 Clock pulse Re1 Reset signal Re2 The drain of the set signal RDS TFT (D) ~ source (S) resistance VGS drive pulse voltage Ca resistance capacitance RL1~RL2000 read line of the storage capacitor between

Claims (17)

[Claims] 1. A radiation flat panel detector comprising a radiation detecting section in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix, wherein each row of the plurality of sensors of the radiation detecting section is provided. A plurality of reading lines for reading the signal charges, a reading means for reading the signal charges detected by each sensor of the radiation detecting unit in parallel through the plurality of reading lines, and the plurality of reading lines. At least one conversion means for inputting in parallel a plurality of signal charges read out from a plurality of set lines and converting the parallel input signal into a time-series serial signal, and each of the conversion means. And an integrating means for forming a pixel signal by integrating the serial signal output from the converting means and inserted in the output path of the converting means. Radiation flat panel detector. 2. The radiation plane detector according to claim 1, wherein each of the conversion means includes a multiple input and single output type multiplexer corresponding to the multiple lines. 3. The radiation plane detector according to claim 1, wherein the read-out means includes a switching element for each sensor, and the signal charge is read out from each sensor by driving each switching element. 4. Each of the sensors includes a phosphor screen that receives the radiation and converts it into an optical signal, a photodiode that detects the optical signal as a signal charge, and a capacitor that stores the signal charge. The radiation plane detector according to claim 3, wherein the switching element and the sensor are formed by thin film technology. 5. The radiation plane detector according to claim 3, wherein the plurality of lines correspond to all the plurality of read lines, and the number of the multiplexers is one. 6. Each of the multiplexers simultaneously outputs the signal charge of the first input line in response to a predetermined output timing, and then sequentially outputs the second and subsequent input lines in accordance with the output timing. The radiation plane detector according to claim 3, wherein 7. The radiation plane detection system according to claim 3, further comprising switching control means for sending to each of said multiplexers a control signal for switching and outputting a plurality of adjacent signal charges input to said multiplexers. vessel. 8. The read-out means reads out the signal charges detected by the respective sensors by driving the respective switching elements in units of a plurality of rows, and the switching control means, with respect to the respective multiplexers, the respective multiplexers. 8. The radiation flat panel detector according to claim 7, wherein a plurality of signal charges input to the switch are output by switching a plurality of adjacent signal charges corresponding to the number of rows. 9. A reset signal for resetting each of the integrators inserted in the output path of each of the multiplexers according to the timing at which a predetermined number of signal charges are output from each of the multiplexers. The radiation plane detector according to claim 3, further comprising control means. 10. A radiation detection unit in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix, and the signal charges provided for each column of the plurality of sensors of the radiation detection unit. A plurality of read lines for reading, a switching element provided for each sensor of the radiation detection unit, and a driving pulse is supplied to each switching element to drive the switching element, thereby detecting by each sensor. Radiation provided with readout control means for reading out the generated signal charges through the readout line, and signal conversion means for converting pixel signals obtained based on the signal charges read out by the readout means into digital image signals. A flat panel detector, which is provided for each of the plurality of read lines and is read through the read lines. In addition to an integration unit that integrates the signal charge to form the pixel signal and a frame rate changing unit that changes the frame rate, the read control unit changes the peak value of the drive pulse according to the change of the frame rate. A radiation plane detector comprising means for controlling. 11. A radiation detection unit in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix, and the signal charges provided for each column of the plurality of sensors of the radiation detection unit. A plurality of read lines for reading, a switching element provided for each sensor of the radiation detection unit, and a driving pulse is supplied to each switching element to drive the switching element, thereby detecting by each sensor. The readout control means for reading out the generated signal charges in parallel through the plurality of readout lines, and the pixel signal obtained based on the signal charges read out by the readout means are sampled according to a predetermined frame rate. A radiation plane detector comprising a signal converting means for converting into a digital image signal,
At least one conversion means for inputting in parallel a plurality of signal charges read from a plurality of set lines out of the plurality of read lines and converting the parallel input signals into a time-series serial signal; In addition to the integration means that is inserted into each output path of the conversion means and that integrates the serial signal output from the conversion means to form the pixel signal, and the frame rate change means that changes the frame rate. The radiation plane detector is characterized in that the read control means includes means for controlling the peak value of the drive pulse according to the change of the frame rate. 12. The radiation plane detector according to claim 10, wherein the switching element is a thin film transistor. 13. The crest value control means sets the crest value of the drive pulse to the current crest value when the frame rate changing means changes the frame rate to a rate higher than the current frame rate. The radiation plane detector according to claim 10, wherein the radiation plane detector is set higher than the radiation plane detector. 14. A radiation flat panel detector comprising a radiation detecting section in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix, wherein each row of the plurality of sensors of the radiation detecting section is provided. A plurality of reading lines for reading the signal charges provided in the switching element, a switching element provided for each sensor of the radiation detecting section, and a drive pulse supplied to each switching element to drive the switching element. The read control means for reading the signal charge detected by each sensor through the read line and the pixel charge by integrating the signal charge read through the read line by the read control means. And a read-out control means of the plurality of sensors of the radiation detection unit. A means for controlling the crest value of the drive pulse according to the distance from the row to the integrating means is provided, and the time constant of the signal charge of each radiation detecting section sent to the integrating means is controlled by this crest value to be substantially constant. A radiation plane detector characterized by being set to a value. 15. A radiation flat panel detector comprising a radiation detecting section in which sensors for accumulating signal charges corresponding to the intensity of incident radiation are arranged in a matrix, wherein each row of the plurality of sensors of the radiation detecting section is arranged. A plurality of reading lines for reading the signal charges provided in the switching element, a switching element provided for each sensor of the radiation detecting section, and a drive pulse supplied to each switching element to drive the switching element. The read control means for reading the signal charges detected by the respective sensors in parallel via the plurality of read lines, and the plurality of signal charges read from the set plurality of read lines among the plurality of read lines At least one conversion means for inputting in parallel as a set and converting the parallel input signals into time-series serial signals , And an integrating means that is inserted into each output path of the converting means and that integrates the serial signals output from the converting means to form a pixel signal, and the read control means is provided for the radiation detecting section. A means for controlling the crest value of the drive pulse according to the distance from each row of a plurality of sensors to the integrating means is provided, and the time constant of the signal charge of each radiation detection unit sent to the integrating means by the control of this crest value. The radiation plane detector is characterized in that is set to a substantially constant value. 16. The radiation plane detector according to claim 14, wherein the switching element is a thin film transistor. 17. A radiation detecting section, in which sensors for accumulating signal charges corresponding to the intensity of radiation such as X-rays transmitted through an incident subject are arranged in a matrix, and is obtained based on the signal charges. In a radiation imaging apparatus configured to image the inside of the subject based on pixel signals, a plurality of read lines for reading the signal charges provided for each column of the plurality of sensors of the radiation detection unit, and the radiation A reading unit that reads the signal charges detected by the respective sensors of the detection unit in parallel through the plurality of reading lines, and a set of a plurality of signal charges that are read from a plurality of set reading lines of the plurality of reading lines. At least one conversion means for inputting in parallel and converting the parallel input signal into a time-series serial signal, and an output path of each of the conversion means. It is and radiation imaging apparatus by integrating the serial signal output from the converting means, characterized in that it comprises an integration means for forming the pixel signal.