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JPH09181256A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH09181256A
JPH09181256A JP33662895A JP33662895A JPH09181256A JP H09181256 A JPH09181256 A JP H09181256A JP 33662895 A JP33662895 A JP 33662895A JP 33662895 A JP33662895 A JP 33662895A JP H09181256 A JPH09181256 A JP H09181256A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
wiring pattern
external connection
element mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33662895A
Other languages
Japanese (ja)
Other versions
JP3466354B2 (en
Inventor
Sunao Arai
直 荒井
Hiroshi Miyagawa
弘志 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP33662895A priority Critical patent/JP3466354B2/en
Publication of JPH09181256A publication Critical patent/JPH09181256A/en
Application granted granted Critical
Publication of JP3466354B2 publication Critical patent/JP3466354B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture a multichip module semiconductor device at a low cost. SOLUTION: A plurality of semiconductor elements 6 is mounted on a semiconductor element mounting substrate 30 made of a resin while the elements 6 are electrically connected to a wiring pattern 30a formed on one surface of the substrate 30 and the peripheral edge section of the other surface of the substrate 30 is joined to the peripheral edge section of a through hole 22 formed through an external connecting terminal supporting substrate 20 made of resin. Then a wiring pattern 20a formed on the joining surface of the substrate 20 is electrically connected to the wiring pattern 30a formed on the surface of the substrate 30 and external connecting terminals 21 provided on the other surface of the substrate 20 and the semiconductor elements 6 are sealed with resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
より詳細にはマルチチップモジュール(MCM)構造を
有する半導体装置に関する。
The present invention relates to a semiconductor device,
More specifically, it relates to a semiconductor device having a multi-chip module (MCM) structure.

【0002】[0002]

【従来の技術】半導体素子の高集積化、高速化ととも
に、これらの特性を十分に発揮するための半導体パッケ
ージがいろいろと考えられている。このうちマルチチッ
プモジュールは半導体素子を接近させて配置することに
より半導体素子間の信号の遅延を小さくして高速化に対
応しようとするものである。マルチチップモジュールは
図11に示すようなセラミックの基板5上に半導体素子
6を搭載したタイプの製品が一般的である。7は薄膜配
線層、8はベース基板、9は封止樹脂である。
2. Description of the Related Art Various semiconductor packages have been considered for fully exhibiting these characteristics as semiconductor elements become highly integrated and operate at high speed. Among them, the multi-chip module aims to reduce the signal delay between the semiconductor elements by arranging the semiconductor elements close to each other to cope with high speed. The multi-chip module is generally a type of product in which the semiconductor element 6 is mounted on the ceramic substrate 5 as shown in FIG. Reference numeral 7 is a thin film wiring layer, 8 is a base substrate, and 9 is a sealing resin.

【0003】しかしながら、このようなセラミックの基
板を使用するマルチチップモジュールは製造コストがか
かることから、より低コストで生産できる製品として基
板に樹脂基板を使用し、この基板に半導体素子を実装し
て樹脂封止する製品が考えられている。図12は基板に
樹脂基板10を使用して半導体素子6を搭載した半導体
装置である。この半導体装置は外部接続端子としてはん
だボール11を使用したBGAタイプの製品である。1
2は配線パターン、13はスルーホール、14はソルダ
ーレジストである。
However, since a multi-chip module using such a ceramic substrate requires a high manufacturing cost, a resin substrate is used as a substrate as a product which can be manufactured at a lower cost, and a semiconductor element is mounted on this substrate. Resin-encapsulated products are being considered. FIG. 12 shows a semiconductor device in which the semiconductor element 6 is mounted on the substrate by using the resin substrate 10. This semiconductor device is a BGA type product using solder balls 11 as external connection terminals. 1
Reference numeral 2 is a wiring pattern, 13 is a through hole, and 14 is a solder resist.

【0004】[0004]

【発明が解決しようとする課題】ところで、従来のマル
チチップモジュールは搭載する半導体素子の種類や配置
に合わせて配線パターン等を形成するから製品ごとに専
用の基板を製作する必要があり、異種製品で共通に基板
を使用するといったことができないことから、これが製
造コストのかかる原因になっている。本発明はこのよう
なマルチチップモジュール型の半導体装置において、異
種製品に対しても汎用的な使用を可能にして、半導体装
置全体としての製造コストを引き下げることができる半
導体装置を提供することを目的としている。
By the way, in the conventional multi-chip module, since the wiring pattern and the like are formed in accordance with the type and arrangement of the semiconductor elements to be mounted, it is necessary to manufacture a dedicated substrate for each product. This is a cause of high manufacturing cost because it is not possible to use a common substrate. It is an object of the present invention to provide a semiconductor device in such a multi-chip module type semiconductor device that can be used universally for different kinds of products and can reduce the manufacturing cost of the entire semiconductor device. I am trying.

【0005】[0005]

【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、樹脂基板からな
る半導体素子搭載基板の一方の面に形成された配線パタ
ーンと電気的に接続されて複数個の半導体素子が搭載さ
れ、前記半導体素子搭載基板の他方の面の周縁部が樹脂
基板からなる外部接続端子支持基板に透設された透孔の
周縁部に接合されるとともに、該外部接続端子支持基板
の接合面側に形成された配線パターンと前記半導体素子
搭載基板に形成された配線パターンとが、及び、該外部
接続端子支持基板の接合面側に形成された配線パターン
と前記外部接続端子支持基板の他面側に設けられた外部
接続端子とが電気的に接続され、前記半導体素子が樹脂
封止されたことを特徴とする。また、前記半導体素子搭
載基板の他方の面に配線パターンが形成され、該配線パ
ターンと電気的に接続されて半導体素子が搭載され、該
配線パターンと半導体素子搭載基板の一方の面に形成さ
れた配線パターンまたは外部接続端子支持基板の接合面
側に形成された配線パターンとが電気的に接続されたこ
とを特徴とする。また、前記半導体素子搭載基板の一方
の面に形成された配線パターンと外部接続端子支持基板
の接合面側に形成された配線パターンとがボンディング
ワイヤまたは半導体素子搭載基板に形成されたスルーホ
ールにより電気的に接続されたことを特徴とする。ま
た、前記半導体素子搭載基板の他方の面に形成された配
線パターンと外部接続端子支持基板の接合面側に形成さ
れた配線パターンとがはんだにより電気的に接続された
ことを特徴とする。また、前記半導体素子搭載基板の周
縁部と外部接続端子支持基板に透設された透孔の周縁部
とが接着剤により接合されていることを特徴とする。ま
た、前記外部接続端子がはんだボールであることを特徴
とする。また、前記半導体素子がポッティング法により
樹脂封止されたことを特徴とする。
The present invention has the following constitution in order to achieve the above object. That is, a plurality of semiconductor elements are mounted by being electrically connected to a wiring pattern formed on one surface of a semiconductor element mounting substrate made of a resin substrate, and a peripheral portion of the other surface of the semiconductor element mounting substrate is a resin. The wiring pattern is formed on the semiconductor element mounting board and the wiring pattern formed on the joining surface side of the external connection terminal supporting board while being joined to the peripheral portion of the through hole formed on the external connecting terminal supporting board formed of the board. A wiring pattern, and a wiring pattern formed on the bonding surface side of the external connection terminal support substrate and an external connection terminal provided on the other surface side of the external connection terminal support substrate are electrically connected, The semiconductor element is resin-sealed. A wiring pattern is formed on the other surface of the semiconductor element mounting substrate, a semiconductor element is mounted by being electrically connected to the wiring pattern, and the wiring pattern is formed on one surface of the semiconductor element mounting substrate. The wiring pattern or the wiring pattern formed on the joint surface side of the external connection terminal supporting substrate is electrically connected. In addition, the wiring pattern formed on one surface of the semiconductor element mounting substrate and the wiring pattern formed on the bonding surface side of the external connection terminal supporting substrate are electrically connected by bonding wires or through holes formed in the semiconductor element mounting substrate. It is characterized in that they are connected to each other. Further, the wiring pattern formed on the other surface of the semiconductor element mounting substrate and the wiring pattern formed on the joint surface side of the external connection terminal supporting substrate are electrically connected by solder. Further, the semiconductor device mounting substrate is characterized in that the peripheral region thereof and the peripheral region of a through hole provided in the external connection terminal supporting substrate are bonded by an adhesive. Further, the external connection terminals are solder balls. Further, the semiconductor element is resin-sealed by a potting method.

【0006】[0006]

【発明の実施の形態】以下、本発明の好適な実施形態に
ついて説明する。図1は本発明に係る半導体装置の構成
を示す断面図である。図で20は外部接続端子支持基
板、30は半導体素子6を搭載するための半導体素子搭
載基板である。外部接続端子支持基板20および半導体
素子搭載基板30はともに樹脂基板を基板材としたもの
である。40は半導体素子6を封止する封止樹脂であ
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. FIG. 1 is a sectional view showing the structure of a semiconductor device according to the present invention. In the figure, 20 is an external connection terminal supporting substrate, and 30 is a semiconductor element mounting substrate for mounting the semiconductor element 6. Both the external connection terminal support substrate 20 and the semiconductor element mounting substrate 30 are made of resin substrates. 40 is a sealing resin for sealing the semiconductor element 6.

【0007】外部接続端子支持基板20ははんだボール
あるいはリードピン等の外部接続端子21を接合して支
持するとともに、半導体素子搭載基板30を接合して支
持する支持基板として用いられる。外部接続端子支持基
板20の中央部には半導体素子搭載基板30を接合する
ため、矩形状の透孔22を透設する。また、外部接続端
子支持基板20の一方の面には配線パターン20aが設
けられ、他方の面には外部接続端子21を接続するラン
ド部20bが設けられる。配線パターン20aとランド
部20bとの電気的接続は樹脂基板を厚さ方向に貫通し
て設けたスルーホール20cを介してなされる。スルー
ホール20cは樹脂基板に貫通孔を設け、めっきにより
この貫通孔の内壁面に導体層を設けて形成したものであ
る。
The external connection terminal support substrate 20 is used as a support substrate for bonding and supporting the external connection terminals 21 such as solder balls or lead pins and for bonding and supporting the semiconductor element mounting substrate 30. In order to join the semiconductor element mounting substrate 30 to the central portion of the external connection terminal supporting substrate 20, a rectangular through hole 22 is provided through. A wiring pattern 20a is provided on one surface of the external connection terminal support substrate 20, and a land portion 20b for connecting the external connection terminal 21 is provided on the other surface. The electrical connection between the wiring pattern 20a and the land portion 20b is made through a through hole 20c that penetrates the resin substrate in the thickness direction. The through hole 20c is formed by forming a through hole in the resin substrate and forming a conductor layer on the inner wall surface of the through hole by plating.

【0008】本実施形態の外部接続端子支持基板20で
はその外周縁側にスルーホール20cが配置されてお
り、外部接続端子支持基板20の一方の面では配線パタ
ーン20aの端部が外部接続端子支持基板20の外周縁
側に引き出されて各々スルーホール20cに接続され、
外部接続端子支持基板20の他方の面では各々のスルー
ホール20cからアレイ状に配置されたランド部20b
に配線パターンが引き出されランド部20bと各スルー
ホール20cとが接続されている。ランド部20bには
外部接続端子21としてはんだボールが接合されてい
る。外部接続端子21としてリードピンを使用する場合
には、ランド部20bを設けずにスルーホール20cに
リードピンを挿入して装着する。
In the external connection terminal supporting board 20 of the present embodiment, the through holes 20c are arranged on the outer peripheral edge side, and the end portion of the wiring pattern 20a on one surface of the external connection terminal supporting board 20 is the external connection terminal supporting board. 20 are connected to the through holes 20c by being pulled out to the outer peripheral edge side,
On the other surface of the external connection terminal supporting substrate 20, the land portions 20b arranged in an array from the respective through holes 20c.
A wiring pattern is drawn out to connect the land portion 20b and each through hole 20c. Solder balls are joined to the land portions 20b as the external connection terminals 21. When a lead pin is used as the external connection terminal 21, the lead pin is inserted into the through hole 20c and mounted without providing the land portion 20b.

【0009】半導体素子搭載基板30は外部接続端子支
持基板20の透孔22の周縁部に接合して支持するた
め、透孔22よりも若干大きめの矩形の板状に形成され
る。半導体素子搭載基板30にはマルチチップモジュー
ルと同様に複数個の半導体素子6を搭載可能に設け、各
々の半導体素子6と外部接続端子支持基板20に取り付
けた外部接続端子21とが電気的に接続される。
Since the semiconductor element mounting substrate 30 is joined to and supported by the peripheral portion of the through hole 22 of the external connection terminal supporting substrate 20, it is formed in a rectangular plate shape slightly larger than the through hole 22. The semiconductor element mounting substrate 30 is provided with a plurality of semiconductor elements 6 that can be mounted similarly to the multi-chip module, and each semiconductor element 6 and the external connection terminal 21 mounted on the external connection terminal support substrate 20 are electrically connected. To be done.

【0010】本実施形態の半導体素子搭載基板30では
基板の両面に配線パターン30a、30bを設け、基板
の両面に半導体素子6を搭載し、各々の半導体素子6と
配線パターン30a、30bとを電気的に接続してい
る。半導体素子6と配線パターン30a、30bとの電
気的接続は本実施形態ではワイヤボンディング法によっ
ているが、その接続方法はワイヤボンディング法に限ら
ずフリップチップボンディング法等の他の方法を利用し
てもよい。
In the semiconductor element mounting substrate 30 of this embodiment, wiring patterns 30a and 30b are provided on both sides of the substrate, the semiconductor element 6 is mounted on both sides of the substrate, and each semiconductor element 6 and the wiring patterns 30a and 30b are electrically connected. Connected to each other. The electrical connection between the semiconductor element 6 and the wiring patterns 30a and 30b is performed by the wire bonding method in the present embodiment, but the connection method is not limited to the wire bonding method and other methods such as a flip chip bonding method may be used. Good.

【0011】半導体素子搭載基板30に搭載した半導体
素子6と外部接続端子21との電気的接続は、半導体素
子搭載基板30の配線パターン30a、30bとこの半
導体素子搭載基板30を接合する外部接続端子支持基板
20の接合面に形成された配線パターン20aとを電気
的に接続することによってなされる。この半導体素子搭
載基板30の配線パターン30a、30bと外部接続端
子支持基板20の接合面に形成された配線パターン20
aとを電気的に接続する方法にはいくつかの方法がある
が、本実施形態では半導体素子搭載基板30の一方の面
に形成した配線パターン30aと外部接続端子支持基板
20の配線パターン20aとをワイヤボンディング法に
より接続し、半導体素子搭載基板30の他方の面に形成
した配線パターン30bと外部接続端子支持基板20の
配線パターン20bとははんだ23によって接続してい
る。
The electrical connection between the semiconductor element 6 mounted on the semiconductor element mounting board 30 and the external connection terminals 21 is performed by connecting the wiring patterns 30a and 30b of the semiconductor element mounting board 30 to the external connection terminals that join the semiconductor element mounting board 30. This is performed by electrically connecting the wiring pattern 20a formed on the bonding surface of the support substrate 20. The wiring pattern 20 formed on the joint surface between the wiring patterns 30a and 30b of the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 20.
There are several methods for electrically connecting a to the a, but in the present embodiment, the wiring pattern 30a formed on one surface of the semiconductor element mounting substrate 30 and the wiring pattern 20a of the external connection terminal supporting substrate 20 Are connected by the wire bonding method, and the wiring pattern 30b formed on the other surface of the semiconductor element mounting substrate 30 and the wiring pattern 20b of the external connection terminal supporting substrate 20 are connected by the solder 23.

【0012】本実施形態で半導体素子搭載基板30の配
線パターン30bと外部接続端子支持基板20の配線パ
ターン20aとを電気的に接続するはんだ23は、これ
ら配線パターン30b、20aを相互に電気的に接続す
る作用と共に、半導体素子搭載基板30を外部接続端子
支持基板20に接合して支持する作用を有している。す
なわち、はんだ23によるはんだ接合により、外部接続
端子支持基板20によって半導体素子搭載基板30が支
持され、半導体素子搭載基板30に搭載された半導体素
子6と外部接続端子21との電気的接続がなされる。
In this embodiment, the solder 23 that electrically connects the wiring pattern 30b of the semiconductor element mounting substrate 30 and the wiring pattern 20a of the external connection terminal supporting substrate 20 electrically connects these wiring patterns 30b and 20a to each other. In addition to the function of connecting, the semiconductor element mounting substrate 30 is bonded to and supported by the external connection terminal supporting substrate 20. That is, the semiconductor element mounting substrate 30 is supported by the external connection terminal supporting substrate 20 by soldering with the solder 23, and the semiconductor element 6 mounted on the semiconductor element mounting substrate 30 and the external connection terminal 21 are electrically connected. .

【0013】なお、24は外部接続端子支持基板20の
表面を保護するソルダーレジストである。半導体素子6
はポッティング法により樹脂封止する。樹脂封止にあた
って半導体素子搭載基板30の両面に封止用の樹脂をポ
ッティングし、半導体素子搭載基板30の一方の面側で
は半導体素子搭載基板30の外周縁部を覆うようにする
とともに、半導体素子搭載基板30の他方の面では外部
接続端子支持基板20の透孔22を閉止するように封止
樹脂40によって封止する。なお、半導体素子6の封止
はポッティング法によらずに樹脂モールドによることも
可能である。
Reference numeral 24 is a solder resist for protecting the surface of the external connection terminal supporting substrate 20. Semiconductor element 6
Is sealed with resin by the potting method. At the time of resin encapsulation, a resin for encapsulation is potted on both sides of the semiconductor element mounting substrate 30 so that one side of the semiconductor element mounting substrate 30 covers the outer peripheral edge portion of the semiconductor element mounting substrate 30. The other surface of the mounting board 30 is sealed with a sealing resin 40 so as to close the through hole 22 of the external connection terminal supporting board 20. The semiconductor element 6 may be sealed by resin molding instead of the potting method.

【0014】図2は半導体素子搭載基板30を外部接続
端子支持基板20に接合する他の実施形態を示す。すな
わち、上記実施形態では半導体素子搭載基板30に設け
た配線パターン30aと外部接続端子支持基板20に設
けた配線パターン20aとをワイヤボンディング法によ
り電気的に接続したが、この実施形態では半導体素子搭
載基板30に外部接続端子支持基板20との接合位置に
合わせてスルーホール30cを設け、このスルーホール
30cを介して配線パターン30aと配線パターン20
aとを電気的に接続することを特徴とする。
FIG. 2 shows another embodiment in which the semiconductor element mounting substrate 30 is bonded to the external connection terminal supporting substrate 20. That is, in the above embodiment, the wiring pattern 30a provided on the semiconductor element mounting substrate 30 and the wiring pattern 20a provided on the external connection terminal supporting substrate 20 are electrically connected by the wire bonding method. A through hole 30c is provided in the substrate 30 at a position where the external connection terminal supporting substrate 20 is joined, and the wiring pattern 30a and the wiring pattern 20 are provided through the through hole 30c.
It is characterized in that it is electrically connected to a.

【0015】スルーホール30cは図のように半導体素
子搭載基板30を厚さ方向に貫通し、外部接続端子支持
基板20に接合される半導体素子搭載基板30の周縁部
に配置する。半導体素子搭載基板30の一方の面側のス
ルーホール30cの一端には配線パターン30aが接続
し、半導体素子搭載基板30の他方の面側でスルーホー
ル30cの他端には配線パターン20aに接続される接
続パッドが設けられる。半導体素子搭載基板30の他方
の面に設ける配線パターン30bについてはスルーホー
ル30cに接続することなく、半導体素子搭載基板30
の周縁部に設けた接続パッドに接続する。
The through hole 30c penetrates the semiconductor element mounting substrate 30 in the thickness direction as shown in the figure, and is arranged in the peripheral portion of the semiconductor element mounting substrate 30 joined to the external connection terminal supporting substrate 20. The wiring pattern 30a is connected to one end of the through hole 30c on one surface side of the semiconductor element mounting substrate 30, and the wiring pattern 20a is connected to the other end of the through hole 30c on the other surface side of the semiconductor element mounting substrate 30. Connection pads are provided. The wiring pattern 30b provided on the other surface of the semiconductor element mounting substrate 30 is not connected to the through hole 30c, but the semiconductor element mounting substrate 30
Is connected to the connection pad provided on the peripheral portion of.

【0016】半導体素子搭載基板30と外部接続端子支
持基板20との接続は上記実施形態と同様にはんだ23
によるはんだ接続によってなされる。これにより、スル
ーホール30cを介して半導体装置用基板30の配線パ
ターン30a、30bと外部接続端子支持基板20の配
線パターン20aとが電気的に接続される。この実施形
態の場合は、半導体装置用基板30を外部接続端子支持
基板20に接合する操作により、ワイヤボンディングす
ることなく、同時に半導体素子搭載基板30と外部接続
端子支持基板20の配線パターン30a、30bと配線
パターン20aとが電気的に接続できるという利点があ
る。
The connection between the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 20 is performed by the solder 23 as in the above embodiment.
Made by soldering by. As a result, the wiring patterns 30a and 30b of the semiconductor device substrate 30 and the wiring pattern 20a of the external connection terminal supporting substrate 20 are electrically connected via the through holes 30c. In the case of this embodiment, the wiring patterns 30a and 30b of the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 20 are simultaneously formed by wire bonding by the operation of bonding the semiconductor device substrate 30 to the external connecting terminal supporting substrate 20. And the wiring pattern 20a can be electrically connected.

【0017】図3は半導体素子搭載基板30と外部接続
端子支持基板20とを接合するさらに他の実施形態を示
す。この実施形態では半導体素子搭載基板30の一方の
面側にのみ外部接続端子支持基板20の配線パターン2
0aと電気的に接続する接続パターンを設け、半導体素
子搭載基板30の他方の面側の配線パターン30bをス
ルーホール30cを介して前記接続パターンに電気的に
接続し、この接続パターンと外部接続端子支持基板20
の配線パターン20aとをワイヤボンディングによって
接続した後、半導体素子搭載基板30と外部接続端子支
持基板20とを導電性を有しない接着剤26を用いて接
合する。
FIG. 3 shows still another embodiment in which the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 20 are bonded together. In this embodiment, the wiring pattern 2 of the external connection terminal supporting substrate 20 is provided only on one surface side of the semiconductor element mounting substrate 30.
0a is provided, and the wiring pattern 30b on the other surface side of the semiconductor element mounting substrate 30 is electrically connected to the connection pattern through the through hole 30c, and the connection pattern and the external connection terminal are provided. Support substrate 20
After the wiring pattern 20a is connected to the wiring pattern 20a by wire bonding, the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 20 are bonded using an adhesive 26 having no conductivity.

【0018】本実施形態では半導体素子搭載基板30の
配線パターン30a、30bと外部接続端子支持基板2
0の配線パターン20aとはワイヤボンディングによっ
て接続するから、接着剤26は半導体素子搭載基板30
と外部接続端子支持基板20とを接合する作用のみでよ
い。なお、半導体素子搭載基板30にスルーホール30
cを設けることにより、上記のように半導体素子搭載基
板30の一方の面側にのみ接続パターンを設ける場合と
は逆に、半導体素子搭載基板30の他方の面側にのみ接
続パターンを設けるようにすることもできる。この場合
には、半導体素子搭載基板30と外部接続端子支持基板
20とをはんだ接続することにより半導体素子搭載基板
30の配線パターン30a、30bと外部接続端子支持
基板20の配線パターン20aとを電気的に接続するこ
とができる。
In this embodiment, the wiring patterns 30a and 30b of the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 2 are used.
Since it is connected to the wiring pattern 20a of 0 by wire bonding, the adhesive 26 is applied to the semiconductor element mounting substrate 30.
It is only necessary to join the external connection terminal supporting substrate 20 with the external connection terminal supporting substrate 20. In addition, the through hole 30 is formed in the semiconductor element mounting substrate 30.
By providing c, as opposed to the case where the connection pattern is provided only on one surface side of the semiconductor element mounting substrate 30 as described above, the connection pattern is provided only on the other surface side of the semiconductor element mounting substrate 30. You can also do it. In this case, the wiring patterns 30a and 30b of the semiconductor element mounting substrate 30 and the wiring pattern 20a of the external connection terminal supporting substrate 20 are electrically connected by soldering the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 20. Can be connected to.

【0019】次に、図1に示した半導体装置を例として
半導体装置の製造方法について説明する。図4(a) は外
部接続端子支持基板20として用いる基板フレーム50
を一方の面から見た状態を示す。実施形態の基板フレー
ム50は外部接続端子支持基板20が3つ形成できる短
冊状に形成したものである。上記半導体装置を製造する
にあたってはこの基板フレーム50を単位に搬送操作等
を行って製造する。22は外部接続端子支持基板20に
設けられる透孔であって、基板フレーム50にあらかじ
め孔あけされて形成されている。20aは上述した配線
パターンである。図4(b) は上記基板フレーム50を他
方の面側から見た状態を示す。外部接続端子支持基板2
0の他方の面には外部接続端子21を接合するランド部
20bがアレイ状に配置されて形成されている。
Next, a method of manufacturing a semiconductor device will be described by taking the semiconductor device shown in FIG. 1 as an example. FIG. 4A shows a board frame 50 used as the external connection terminal supporting board 20.
Shows the state viewed from one side. The board frame 50 of the embodiment is formed in a strip shape in which three external connection terminal supporting boards 20 can be formed. When manufacturing the semiconductor device, the substrate frame 50 is used as a unit for carrying operation and the like. Reference numeral 22 denotes a through hole provided in the external connection terminal supporting board 20, which is formed in the board frame 50 in advance. Reference numeral 20a is the wiring pattern described above. FIG. 4B shows the substrate frame 50 as viewed from the other surface side. External connection terminal support board 2
On the other surface of 0, land portions 20b for joining the external connection terminals 21 are arranged and formed in an array.

【0020】図5は外部接続端子支持基板20に接合す
る半導体素子搭載基板30の斜視図である。半導体素子
搭載基板30には半導体素子6と電気的に接続する配線
パターン30aが設けられ、半導体素子6がマルチチッ
プモジュールと同様な形態で搭載されている。なお、配
線パターン30aは半導体素子搭載基板30の周縁部で
ワイヤボンディングするから、半導体素子搭載基板30
の周縁部で一定間隔に配線パターン30aを形成し、そ
の端部をボンディング部32としている。
FIG. 5 is a perspective view of the semiconductor element mounting substrate 30 bonded to the external connection terminal supporting substrate 20. A wiring pattern 30a electrically connected to the semiconductor element 6 is provided on the semiconductor element mounting substrate 30, and the semiconductor element 6 is mounted in a form similar to that of the multichip module. Since the wiring pattern 30a is wire-bonded at the peripheral portion of the semiconductor element mounting substrate 30, the semiconductor element mounting substrate 30
The wiring patterns 30a are formed at regular intervals along the peripheral edge of the, and the ends thereof are used as the bonding portions 32.

【0021】半導体素子搭載基板30にはあらかじめ半
導体素子6を搭載し、半導体素子6と配線パターン30
aとをワイヤボンディングした後、半導体素子搭載基板
30を基板フレーム50に形成された配線パターン20
aと位置合わせして接合する。本実施形態では半導体素
子搭載基板30と基板フレーム50とははんだ接続によ
って接続する。図6に半導体素子搭載基板30を基板フ
レーム50に接合した状態の斜視図を示す。基板フレー
ム50に3枚の半導体素子搭載基板30が接合されてい
る。
The semiconductor element 6 is preliminarily mounted on the semiconductor element mounting substrate 30, and the semiconductor element 6 and the wiring pattern 30 are mounted.
After wire bonding with a, the semiconductor element mounting substrate 30 is formed with the wiring pattern 20 formed on the substrate frame 50.
Align with a and join. In this embodiment, the semiconductor element mounting substrate 30 and the substrate frame 50 are connected by soldering. FIG. 6 shows a perspective view of the semiconductor element mounting substrate 30 bonded to the substrate frame 50. Three semiconductor element mounting substrates 30 are bonded to the substrate frame 50.

【0022】図7は基板フレーム50に半導体素子搭載
基板30をはんだ接合した状態の断面図である。半導体
素子6は半導体素子搭載基板30上で配線パターン30
a、30bに電気的に接続されている。また、半導体素
子搭載基板30の他方の面に形成された配線パターン3
0bと外部接続端子支持基板20の配線パターン20a
とがはんだ23によって電気的に接続されている。
FIG. 7 is a sectional view showing a state in which the semiconductor element mounting substrate 30 is soldered to the substrate frame 50. The semiconductor element 6 has a wiring pattern 30 on the semiconductor element mounting substrate 30.
It is electrically connected to a and 30b. Further, the wiring pattern 3 formed on the other surface of the semiconductor element mounting substrate 30.
0b and the wiring pattern 20a of the external connection terminal supporting substrate 20.
And are electrically connected by solder 23.

【0023】次いで、半導体素子搭載基板30の配線パ
ターン30aと基板フレーム50の配線パターン20a
とをワイヤボンディング法により接続する(図8)。3
6がボンディングワイヤである。基板フレーム50に設
けられる配線パターン20aには半導体素子搭載基板3
0に形成されている配線パターン30aのボンディング
部32の配置に対応してボンディング部が設けられてお
り、半導体素子搭載基板30と外部接続端子支持基板2
0との間のワイヤボンディングはこれらの対応するボン
ディング部間で行う。
Next, the wiring pattern 30a of the semiconductor element mounting substrate 30 and the wiring pattern 20a of the substrate frame 50.
And are connected by a wire bonding method (FIG. 8). 3
6 is a bonding wire. The semiconductor element mounting substrate 3 is formed on the wiring pattern 20a provided on the substrate frame 50.
Bonding portions are provided so as to correspond to the arrangement of the bonding portions 32 of the wiring pattern 30a formed in 0, and the semiconductor element mounting substrate 30 and the external connection terminal supporting substrate 2 are provided.
Wire bonding with 0 is performed between these corresponding bonding portions.

【0024】次いで、半導体素子搭載基板30の一方の
面および他方の面に封止樹脂をポッティングし、半導体
素子6を樹脂封止する(図9)。次に、ランド部20b
に外部接続端子21であるはんだボールを接合し、基板
フレーム50から各々外部接続端子支持基板20を個片
に切り離しする(図10)。こうして、外部接続端子支
持基板20で半導体素子搭載基板30を支持して樹脂封
止した半導体装置が得られる。
Then, a sealing resin is potted on one surface and the other surface of the semiconductor element mounting substrate 30 to seal the semiconductor element 6 with the resin (FIG. 9). Next, the land portion 20b
Solder balls, which are the external connection terminals 21, are joined to each other, and the external connection terminal supporting board 20 is cut into individual pieces from the board frame 50 (FIG. 10). Thus, a semiconductor device in which the semiconductor element mounting substrate 30 is supported by the external connection terminal supporting substrate 20 and resin-sealed is obtained.

【0025】上記各実施形態において説明した外部接続
端子支持基板20に半導体素子搭載基板30を接合して
構成した半導体装置は、複数の半導体素子6をあらかじ
め搭載した半導体素子搭載基板30によって形成するか
ら従来のマルチチップモジュールとまったく同様の機能
を有する製品として得ることができる。外部接続端子支
持基板20と半導体素子搭載基板30には樹脂基板を使
用するから、基板は安価に製造でき、その組み立ても容
易である。また、樹脂基板は配線パターン等の導体部分
には銅等の電気的特性の優れた素材が使用できるから、
半導体装置全体として電気的特性に優れ、きわめて高速
な半導体素子を搭載できる特性の優れた半導体装置とし
て提供することができるという利点がある。
Since the semiconductor device mounting substrate 30 bonded to the external connection terminal supporting substrate 20 described in each of the above embodiments is formed by the semiconductor element mounting substrate 30 on which a plurality of semiconductor elements 6 are mounted in advance. It can be obtained as a product having exactly the same function as a conventional multi-chip module. Since resin substrates are used for the external connection terminal support substrate 20 and the semiconductor element mounting substrate 30, the substrates can be manufactured at low cost and their assembly is easy. In addition, since the resin substrate can use materials with excellent electrical characteristics such as copper for the conductor parts such as wiring patterns,
There is an advantage in that the semiconductor device as a whole can be provided as a semiconductor device having excellent electrical characteristics and excellent characteristics in which an extremely high-speed semiconductor element can be mounted.

【0026】また、上記実施形態のように外部接続端子
支持基板20に透孔22を設けて半導体素子搭載基板3
0を支持するようにすると、半導体素子搭載基板30の
両面が半導体素子6の搭載面として使用でき、複数の半
導体素子6を搭載することが容易であり、多様な搭載が
可能になるという利点もある。
Further, as in the above-described embodiment, the through hole 22 is provided in the external connection terminal supporting substrate 20 to form the semiconductor element mounting substrate 3
If 0 is supported, both sides of the semiconductor element mounting substrate 30 can be used as mounting surfaces for the semiconductor elements 6, and a plurality of semiconductor elements 6 can be easily mounted, and various mountings are possible. is there.

【0027】また、外部接続端子支持基板20での外部
接続端子21の配置は搭載する半導体素子6が異なって
も共通に設定されている場合が多く、半導体素子搭載基
板30と外部接続端子支持基板20との電気的接続部分
を共通にしておくことによって、異なる半導体素子6を
搭載した半導体素子搭載基板30を使用する場合でも外
部接続端子支持基板20、基板フレーム50が共通に使
用することが可能になり、この点から製造コストを下げ
ることができるという利点がある。
The arrangement of the external connection terminals 21 on the external connection terminal supporting board 20 is often set in common even if the semiconductor elements 6 mounted are different, and the semiconductor element mounting board 30 and the external connection terminal supporting board are arranged. By making the electrical connection portion with 20 common, it is possible to commonly use the external connection terminal support substrate 20 and the substrate frame 50 even when using the semiconductor element mounting substrate 30 on which different semiconductor elements 6 are mounted. From this point, there is an advantage that the manufacturing cost can be reduced.

【0028】[0028]

【発明の効果】本発明に係る半導体装置は、上述したよ
うに、樹脂基板を用いた半導体装置として低コストで生
産できるマルチチップモジュールとして提供でき、量産
に好適な半導体装置として提供することができる。ま
た、高速化に十分対応できる特性的に優れた半導体装置
として提供することができる等の著効を奏する。
As described above, the semiconductor device according to the present invention can be provided as a multi-chip module which can be produced at low cost as a semiconductor device using a resin substrate, and can be provided as a semiconductor device suitable for mass production. . In addition, a remarkable effect such as being able to be provided as a semiconductor device having excellent characteristics that can sufficiently cope with high speed is exhibited.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体装置の一実施形態を示す断
面図である。
FIG. 1 is a sectional view showing one embodiment of a semiconductor device according to the present invention.

【図2】半導体装置の他の実施形態を示す断面図であ
る。
FIG. 2 is a cross-sectional view showing another embodiment of a semiconductor device.

【図3】半導体装置のさらに他の実施形態を示す断面図
である。
FIG. 3 is a sectional view showing still another embodiment of a semiconductor device.

【図4】半導体装置の製造に使用する基板フレームの斜
視図である。
FIG. 4 is a perspective view of a substrate frame used for manufacturing a semiconductor device.

【図5】半導体素子搭載基板の斜視図である。FIG. 5 is a perspective view of a semiconductor element mounting substrate.

【図6】基板フレームに半導体素子搭載基板を接続した
状態の斜視図である。
FIG. 6 is a perspective view showing a state where a semiconductor element mounting substrate is connected to a substrate frame.

【図7】基板フレームに半導体素子搭載基板を接続した
状態の断面図である。
FIG. 7 is a cross-sectional view showing a state in which a semiconductor element mounting substrate is connected to a substrate frame.

【図8】半導体素子搭載基板と外部接続端子支持基板と
を配線パターン間でワイヤボンディングした状態の断面
図である。
FIG. 8 is a cross-sectional view showing a state in which a semiconductor element mounting substrate and an external connection terminal supporting substrate are wire-bonded between wiring patterns.

【図9】半導体素子を樹脂封止した状態の断面図であ
る。
FIG. 9 is a cross-sectional view of a semiconductor element sealed with a resin.

【図10】はんだボールを接合し、半導体装置の個片に
した状態の断面図である。
FIG. 10 is a cross-sectional view showing a state in which solder balls are joined together to form individual pieces of a semiconductor device.

【図11】マルチチップモジュールの従来例の構成を示
す断面図である。
FIG. 11 is a cross-sectional view showing a configuration of a conventional example of a multi-chip module.

【図12】樹脂基板に半導体素子を搭載した半導体装置
の従来例の構成を示す断面図である。
FIG. 12 is a sectional view showing a configuration of a conventional example of a semiconductor device in which a semiconductor element is mounted on a resin substrate.

【符号の説明】[Explanation of symbols]

6 半導体チップ 10 樹脂基板 20 外部接続端子支持基板 20a 配線パターン 20b ランド部 20c スルーホール 21 外部接続端子 22 透孔 23 はんだ 24 ソルダーレジスト 26 接着剤 30 半導体素子搭載基板 30a、30b 配線パターン 30c スルーホール 32 ボンディング部 36 ボンディングワイヤ 40 封止樹脂 50 基板フレーム 6 Semiconductor Chip 10 Resin Substrate 20 External Connection Terminal Support Substrate 20a Wiring Pattern 20b Land 20c Through Hole 21 External Connection Terminal 22 Through Hole 23 Solder 24 Solder Resist 26 Adhesive 30 Semiconductor Element Mounting Substrate 30a, 30b Wiring Pattern 30c Through Hole 32 Bonding part 36 Bonding wire 40 Sealing resin 50 Substrate frame

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 樹脂基板からなる半導体素子搭載基板の
一方の面に形成された配線パターンと電気的に接続され
て複数個の半導体素子が搭載され、 前記半導体素子搭載基板の他方の面の周縁部が樹脂基板
からなる外部接続端子支持基板に透設された透孔の周縁
部に接合されるとともに、該外部接続端子支持基板の接
合面側に形成された配線パターンと前記半導体素子搭載
基板に形成された配線パターンとが、及び、該外部接続
端子支持基板の接合面側に形成された配線パターンと前
記外部接続端子支持基板の他面側に設けられた外部接続
端子とが電気的に接続され、 前記半導体素子が樹脂封止されたことを特徴とする半導
体装置。
1. A plurality of semiconductor elements are mounted by being electrically connected to a wiring pattern formed on one surface of a semiconductor element mounting substrate made of a resin substrate, and a peripheral edge of the other surface of the semiconductor element mounting substrate. Part is joined to the peripheral portion of the through hole provided in the external connection terminal supporting substrate made of a resin substrate, and the wiring pattern formed on the joint surface side of the external connecting terminal supporting substrate and the semiconductor element mounting substrate. The formed wiring pattern is electrically connected, and the wiring pattern formed on the joint surface side of the external connection terminal support substrate and the external connection terminal provided on the other surface side of the external connection terminal support substrate are electrically connected. And the semiconductor element is resin-sealed.
【請求項2】 半導体素子搭載基板の他方の面に配線パ
ターンが形成され、該配線パターンと電気的に接続され
て半導体素子が搭載され、該配線パターンと半導体素子
搭載基板の一方の面に形成された配線パターンまたは外
部接続端子支持基板の接合面側に形成された配線パター
ンとが電気的に接続されたことを特徴とする請求項1記
載の半導体装置。
2. A wiring pattern is formed on the other surface of the semiconductor element mounting substrate, a semiconductor element is mounted by being electrically connected to the wiring pattern, and the wiring pattern is formed on one surface of the semiconductor element mounting substrate. 2. The semiconductor device according to claim 1, wherein the formed wiring pattern or a wiring pattern formed on the bonding surface side of the external connection terminal supporting substrate is electrically connected.
【請求項3】 半導体素子搭載基板の一方の面に形成さ
れた配線パターンと外部接続端子支持基板の接合面側に
形成された配線パターンとがボンディングワイヤまたは
半導体素子搭載基板に形成されたスルーホールにより電
気的に接続されたことを特徴とする請求項1または2記
載の半導体装置。
3. A wiring pattern formed on one surface of a semiconductor element mounting substrate and a wiring pattern formed on a bonding surface side of an external connection terminal supporting substrate are bonding wires or through holes formed on the semiconductor element mounting substrate. 3. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected by.
【請求項4】 半導体素子搭載基板の他方の面に形成さ
れた配線パターンと外部接続端子支持基板の接合面側に
形成された配線パターンとがはんだにより電気的に接続
されたことを特徴とする請求項1または2記載の半導体
装置。
4. The wiring pattern formed on the other surface of the semiconductor element mounting substrate and the wiring pattern formed on the bonding surface side of the external connection terminal supporting substrate are electrically connected by soldering. The semiconductor device according to claim 1.
【請求項5】 半導体素子搭載基板の周縁部と外部接続
端子支持基板に透設された透孔の周縁部とが接着剤によ
り接合されていることを特徴とする請求項1または2記
載の半導体装置。
5. The semiconductor device according to claim 1, wherein the peripheral edge portion of the semiconductor element mounting substrate and the peripheral edge portion of the through hole provided through the external connection terminal supporting substrate are bonded with an adhesive. apparatus.
【請求項6】 外部接続端子がはんだボールであること
を特徴とする請求項1、2、3、4または5記載の半導
体装置。
6. The semiconductor device according to claim 1, wherein the external connection terminal is a solder ball.
【請求項7】 半導体素子がポッティング法により樹脂
封止されたことを特徴とする請求項1、2、3、4、5
または6記載の半導体装置。
7. The semiconductor element is resin-sealed by a potting method, according to claim 1, 2, 3, 4, 5.
Alternatively, the semiconductor device according to item 6.
JP33662895A 1995-12-25 1995-12-25 Semiconductor device Expired - Fee Related JP3466354B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33662895A JP3466354B2 (en) 1995-12-25 1995-12-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33662895A JP3466354B2 (en) 1995-12-25 1995-12-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH09181256A true JPH09181256A (en) 1997-07-11
JP3466354B2 JP3466354B2 (en) 2003-11-10

Family

ID=18301128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33662895A Expired - Fee Related JP3466354B2 (en) 1995-12-25 1995-12-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3466354B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166443A (en) * 1998-04-30 2000-12-26 Nec Corporation Semiconductor device with reduced thickness
US6673651B2 (en) 1999-07-01 2004-01-06 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US6734553B2 (en) 2001-05-25 2004-05-11 Nec Electronics Corporation Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166443A (en) * 1998-04-30 2000-12-26 Nec Corporation Semiconductor device with reduced thickness
US6673651B2 (en) 1999-07-01 2004-01-06 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US7427810B2 (en) 1999-07-01 2008-09-23 Oki Electric Industry Co., Ltd. Semiconductor device including semiconductor element mounted on another semiconductor element
US7592690B2 (en) 1999-07-01 2009-09-22 Oki Semiconductor Co., Ltd. Semiconductor device including semiconductor elements mounted on base plate
US7723832B2 (en) 1999-07-01 2010-05-25 Oki Semiconductor Co., Ltd. Semiconductor device including semiconductor elements mounted on base plate
US8008129B2 (en) 1999-07-01 2011-08-30 Oki Semiconductor Co., Ltd. Method of making semiconductor device packaged by sealing resin member
US8486728B2 (en) 1999-07-01 2013-07-16 Oki Semiconductor Co., Ltd. Semiconductor device including semiconductor elements mounted on base plate
US6734553B2 (en) 2001-05-25 2004-05-11 Nec Electronics Corporation Semiconductor device
US6984889B2 (en) 2001-05-25 2006-01-10 Nec Electronics Corporation Semiconductor device

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