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JPH0730059A - Multichip module - Google Patents

Multichip module

Info

Publication number
JPH0730059A
JPH0730059A JP15326393A JP15326393A JPH0730059A JP H0730059 A JPH0730059 A JP H0730059A JP 15326393 A JP15326393 A JP 15326393A JP 15326393 A JP15326393 A JP 15326393A JP H0730059 A JPH0730059 A JP H0730059A
Authority
JP
Japan
Prior art keywords
semiconductor element
recess
semiconductor
chip module
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15326393A
Other languages
Japanese (ja)
Inventor
Ryoichi Nagaoka
亮一 長岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15326393A priority Critical patent/JPH0730059A/en
Publication of JPH0730059A publication Critical patent/JPH0730059A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To enable a multichip module mounted with a plurality of semiconductor elements to be enhanced in element mounting density and lessened in size. CONSTITUTION:Semiconductor element, connecting electrodes 4 and 5 are provided to the base of a recess 3 bored in a multilayer board 1 and the upside of the multilayer board 1 respectively, a semiconductor element 6 is housed in the recess 3, and a semiconductor element 8 is mounted on the board 1 bestriding the recess 3 so as to enhance semiconductor elements mounted on the multilayer board 1 in density. By this setup, a multichip module of this constitution can be enhanced to be two to three times as high in degree of integration as or lessened to be 1/2 to 1/3 as large in size as a conventional one.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子及びその他
の電子素子を多数表面実装し、所定の電気配線で接続し
て形成されるマルチチップモジュールの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a multi-chip module formed by mounting a large number of semiconductor elements and other electronic elements on the surface and connecting them by predetermined electric wiring.

【0002】[0002]

【従来の技術】従来のマルチチップモジュールは図5に
示すように電気配線基板の1平面上に半導体素子を実装
している構造が1般的である。多層基板は半導体素子間
及び外部入出力端子間を接続する電気配線を有し基板の
1平面上に半導体素子を実装し、対抗する面は外部入出
力端子を設けるかまたは放熱用のフィンで構成される。
多層基板の必要な大きさは実装される半導体素子の数と
大きさで決定される(例えば、特開平3−93259号
公報参照)。
2. Description of the Related Art A conventional multi-chip module generally has a structure in which semiconductor elements are mounted on one plane of an electric wiring board as shown in FIG. The multi-layer board has electrical wiring for connecting the semiconductor elements and the external input / output terminals, and the semiconductor elements are mounted on one plane of the board. To be done.
The required size of the multilayer substrate is determined by the number and size of semiconductor elements to be mounted (see, for example, Japanese Patent Laid-Open No. 3-93259).

【0003】[0003]

【発明が解決しようとする課題】この従来のマルチチッ
プモジュール構造では、基板の1平面で構成する半導体
素子の大きさと個数で基板寸法が決定されるため、高集
積化・小型化の要求に答えることが難しいという問題点
があった。
In this conventional multi-chip module structure, the size of the substrate is determined by the size and number of semiconductor elements formed on one plane of the substrate, so that the demand for high integration and miniaturization is met. There was a problem that it was difficult.

【0004】本発明は、このような従来の技術が有する
問題点に着目してなされたもので、半導体素子実装密度
の向上及びモジュールの小型化ができるようにしたマル
チチップモジュールを提供することを目的としている。
The present invention has been made in view of the above problems of the conventional technique, and it is an object of the present invention to provide a multi-chip module capable of improving the packaging density of semiconductor elements and miniaturizing the module. Has an aim.

【0005】[0005]

【課題を解決するための手段】かかる目的を達成するた
めの本発明の要旨とするところは、以下の2項に存す
る。
The gist of the present invention for achieving the above object lies in the following two items.

【0006】[1] 半導体素子を含む複数の電子素子
を表面に実装し、該電子素子に接続される電気配線が形
成されているマルチチップモジュールにおいて、半導体
素子(6、8)及び多層基板から成り、多層基板(1)
には、半導体素子(6、8)を嵌合するための凹部
(1)が複数個配設され、半導体素子接続用電極(4、
5)がパタ−ンニングされ、外部と入出力信号の受け渡
しをするための外部入出力端子(2)が複数個配設さ
れ、電気配線が半導体素子(6、8)間及び外部入出力
端子(2)間並びに半導体素子(6、8)と前記外部入
出力端子(2)との間を接続され、半導体素子(6、
8)は、凹部(3)の底部に嵌装されるか、または凹部
(3)を股いで載設されていることを特徴とするマルチ
チップモジュール。
[1] In a multi-chip module in which a plurality of electronic elements including semiconductor elements are mounted on the surface and electric wirings connected to the electronic elements are formed, a semiconductor element (6, 8) and a multi-layer substrate are used. Nari, multilayer board (1)
Is provided with a plurality of recesses (1) for fitting the semiconductor elements (6, 8), and semiconductor element connecting electrodes (4,
5) is patterned, a plurality of external input / output terminals (2) for transferring input / output signals to / from the outside are provided, and electric wiring is provided between the semiconductor elements (6, 8) and the external input / output terminals (6). 2) and between the semiconductor element (6, 8) and the external input / output terminal (2), and the semiconductor element (6,
8) is a multi-chip module characterized by being fitted to the bottom of the recess (3) or mounted on the recess (3) with a crotch.

【0007】[2] 凹部(3)を樹脂で封止したこと
を特徴とする上記[1]に記載のマルチチップモジュー
ル。
[2] The multichip module according to the above [1], wherein the recess (3) is sealed with a resin.

【0008】[0008]

【実施例】本発明を図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

【0009】図1は、本発明の1実施例のマルチチップ
モジュールの縦断面図である。
FIG. 1 is a vertical sectional view of a multi-chip module according to an embodiment of the present invention.

【0010】半導体素子6、8及びその他の電子素子を
多数表面実装し、所定の電気配線で接続して形成される
マルチチップモジュールにおいて、半導体素子6、8及
び多層基板1から成る。
A multi-chip module formed by mounting a large number of semiconductor elements 6 and 8 and other electronic elements on the surface and connecting them by predetermined electric wiring is composed of the semiconductor elements 6 and 8 and the multilayer substrate 1.

【0011】多層基板は、その底部と上部とに半導体素
子接続用電極4、5がパタ−ンニングされ、半導体素子
6、8を嵌合するための凹部3が複数個配設される。外
部と入出力信号の受け渡しをするための外部入出力端子
2が複数個配設される。半導体素子6、8間、外部入出
力端子2間及び半導体素子6、8・外部入出力端子間の
電気配線がその底部と上部と内部に繞設される。
The multi-layer substrate has semiconductor element connecting electrodes 4 and 5 patterned on the bottom and top thereof, and a plurality of recesses 3 for fitting the semiconductor elements 6 and 8 therein. A plurality of external input / output terminals 2 are provided for exchanging input / output signals with the outside. Electrical wiring is provided between the semiconductor elements 6 and 8, between the external input / output terminals 2, and between the semiconductor elements 6 and 8 and the external input / output terminals at the bottom, the top and the inside.

【0012】半導体素子6、8は、多層基板1の凹部3
の底部と凹部上部円周を用いて嵌装・載設される。
The semiconductor elements 6 and 8 are the recesses 3 of the multilayer substrate 1.
It is fitted and mounted using the bottom part and the circumference of the upper part of the recess.

【0013】凹部3の底部には半導体素子接続用の電極
4を形成している。また凹部3の上部に当たる部分にも
半導体素子接続用電極5を設けている。
An electrode 4 for connecting a semiconductor element is formed on the bottom of the recess 3. Further, the semiconductor element connecting electrode 5 is also provided in a portion corresponding to the upper portion of the recess 3.

【0014】まず凹部3に半導体素子6を実装し、半導
体素子6の回路と凹部底部に設けた接続用電極4を接続
する。図1では半導体素子6の回路面を上にし金または
アルミ細線7によるワイヤ−ボンディング法により接続
されている。凹部3内の半導体素子6を実装後、凹部を
跨ぐ様に半導体素子8を実装する。凹部を跨ぐ半導体素
子8は接続用端子9が施されたプラスチックパッケ−ジ
やセラミックパッケ−ジに収容された構造、またはキャ
リアテ−プ(図3の11)に半導体素子を実装した構造
の半導体素子を使用する。
First, the semiconductor element 6 is mounted in the recess 3, and the circuit of the semiconductor element 6 is connected to the connection electrode 4 provided at the bottom of the recess. In FIG. 1, the semiconductor element 6 is connected with the circuit side facing upward by a wire bonding method using a gold or aluminum thin wire 7. After mounting the semiconductor element 6 in the recess 3, the semiconductor element 8 is mounted so as to straddle the recess. The semiconductor element 8 straddling the recess is housed in a plastic package or a ceramic package provided with connection terminals 9, or a semiconductor tape having a semiconductor element mounted on a carrier tape (11 in FIG. 3). Use the element.

【0015】多層基板との接続は、凹部上部に設けられ
た接続用電極5とで行われ半田付けなどの工法を用い
る。
The connection with the multi-layer substrate is carried out with the connecting electrode 5 provided on the upper part of the recess, and a method such as soldering is used.

【0016】図2は、第2の実施例を示す。FIG. 2 shows a second embodiment.

【0017】特許請求の範囲第1項記載のマルチチップ
モジュールにおいて、凹部3を樹脂で封止している。
In the multichip module according to the first aspect of the invention, the recess 3 is sealed with resin.

【0018】第1の実施例の凹部3に裸の半導体素子6
を使用し、半導体素子6の信頼性を確保するために樹脂
10にて凹部を封止している。
A bare semiconductor element 6 is formed in the recess 3 of the first embodiment.
Is used, and the recess is sealed with the resin 10 in order to ensure the reliability of the semiconductor element 6.

【0019】図3は本発明の第3の実施例である。FIG. 3 shows a third embodiment of the present invention.

【0020】凹部3の底部に半導体素子6を実装した
後、キャリアテ−プ11に実装した半導体素子6の端子
のみを、凹部上部の接続用電極52と接続する。
After the semiconductor element 6 is mounted on the bottom of the recess 3, only the terminals of the semiconductor element 6 mounted on the carrier tape 11 are connected to the connection electrodes 52 on the upper part of the recess.

【0021】更に、半導体素子6を凹部3に落とし込
み、上部電極52の周囲に設けた半導体素子接続用電極
52を、半導体素子8を実装する。
Further, the semiconductor element 6 is dropped into the recess 3 and the semiconductor element connecting electrode 52 provided around the upper electrode 52 is mounted on the semiconductor element 8.

【0022】図4は、凹部3に階段状の段差12を設け
た第4の実施例である。
FIG. 4 shows a fourth embodiment in which the recess 3 is provided with a step-like step 12.

【0023】半導体素子6と多層基板の接続用電極との
接続距離を短くした構造を特徴とする。
The structure is characterized in that the connecting distance between the semiconductor element 6 and the connecting electrode of the multilayer substrate is shortened.

【0024】[0024]

【発明の効果】以上説明したように、本発明のマルチチ
ップモジュール構造では、半導体素子を高さ方向に重ね
実装できるため、従来のマルチチップモジュールに比較
し2倍〜3倍の高集積化(高密度化)、または1/2〜
1/3の小型化が実現できる。更に凹部を樹脂で封止し
たことにより、半導体素子6及びモジュールの信頼性を
確保できる。
As described above, in the multi-chip module structure of the present invention, since the semiconductor elements can be stacked and mounted in the height direction, the integration can be increased by 2 to 3 times as compared with the conventional multi-chip module ( Higher density), or 1/2 ~
1/3 reduction in size can be realized. Further, by sealing the recess with resin, the reliability of the semiconductor element 6 and the module can be secured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の縦断面図である。FIG. 1 is a vertical cross-sectional view of a first embodiment of the present invention.

【図2】本発明の第2の実施例の部分縦断面図である。FIG. 2 is a partial vertical cross-sectional view of a second embodiment of the present invention.

【図3】本発明の第3の実施例の部分縦断面図である。FIG. 3 is a partial vertical sectional view of a third embodiment of the present invention.

【図4】本発明の第4の実施例の部分縦断面図。FIG. 4 is a partial vertical sectional view of a fourth embodiment of the present invention.

【図5】従来のマルチチップモジュールの縦断面図。FIG. 5 is a vertical sectional view of a conventional multi-chip module.

【符号の説明】[Explanation of symbols]

1 多層基板 2 外部入出力端子 3 凹部 4 半導体素子接続用電極 5 半導体素子接続用電極 6 半導体素子 7 細線 8 半導体素子 9 接続端子 10 樹脂 11 キャリアテ−プの端子部 12 階段状段差部 13 キャップ 14 多層基板 51 半導体素子接続用電極 52 半導体素子接続用電極 DESCRIPTION OF SYMBOLS 1 Multilayer substrate 2 External input / output terminal 3 Recess 4 Electrode for connecting semiconductor element 5 Electrode for connecting semiconductor element 6 Semiconductor element 7 Fine wire 8 Semiconductor element 9 Connection terminal 10 Resin 11 Terminal portion of carrier tape 12 Stepped step portion 13 Cap 14 Multilayer Substrate 51 Semiconductor Element Connecting Electrode 52 Semiconductor Element Connecting Electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を含む複数の電子素子を表面
に実装し、該電子素子に接続される電気配線が形成され
ているマルチチップモジュールにおいて、 半導体素子及び多層基板から成り、 前記多層基板には、前記半導体素子を嵌合するための凹
部が複数個配設され、半導体素子接続用電極がパタ−ン
ニングされ、外部と入出力信号の受け渡しをするための
外部入出力端子が複数個配設され、前記電気配線が前記
半導体素子間及び前記外部入出力端子間並びに前記半導
体素子と前記外部入出力端子との間を接続し、 前記半導体素子は、前記凹部の底部に嵌装されるか、ま
たは前記凹部を股いで載設されていることを特徴とする
マルチチップモジュール。
1. A multi-chip module in which a plurality of electronic elements including a semiconductor element are mounted on a surface and electric wirings connected to the electronic elements are formed. The multi-chip module comprises a semiconductor element and a multi-layer substrate. Is provided with a plurality of recesses for fitting the semiconductor elements, patterned electrodes for connecting the semiconductor elements, and a plurality of external input / output terminals for exchanging input / output signals with the outside. The electrical wiring connects between the semiconductor elements and between the external input / output terminals and between the semiconductor element and the external input / output terminals, and the semiconductor element is fitted to the bottom of the recess, Alternatively, the multi-chip module is characterized in that the recess is mounted in a crotch shape.
【請求項2】 前記凹部を樹脂で封止したことを特徴と
する特許請求の範囲第1項記載のマルチチップモジュー
ル。
2. The multi-chip module according to claim 1, wherein the recess is sealed with resin.
JP15326393A 1993-06-24 1993-06-24 Multichip module Pending JPH0730059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15326393A JPH0730059A (en) 1993-06-24 1993-06-24 Multichip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15326393A JPH0730059A (en) 1993-06-24 1993-06-24 Multichip module

Publications (1)

Publication Number Publication Date
JPH0730059A true JPH0730059A (en) 1995-01-31

Family

ID=15558638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15326393A Pending JPH0730059A (en) 1993-06-24 1993-06-24 Multichip module

Country Status (1)

Country Link
JP (1) JPH0730059A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801438A (en) * 1995-06-16 1998-09-01 Nec Corporation Semiconductor device mounting and multi-chip module
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
US5831833A (en) * 1995-07-17 1998-11-03 Nec Corporation Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
GB2339337A (en) * 1995-06-16 2000-01-19 Nec Corp Semiconductor device mounting in recesses in a circuit board
US6043987A (en) * 1997-08-25 2000-03-28 Compaq Computer Corporation Printed circuit board having a well structure accommodating one or more capacitor components
US6154371A (en) * 1998-09-30 2000-11-28 Cisco Technology, Inc. Printed circuit board assembly and method
GB2370421A (en) * 2000-12-22 2002-06-26 Ubinetics Printed circuit board with recessed component
JP2002232145A (en) * 2001-01-30 2002-08-16 Densei Lambda Kk Multilayer printed board
KR100399724B1 (en) * 2000-12-29 2003-09-29 앰코 테크놀로지 코리아 주식회사 Semiconductor package
KR100600176B1 (en) * 2000-09-19 2006-07-12 앰코 테크놀로지 코리아 주식회사 Semiconductor package
DE102007020475A1 (en) * 2007-04-27 2008-11-06 Häusermann GmbH Method for producing a printed circuit board with a cavity for the integration of components and printed circuit board and application

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* Cited by examiner, † Cited by third party
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JPS5944852A (en) * 1982-09-07 1984-03-13 Seiko Epson Corp Mounting method of multi-layer chip
JPH03280496A (en) * 1990-03-28 1991-12-11 Taiyo Yuden Co Ltd Electronic copmponent mounting structure and method of packaging
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GB2302451B (en) * 1995-06-16 2000-01-26 Nec Corp Semiconductor device mounting method and multi-chip module produced by the same
US5801438A (en) * 1995-06-16 1998-09-01 Nec Corporation Semiconductor device mounting and multi-chip module
GB2339337B (en) * 1995-06-16 2000-03-01 Nec Corp Semiconductor device mounting method and multi-chip module produced by the same
GB2339337A (en) * 1995-06-16 2000-01-19 Nec Corp Semiconductor device mounting in recesses in a circuit board
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US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
US6043987A (en) * 1997-08-25 2000-03-28 Compaq Computer Corporation Printed circuit board having a well structure accommodating one or more capacitor components
US6154371A (en) * 1998-09-30 2000-11-28 Cisco Technology, Inc. Printed circuit board assembly and method
KR100600176B1 (en) * 2000-09-19 2006-07-12 앰코 테크놀로지 코리아 주식회사 Semiconductor package
GB2370421A (en) * 2000-12-22 2002-06-26 Ubinetics Printed circuit board with recessed component
KR100399724B1 (en) * 2000-12-29 2003-09-29 앰코 테크놀로지 코리아 주식회사 Semiconductor package
JP2002232145A (en) * 2001-01-30 2002-08-16 Densei Lambda Kk Multilayer printed board
DE102007020475A1 (en) * 2007-04-27 2008-11-06 Häusermann GmbH Method for producing a printed circuit board with a cavity for the integration of components and printed circuit board and application

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