JPH0917981A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost by scaling down the chip size of a flash memory, etc. SOLUTION: In a semiconductor storage device such as a NOR-type flash memory, etc., fundamentally composed of constituents of memory arrays MARY in each of which two-layer gate structure type of nonvolatile memory cells are arranged in substantially lattice form, when one hand of a row selection signal lines BLLO and BLRO in a pair or the like arranged between two memory blocks BBLOO and MBROO in a pair or the like is used as a bit line, the other hand is used selectively as a source line. Hereby, the row selection signal lines BLLO and BLRO or the like are doubled as a bit line and a source line, whereby the required selection signal lines of a memory array are reduced sharply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a Noah type flash memory and a technique particularly effective for use in reducing the chip size thereof.

[0002]

2. Description of the Related Art There is a flash memory which has as its basic constituent element a memory array in which two-layer gate structure type non-volatile memory cells are arranged in a grid. In addition, the memory cell is divided into memory blocks with a predetermined number of memory cells arranged in the same column as a unit, and the drains and sources of the predetermined number of memory cells forming each memory block are commonly coupled to a sub-bit line and a sub-source line, respectively. Noah
Type flash memory. The NOR type flash memory includes word lines, bit lines and source lines which are arranged orthogonally to each other, and further selectively connects a bit line or a source line and a sub bit line or a sub source line of a designated memory block. Select MOSFET for coupling (metal oxide semiconductor field effect transistor. In this specification, M
OSFET is referred to as a generic name of an insulated gate field effect transistor).

[0003]

In recent years, flash memories have become significantly large-scale and large-capacity, and accompanying this, an increase in chip size is becoming a problem. In particular, in the conventional flash memory that requires the word line, the bit line, and the source line for each row or column, the tendency becomes remarkable, which restricts the cost reduction of the flash memory.

An object of the present invention is to reduce the chip size of a semiconductor memory device such as a flash memory and reduce its cost.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a semiconductor memory device such as a NOR flash memory having a memory array in which non-volatile memory cells of a two-layer gate structure type are arranged in a substantially lattice pattern as a basic constituent element, a two-layer gate structure type nonvolatile memory cell is arranged between two memory blocks forming a pair. The paired column selection signal lines or the two column selection signal lines arranged on both sides of each memory block are selectively used as bit lines or source lines.

[0007]

According to the above means, the column selection signal line is also used as the bit line and the source line, and the required selection signal line of the memory array can be significantly reduced. Therefore, the chip size of the NOR flash memory or the like can be reduced, Cost reduction can be achieved.

[0008]

1 is a block diagram showing an embodiment of a flash memory to which the present invention is applied. Also,
FIG. 2 shows a block diagram of a first embodiment of the memory array MARY included in the flash memory of FIG. 1, and FIG. 3 shows a partial circuit diagram of the first embodiment. Further, FIG. 4 shows a selection condition diagram of one embodiment of the memory array MARY of FIG. 2, and FIGS. 5 and 6 show connection diagrams at the time of reading the left memory block and at the time of reading the right memory block, respectively. It is shown.
Based on these figures, the configuration and operation of the flash memory of this embodiment and its features will be described. The circuit elements forming each block in FIG.
It is formed on one semiconductor substrate such as single crystal silicon by a manufacturing technique of a MOS (complementary MOS) integrated circuit. 3 to 6, the memory block MBL00
, And MBR00 will be described as an example, but since the other memory blocks have the same configuration as this, it should be analogized.

In FIG. 1, the flash memory of this embodiment has a memory array MARY, which occupies most of the surface of a semiconductor substrate, as its basic constituent element. The memory array MARY is 2 × (m + 1) as shown in FIG.
× (n + 1) memory blocks MBL00 to MBL0
n to MBLm0 to MBLmn and MBR00 to
MBR0n to MBRm0 to MBRmn are provided. In these memory blocks, two memory blocks MBL0 that are adjacent to each other in the row direction form a pair and form a pair.
0 and MBR00, etc., a pair of column selection signal lines, that is, bit lines BLL0 and BLR0 to BLLn and B.
LRn are arranged respectively. In this embodiment,
The column selection signal line that is also used as the bit line and the source line is called a bit line, but it may be called a source line.

Here, the memory blocks MBL00 to MBL0n to MBLm forming the memory array MARY.
0 to MBLmn and MBR00 to MBR0n to MBRm0 to MBRmn are memory blocks MB in FIG.
As represented by L00 and MBR00, each includes p + 1 two-layer gate structure type memory cells MC arranged in the same column. These memory cells MC are connected in parallel to form a so-called NOR type memory array. Hereinafter, a detailed description of the memory blocks will be given by taking these memory blocks MBL00 and MBR00 as an example.

Memory blocks MBL00 and MBR00
The control gates of the memory cells MC constituting the memory cell MC are commonly coupled to the corresponding word lines WL00 to WL0p, and the drains and sources thereof are the corresponding sub bit lines SBLL and SBL.
BLR or sub-source lines SSLL and SSLR are commonly coupled. Of these, the sub bit line SBL
L and SBLR are commonly coupled to the corresponding bit line BLL0 or BLR0 via the corresponding switch means or N-channel MOSFET N1 or N2. In addition, the sub-source line SSLL of the memory block MBL00 has a corresponding switching means, that is, an N-channel MOSFET N.
3, the sub-source line SSLR of the memory block MBR00 is commonly coupled to the right bit line BLR0 via the corresponding switch means, that is, the N-channel MOSFET N.
4 are commonly coupled to the left bit line BLL0 through the line 4.
The gates of the MOSFETs N1 and N2 are commonly coupled to the corresponding block selection line BSA0, and the gates of the MOSFETs N3 and N4 are commonly coupled to the corresponding block selection line BSB0 or BSC0, respectively.

The word lines WL00 to WL0p to WLm0 to WLmp, the block selection lines BSA0 to BSAm, BSB0 to BSBm and BSC0 to BSCm forming the memory array MARY are coupled to the X address decoder XD on the left side thereof and selectively. A predetermined selection or non-selection level is set. In addition, the bit lines BLL0 to BLL
n and BLR0 to BLRn are coupled to the source substrate voltage switching circuit SVC above and to the sense amplifier SA below.

The X address decoder XD has an i + 1 bit internal address signal X0 from the X address buffer XB.
To Xi are supplied and the timing generation circuit TG
Is supplied with an internal control signal CE from the internal voltage generation circuit V
Internal voltages VP2, VP3 and VN3 are supplied from G. Further, the source substrate voltage switching circuit SVC is supplied with the internal address signal Y0 of the least significant bit from the Y address buffer YB and the internal control signal EC from the timing generation circuit TG, and the internal voltage generation circuit VG.
Are supplied with internal voltages VN1 and VN2. further,
The sense amplifier SA is supplied with the internal control signal WC from the timing generation circuit TG and the internal voltage VP1 from the internal voltage generation circuit VG. To the X address buffer XB, X address signals AX0 to AXi are supplied via external terminals AX0 to AXi, and an internal control signal AL is supplied from the timing generation circuit TG.

In this embodiment, the sense amplifier SA
Includes an n + 1-bit data register DR. One input / output node of each bit of the sense amplifier SA is connected to the corresponding bit line BLL0 to BLL of the memory array MARY.
Selectively connected to Ln or BLR0 to BLRn,
The other input / output node is 8 via the Y switch YS.
Bit-by-bit is selectively connected to the data buses DB0 to DB7. The (n + 1) / 8-bit bit line selection signals YS0 to YSq (not shown) are supplied to the Y switch YS from the Y address decoder YD. Further, the Y address decoder YD is supplied with j + 1-bit internal address signals Y0 to Yj from the Y address buffer YB and the internal control signal CE from the timing generation circuit TG. Further, the Y address buffer YB has external terminals AY0 to AY0.
Y address signals AY0 to AYj are supplied via AYj, and an internal control signal AL and an internal control signal DC (not shown) are supplied from the timing generation circuit TG. The data buses DB0 to DB7 are coupled to one input / output terminal of the multiplexer MX and also coupled to the input / output terminal of the mode controller MC. The other input / output terminal of the multiplexer MX is coupled to one input / output terminal of the data input / output circuit IO, and one output signal of the mode controller MC passes through the external terminal R / BB and the ready / busy signal R / BB.
It becomes BB. Further, the other input terminal of data input / output circuit IO is coupled to corresponding data input / output terminals IO0-IO7. Further, the multiplexer MX is supplied with the internal control signal CMD from the timing generation circuit TG.

As for the internal control signal CE, the flash memory has a chip enable signal CEB (here, a so-called inversion signal or the like which is selectively brought to a low level when the flash memory is enabled, has B added at the end of its name. When the selected state is received by receiving the low level (the same applies hereinafter), it is selectively set to the high level. The internal control signal EC is selectively set to a high level at a predetermined timing when the flash memory is selected in the erase mode, and the internal control signal WC is selected when the flash memory is selected in the write mode. It is selectively set to a high level at a predetermined timing. On the other hand, the internal voltages VP1 and VP
2 and VP3 are not particularly limited, but are respectively +1
V, + 6V and + 10V, internal voltage VN1, VN
2 and VN3 are -3V, -4V and -10V, respectively.
It is said.

The X address buffer XB fetches the X address signals AX0 to AXi supplied via the address input terminals AX0 to AXi in accordance with the internal control signal AL,
The internal address signals X0 to Xi are formed based on these X address signals while being held, and are supplied to the X address decoder XD. Also, the X address decoder XD
Decodes the internal address signals X0 to Xi supplied from the X address buffer XB to generate the memory array MAR.
Y word lines WL00 to WL0p to WLm0 to WL
mp, block selection lines BSA0 to BSAm, BSB0 to
BSBm and BSC0 to BSCm are selectively set to a predetermined selection or non-selection level.

Next, the source substrate voltage switching circuit SVC is
According to the internal address signal Y0 and the internal control signal EC,
The bit lines BLL0 to BLLn and BLR0 to BLRn of the memory array MARY are selectively set to a predetermined selection or non-selection level. Further, the sense amplifier SA is n + coupled to the selected word line of the memory array MARY.
From one memory cell MC to the corresponding bit line BLL0
The read signal output via BLLn or BLR0 to BLRn is amplified, serially output from the Y switch YS via the multiplexer MX and the data input / output circuit IO in units of 8 bits, and from the data input / output circuit IO to the multiplexer MX. And write data serially input via the Y switch YS, and write the write data into the n + 1 memory cells MC connected to the selected word line of the memory array MARY according to the internal control signal WC. In order to realize such a serial input / output operation of read or write data, the Y address buffer YB is controlled by the internal address signal Y0 according to the internal control signal DC.
It also has the function of stepping through Yj.

By the way, when the flash memory is set to the write mode, the level of the word line in the selected state is the internal voltage VN3, that is, -1 as shown in FIG.
The level of the word line in the non-selected state is set to 0V and is set to the power supply voltage VCC, that is, + 3V or the ground potential VSS, that is, 0V. Further, the level of the block selection line A in the selected state, that is, BSA0 to BSAm, is the internal voltage VP.
The level of the block selection line A in the non-selected state is set to the ground potential VSS, that is, 0V. At this time, the block selection line B, that is, BSB0 to BSBm and the block selection line C, that is, BSC0 to BSCm, are
All are opened. The sense amplifier SA is connected to the left bit lines BLL0 to BLLn or the right bit lines BLR0 to BLRn to be written.
Supply voltage VCC, that is, + 3V is selectively supplied from
The ground potential VSS, that is, 0V, is supplied to the bit lines that are not the write target. The ground potential VSS is supplied to the well region serving as the substrate portion of the memory cell MC.

As a result, first, 2 × (n
In the +1) memory blocks, the corresponding block select lines BSA0 to BSAm are selectively set to the high level to turn on the select MOSFETs N1 and N2, and the corresponding left bit lines BLL0 to BLLn or the right bit lines BLL0 to BLLn are selected. BLR0 to BLRn to sub bit line SBLL
Alternatively, a write voltage of + 3V is selectively supplied to SBLR. In addition, the gate of the designated memory cell MC of these memory blocks has a corresponding word line WL.
An internal voltage VN3, that is, −10V is supplied via 00 to WL0p to WLm0 to WLmp, and 0V is supplied to the substrate portion thereof. As a result, in the n + 1 memory cells MC connected to the selected word line of the left or right memory block, the electrons accumulated in the floating gate are FN (Fowler Nordheim).
It is pulled out to the drain side by the Nordheim) tunnel phenomenon, and its threshold voltage is changed to a relatively small value.

Next, when the flash memory is set to the erase mode, the level of the word line in the selected state is the internal voltage VP3, that is, + 10V, and the non-selected level is the ground potential VSS, that is, 0V. The levels of the block selection lines A to C are all at the ground potential VSS, that is, 0.
V, and all bit line levels are set to the internal voltage VN1 or -3V. At this time, an internal voltage VN2, that is, −3V, is applied to the well region which is the substrate portion of the memory cell MC.
Is supplied.

As a result, in the 2 × (n + 1) memory cells MC coupled to the selected word line of the memory array MARY, the FN tunnel phenomenon occurs between the substrate portion, that is, the channel and the floating gate, Since electrons are injected into the floating gate from the entire surface of the channel, the threshold voltage is changed to a relatively large value.

On the other hand, when the flash memory is set to the read mode, the level of the word line and block selection line A in the selected state is the power supply voltage VCC, that is, + 3V,
The level of the word line and the block selection line A in the non-selected state is set to the ground potential VSS, that is, 0V. At this time, the level of the selected block selection line B is selectively set to the power supply voltage VCC, that is, + 3V, when the left memory block MBL00 of the two memory blocks MBL00 and MBR00 forming a pair is specified, and the right side When the memory block MBR00 is designated, it is set to the ground potential VSS, that is, 0V. Similarly, the level of the selected block selection line C is selectively set to the power supply voltage VCC, that is, +3 V, when the memory block MBR00 on the right side of the two memory blocks MBL00 and MBR00 forming a pair is designated, and the level on the left side. If the memory block MBL00 is specified, the ground potential VSS
That is, it is set to 0V. The levels of the block selection lines B and C that are in the non-selected state are all the ground potential VSS, that is, 0.
V.

The memory array MARY receives + 3V of the block selection line A and receives, for example, the corresponding 2 × (n + 1) memory blocks MBL00 to MBL0n and MB.
R00 to MBR0n switch MOSFETs N1 and N
2 is turned on, and the sub bit line SBLL or S
A connection state is established between the BLR and the corresponding bit line BLL0 to BLLn or BLR0 to BLRn. Also,
Upon receiving + 3V of the block selection line B, for example, the switch MOSFET N2 of the corresponding left n + 1 memory blocks MBL00 to MBL0n is turned on, and upon receiving + 3V of the block selection line C, for example, the corresponding right side n + 1.
The switch MOSFET N3 of each of the memory blocks MBR00 to MBR0n is turned on. As a result, the bit lines BLR0 to BLRn on the right side are selectively used as source lines when one of the block selection lines B, that is, BSB0 to BSBm is set to the selection level of + 3V, and the bit lines BLL0 to BLLn on the left side are selected. , Block selection line C
That is, any one of BSC0 to BSCm is set to the selection level of + 3V and selectively used as the source line. Needless to say, the right bit line BLR0
When BLRn are used as source lines, the left bit lines BLL0 to BLLn are used as bit lines, and when the left bit lines BLL0 to BLLn are used as source lines, the right bit lines BLR0 to BLRn are used as source lines. used.

In the read mode, for example, when the memory cell MC coupled to the word line WL00 of the left memory block MBL00 is selected, the drain of the selected memory cell MC is sensed as illustrated in FIG. An internal voltage VP1, that is, a read voltage of +1 V is applied from the amplifier SA via the left bit line BLL0 used as a bit line, the switch MOSFET N1 and the sub bit line SBLL. Therefore, the selected memory cell M
When C is in the written state and the threshold voltage thereof is low, this selected memory cell MC is turned on, and the sub-source line SSLL switches the switch MOSFET.
A relatively large read current as indicated by a dotted line flows through N3 and the right bit line BLR0 used as a source line. When the selected memory cell MC remains in the erased state and its threshold voltage is high, the selected memory cell MC is turned off and no read current flows. The read current through the selected memory cell MC is sensed by the corresponding amplifier circuit of the sense amplifier SA, and is taken into the corresponding data register as read data of logic “0” or “1”.

Similarly, in the read mode, for example, when the memory cell MC coupled to the word line WL00 of the right memory block MBR00 is selected, the drain of the selected memory cell MC is exemplified in FIG. In addition, the internal voltage VP1, that is, + via the bit line BLR0 on the right side used as a bit line from the sense amplifier SA, the switch MOSFET N2 and the sub bit line SBLR.
A read voltage of 1V is applied. Therefore, when the selected memory cell MC is in the written state and its threshold voltage is low, the selected memory cell MC is turned on and the sub-source line SSLR switches to the switch MO.
A relatively large read current as indicated by a dotted line flows through the SFET N4 and the left bit line BLL0 used as a source line. When the selected memory cell MC remains in the erased state and its threshold voltage is high, the selected memory cell MC is turned off and no read current flows. The read current through the selected memory cell MC is sensed by the corresponding amplifier circuit of the sense amplifier SA, and is taken into the corresponding data register as read data of logic “0” or “1”.

As described above, in the flash memory of this embodiment, for example, a pair of bit lines B is provided between a pair of memory blocks MBL00 and MBR00 which are adjacent in the row direction.
LL0, BLR0, etc. are arranged, and these bit lines which are normally used as bit lines are set to the selection level by selecting either the block selection line C, that is, BSC0 to BSCm or the block selection line B, that is, BSB0 to BSBm. Selectively used as a source line. As a result,
In the flash memory of this embodiment, the same function as that of the conventional flash memory can be realized without providing a dedicated source line, so that the number of required selection signal lines of the flash memory can be significantly reduced, and thus the flash memory can be reduced. It is possible to reduce the cost.

FIG. 7 shows a block diagram of a second embodiment of the memory array MARY included in the flash memory of FIG. Further, FIG. 8 shows a partial circuit diagram of one embodiment of the memory array MARY of FIG. 7, and FIGS. 5 and 6 show connection diagrams at the time of reading even bit lines and at the time of reading odd bit lines. Are shown respectively. Since the memory array MARY of this embodiment basically follows the embodiments of FIGS. 2 to 6, only the parts different from this will be described.
Further, in the following description, the specific connection conditions and the like of the memory array MARY are described by taking the read mode as an example.
The write and erase modes should be inferred from the description of the above embodiment and the description of the read mode.

In FIG. 7, the memory array MARY of this embodiment is arranged in a substantially lattice pattern (m + 1) × (n.
+1) memory blocks MB00 to MB0n to M
Bm0 to MBmn, and n + 2 column selection signal lines, that is, bit lines BL0 to BLn alternately arranged in the row direction between the memory blocks.

Here, the memory blocks MB00 to MB0n to MBm0 to M constituting the memory array MARY.
Bmn is the memory blocks MB00 and MB01 of FIG.
, P + 1 arranged in the same column as shown in FIG.
Each of the two-layer gate structure type memory cells MC is included.
Hereinafter, a detailed description of the memory blocks will be given by taking these memory blocks MB00 and MB01 as an example.

The control gates of the memory cells MC constituting the memory blocks MB00 and MB01 are commonly coupled to the corresponding word lines WL00 to WL0p, and the drains and sources thereof are respectively common to the corresponding sub bit lines SBL and sub source lines SSL. Be combined. Of these, the sub-bit line SBL of each memory block is connected to the corresponding switch means, that is, the bit line BL0 or BL1 arranged on the left side thereof via the N-channel MOSFET N5 or N6.
And the sub-source line SSL is connected to the corresponding switch means, that is, the N-channel MOSFET N7.
Or, the bit line BL1 arranged on the right side through N8
Alternatively, they are commonly coupled to BL2. MOSFET N
The gates of 5 and N6 are corresponding block select lines BSA
0, and the gates of MOSFETs N7 and N8 are commonly connected to the corresponding block select line BSB0 or BSC0, respectively.

When the flash memory is set to the read mode, the level of the selected word line and the block selection line A, that is, BSA0 to BSAm is set to the power supply voltage VCC, that is, + 3V as in the above embodiment, and the non-selected state is set. The level of a certain word line and block selection line A is set to the ground potential VSS, that is, 0V. At this time, the level of the selected block selection line B, that is, BSB0 to BSBm is selectively set to the power supply voltage VCC, that is, + 3V when the even-numbered memory blocks MB00, MB02, etc. are designated, and the even-numbered memory block MB01. , M
When B03 etc. is specified, ground potential VSS, that is, 0 V
It is said. Similarly, the level of the selected block selection line C, that is, BSC0 to BSCm is selectively set to the power supply voltage VCC, that is, + 3V when the odd-numbered memory blocks MB01, MB03, etc. are designated, and the even-numbered memory block MB00. , MB02, etc. are set to the ground potential VSS, that is, 0V. The levels of the block selection lines B and C that are in the non-selected state are all set to the ground potential VSS, that is, 0V.

In the memory array MARY, the switch MOSFETs N5 and N6 of the corresponding n + 1 memory blocks MB00 to MB0n are turned on upon receiving + 3V of the block selection line A, and the left bit line BL0 corresponding to the sub bit line SBL. And BL1 and the like are connected. Further, receiving + 3V of the block selection line B, (n + 1) / 2 even-numbered memory blocks MB0
The switch MOSFET N7 of 0, MB02, etc. is turned on, and the switch MOSFET N8 of the odd numbered (n + 1) memory blocks MB01, MB03, etc. is turned on by receiving + 3V of the block selection line C. As a result, in the odd-numbered bit lines BL1 and BS3, etc., the block select line B, that is, any of BSB0 to BSBm is +.
By setting the selection level to 3V, it is selectively used as a source line, and for the even-numbered bit lines BL0 and BS2, the block selection line C, that is, one of BSC0 to BSCm is set to the selection level of + 3V. It is selectively used as a source line. Needless to say, when the odd-numbered bit lines BL1 and BS3 and the like are used as source lines, the even-numbered bit lines BL0 and BS2 and the like are used as bit lines and the even-numbered bit line BL0.
, BS2, etc. are used as source lines, odd-numbered bit lines BL1, BS3, etc. are used as source lines.

In the read mode, for example, when the memory cell MC coupled to the word line WL00 of the even-numbered memory block MB00 is selected, the drain of the selected memory cell MC is, as illustrated in FIG. An internal voltage VP1, that is, a read voltage of + 1V is applied from the sense amplifier SA via the even-numbered bit line BL0 used as a bit line, the switch MOSFET N5, and the sub-bit line SBL. Therefore, when the selected memory cell MC is in the written state and the threshold voltage thereof is low, the selected memory cell MC is turned on and the switch MOSFET is switched from the sub-source line SSL to the switch MOSFET.
A relatively large read current as indicated by a dotted line flows through N7 and the odd-numbered bit line BL1 used as a source line. If the selected memory cell MC is left in the erased state and its threshold voltage is high, the selected memory cell MC is turned off and no read current flows. The read current through the selected memory cell MC is sensed by the corresponding amplifier circuit of the sense amplifier SA, and is taken into the corresponding data register as read data of logic “0” or “1”.

As is apparent from the above description, in the flash memory of this embodiment, even or odd numbered memory blocks are selectively activated, so that the writing and reading of the stored data is (n + 1) / 2. The data register DR of the sense amplifier SA is (n
It has a +1) / 2 bit configuration. Further, the memory array M
Of the bit lines BL0 to BLn forming ARY, the bit line BL0 arranged on the leftmost side is used only as a bit line, and the bit line BLn + 1 arranged on the rightmost side.
Are used only as source lines.

Next, in the read mode, for example, when the memory cell MC coupled to the word line WL00 of the odd-numbered memory block MB01 is selected, the drain of this selected memory cell MC is exemplified in FIG. So that the odd numbered bit lines BL1 and switch MOSFET N6 used as bit lines from the sense amplifier SA
Further, the internal voltage VP1, that is, the read voltage of +1 V is applied via the sub bit line SBL. Therefore, when the selected memory cell MC is in the written state and its threshold voltage is low, the selected memory cell MC is turned on and the sub-source line SSL switches to the switch MOSF.
A relatively large read current as indicated by a dotted line flows through ETN8 and the even-numbered bit line BL2 used as a source line. When the selected memory cell MC remains in the erased state and its threshold voltage is high, the selected memory cell MC is turned off and no read current flows. The read current through the selected memory cell MC is sensed by the corresponding amplifier circuit of the sense amplifier SA, and is taken into the corresponding data register as read data of logic “0” or “1”.

As described above, in the flash memory of this embodiment, n + 1 memory blocks MB00 to MB0 are included.
n to MBm0 to MBmn and n + 2 bit lines BL
0 to BLn are alternately arranged in the row direction. Among them, the odd-numbered bit lines BL1 and BL3 and the like are selectively used as source lines by setting the corresponding block selection line B, that is, BSB0 to BSBm, to the even-numbered bit lines BL2 and BL4 and the like. Is selectively used as a source line by setting the corresponding block selection line C, that is, BSC0 to BSCm to the selection level. As a result, even in the flash memory of this embodiment, the same function as that of the conventional flash memory can be realized without providing a dedicated source line, so that the required number of selection signal lines as the flash memory can be significantly reduced and its cost can be reduced. It can be realized.

The functions and effects obtained from the above embodiment are as follows. That is, (1) a pair of two memory blocks in a semiconductor memory device such as a NOR flash memory whose basic constituent element is a memory array in which two-layer gate structure type non-volatile memory cells are arranged in a substantially lattice pattern. By selectively using a pair of column selection signal lines arranged between them or two column selection signal lines arranged on both sides of each memory block as a bit line or a source line, Also, it is possible to obtain the effect that it can also be used as a source line. (2) According to the above item (1), the required selection signal lines of the memory array such as a flash memory can be significantly reduced. (3) According to the above items (1) and (2), there is an effect that the chip size of the flash memory or the like can be reduced and the cost thereof can be reduced.

The invention made by the inventor of the present invention has been specifically described based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the memory array MARY can be divided into a plurality of memory mats including its direct peripheral circuits. Further, the flash memory can take any bit configuration such as x1 or x16 bits, and does not require serial input / output of data. The flash memory can adopt a so-called address multiplex system, and its block configuration can also adopt various embodiments. Furthermore, the combination, name and logic level of the start control signal and the internal control signal, the power supply voltage and the polarities and absolute values of the internal voltages are not restricted by this embodiment, and the selection conditions of the memory array MARY are also the same. .

In the above description, the case where the invention made by the present inventor is mainly applied to a flash memory which is a field of application which is the background of the invention has been described. However, the invention is not limited thereto and, for example, an EEPROM (electric The present invention can also be applied to various semiconductor memory devices such as a read-only memory) in which stored information can be erased and rewritten, and digital systems such as a microcomputer including these semiconductor memory devices. The present invention can be widely applied to a semiconductor memory device requiring at least a bit line and a source line and a system including such a semiconductor memory device.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor memory device such as a NOR flash memory having a memory array in which non-volatile memory cells of a two-layer gate structure type are arranged in a substantially lattice pattern as a basic constituent element, a two-layer gate structure type nonvolatile memory cell is arranged between two memory blocks forming a pair. The column selection signal lines are selectively used as the bit lines or the source lines by selectively using the paired column selection signal lines or the two column selection signal lines arranged on both sides of each memory block as the bit lines and the source lines. Also, since the required selection signal lines of the memory array can be significantly reduced, the chip size of the NOR flash memory or the like can be reduced and the cost thereof can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a flash memory to which the present invention is applied.

FIG. 2 is a block diagram showing a first embodiment of a memory array included in the flash memory of FIG.

FIG. 3 is a partial circuit diagram showing an embodiment of the memory array of FIG.

FIG. 4 is a selection condition diagram showing an embodiment of the memory array of FIG.

5 is a connection diagram of the memory array of FIG. 2 when reading a left memory block.

FIG. 6 is a connection diagram at the time of reading the right memory block of the memory array of FIG.

7 is a block diagram showing a second embodiment of a memory array included in the flash memory of FIG. 1. FIG.

FIG. 8 is a partial circuit diagram showing an embodiment of the memory array of FIG.

9 is a connection diagram of the memory array of FIG. 7 when reading even bit lines.

10 is a continuation view of the memory array of FIG. 7 when reading odd bit lines.

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, XB ... X address buffer, SVC ... source substrate voltage switching circuit, SA ... sense amplifier, YS ... Y switch, YD ... Y address decoder, YB ... … Y address buffer, MC …… mode controller, MX ……
Multiplexer, IO ... Data input / output circuit, TG ...
Timing generator, VG ... Internal voltage generator. MB
L00 to MBL0n to MBLm0 to MBLmn, M
BR00 to MBR0n to MBRm0 to MBRmn,
MB00 to MB0n to MBm0 to MBmn ... Memory block, BSA0 to BSAm ... Block selection line A, BSB0 to BSBm ... Block selection line B, BSC
0 to BSCm ... Block selection line C, WL00 to WL0
p to WLm0 to WLmp ... Word line, BLL0
BLLn, BLR0 to BLRn, BL0 to BLn + 1 ...
... bit lines. MC: 2-layer gate structure type memory cell, S
BLL, SBLR, SBL ... Sub bit line, SSL
L, SSLR, SSL ... Sub-source line. N1-N8 ...
... N-channel MOSFET.

Front page continuation (72) Inventor Toshifumi Noda 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (4)

[Claims] 1. A memory array comprising non-volatile memory cells arranged in a substantially lattice pattern, and column selection signal lines arranged in parallel in a column direction and selectively used as bit lines or source lines. A semiconductor memory device comprising: 2. The memory cells are divided into memory blocks in units of a predetermined number arranged in the same column, and the drains and sources of the predetermined number of memory cells forming each memory block have corresponding sub-bit lines and sub-sources. 2. The semiconductor memory device according to claim 1, wherein the lines are commonly coupled to each other. 3. The memory blocks are paired with two adjacent to each other in the row direction, and the column selection signal lines are arranged in pairs between two memory blocks forming a pair, and The semiconductor according to claim 1 or 2, wherein each of the two column selection signal lines forming a pair is used as a source line when one of the column selection signal lines is used as a bit line. Storage device. 4. The column selection signal line is arranged alternately with the memory block, and the left side of each of the two column selection signal lines arranged on both sides of each memory block is used as a bit line. 3. The semiconductor memory device according to claim 1 or 2, wherein the right side thereof is used as a source line.