JPH09159727A - Cmos semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly accurately execute testing by providing a test circuit which is connected to a test signal input terminal and a power source line and holds a logic between a data input terminal and a data output terminal when a test signal is input to the test signal input terminal in the same manner as when a test is not carried out. SOLUTION: A test circuit part 6a consists of a second inverter 16 for inverting data connected to a data input terminal 1, a two-input NAND circuit 17 connected to an output terminal of the inverter 16 and a test signal input terminal 3, a pMOS transistor 14 driven by an output of the circuit 17, a two- input AND circuit, 18 connected to the terminals 1, 3 and an nMOS transistor 15a driven by an output of the circuit 18. The transistors 14, 15a are connected in series between a power source 12 and a ground 13. A common connecting part of the transistors is connected to a first inverter 7. When an Idd test is carried out, a potential at the common connecting part of the transistors 14, 15a becomes a pseudo output of a differential amplifier part 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor device having a test circuit.

[0002]

2. Description of the Related Art Conventionally, in a CMOS semiconductor device having a CMOS circuit, various test circuits and test methods have been considered in order to obtain a high failure detection rate. The failure detection rate is a rate of failures that can be detected in all possible failures such as elements and wirings of a CMOS semiconductor device during a test. Therefore, a test with a high failure detection rate can select defective products with a high probability.

As a general test method, there is one in which a test pattern is input to an input terminal and it is determined whether or not the output terminal outputs a correct value according to the logic of the circuit. Therefore, in this test, when the circuit has a failure, the output terminal outputs a value different from the expected value.

However, in recent years, as the semiconductor process has become finer and the circuit scale of the CMOS semiconductor device has become larger, the test pattern length tends to increase in order to obtain a high failure detection rate in the above-mentioned test. As the length of the test pattern increases, a problem that a huge amount of time is spent to create the test pattern has arisen.

In order to solve such a problem, Idd
A q-test was considered. The Iddq test will be briefly described below.

In a CMOS circuit, a current flows when a signal changes, but normally, when the signal does not change, that is, in a steady state, there is no path from the power supply to the ground (GND), and in such a steady state. , Several μA to tens of μ
Only the current of A flows. The Iddq test is a method of finding a failure by utilizing the characteristics of such a CMOS circuit and measuring a current in a steady state.

Recently, due to the use of a complex logic block or the like, even if a current flows, the number of cases in which the voltage drop settles down to a level not exceeding the threshold voltage and the operation becomes normal in the function test is increasing. In this case, the operation is normal, but the Iddq test fails. In such a case, it may be said that there is no problem because the operation is normal, but the low power consumption characteristic of the CMOS circuit disappears.

As described above, the Iddq test is characterized in that it can detect defects that cannot be detected by the function test.

Further, even if there is a defect that can be detected by a function test, in order to detect the defect as a failure, in addition to activating the input of the defective transistor, its influence is propagated to the output terminal. There is a need. On the other hand, in the Iddq test, by activating the input, the detection result can be observed through the power supply line, and it is not necessary to propagate the value to the output, and only the transistor is operated. Since it is good, it can be used as a complement to the function test.

The Iddq test can detect more than half of all fault definitions of the CMOS semiconductor device by measuring the steady-state current of the CMOS circuit with one test pattern. Furthermore, CMOS
By measuring the steady-state current with a plurality of test patterns that change the inside of the circuit, it is possible to effectively obtain a high fault coverage with a small test pattern.

Here, a point to be noted in the Iddq test is that the CMOS semiconductor device is a CMOS circuit,
An example is a combination of a PULL-UP buffer or a PULL-DOWN buffer. PU
The LL-UP buffer and the PULL-DOWN buffer are buffers each having a resistance connected to a power supply and a ground in addition to a transistor path.
In the buffer, when the output value becomes 0, PULL-
In the DOWN buffer, when the output value becomes 1, a current path is formed between the power supply and the ground. Therefore, when selecting a test pattern, it is necessary to avoid a test pattern that causes a current path as described above.

However, when these buffers have the current cut mode, by cutting the current path, the power supply current flowing from the power supply to the ground (GND) in the steady state can be made zero, and I
The reliability of the ddq test can be improved. Therefore, the circuit of the CMOS semiconductor device that performs the Iddq test has zero power supply current from the power supply to GND in the steady state.
With the function that makes it possible to perform high-precision tests.

As an example of such a CMOS semiconductor device, there is a conventional CMOS differential circuit as shown in FIG. This CMOS differential circuit has a data input terminal 1
, Data inversion input terminal 2 and test signal input terminal 3
And the output terminal 4, and includes a differential amplifier section 5, a test circuit section 6b, and a first inverter 7.

Here, the test circuit section 6b comprises an nMOS transistor 15b connected to the test signal input terminal 3 and driven by the test signal.
The input to the first inverter 7 during the test is controlled.

When performing an Iddq test using a differential circuit having such a test circuit, "H" is input to the test signal input terminal 3 to set the power supply current of the differential amplifier section 5 to zero. At this time, since the nMOS transistor 15b of the test circuit section 6b is turned on, the differential amplifier section output 11
The potential of is fixed to the pseudo output "L". Further, since the power supply current of the first inverter 7 also becomes 0, the power supply current of the entire differential circuit becomes 0, which enables the Iddq test. At this time, the potential of the output terminal 4 is fixed at "H".

When "L" is input to the test signal input terminal 3, the nMOS transistor 15b of the test circuit section 6b is turned off and the CMOS differential circuit operates normally.

[0017]

However, in the conventional CMOS differential circuit described above, when the Iddq test is performed, that is, when "H" is input to the test signal input terminal 3, the pseudo of the differential amplifier section 5 is simulated. Output is fixed to "L", whereby the first inverter 7
Will always output "H". Therefore, the first
There is a problem that the failure cannot be detected when the output of the inverter 7 is "L", and the failure detection rate is difficult to increase.

The object of the present invention is to solve the above problems and
Another object of the present invention is to provide a differential circuit that outputs the same logical value as in normal operation even when performing a ddq test.

[0019]

According to the present invention, a power supply line, a data input terminal, a buffer circuit connected to the data input terminal and the power supply line, and a buffer circuit connected to the buffer circuit and the power supply line. A CMOS circuit, a data output terminal connected to the CMOS circuit, a test circuit, a test signal input terminal for inputting a test signal indicating a test, and a test connected to the test signal input terminal. A switch circuit for disconnecting the connection between the buffer circuit and the power supply line when a signal is input,
While not testing, the data output terminal outputs data of a predetermined logical value according to the input data from the data input terminal, and at the time of testing, the test signal input while the input to the data input terminal is fixed. In a CMOS semiconductor device configured to perform a test by inputting the test signal to a terminal, the test circuit is connected in parallel with the buffer circuit between the data input terminal and the CMOS circuit, The test circuit is further connected to the test signal input terminal and a power supply line, and when the test signal is input to the test signal input terminal, a logic between the data input terminal and the data output terminal. It is possible to obtain a CMOS semiconductor device having a function of keeping the same as that at the time of non-test.

Further, according to the present invention, in the CMOS semiconductor device, the data input terminal includes first and second data input terminals.
Data input terminal, the data input to the second data input terminal is data having an inverted value of the data input to the first data input terminal, and the buffer circuit is A CMOS semiconductor device is obtained which is a differential amplifier connected to the first and second data input terminals, and the CMOS circuit is a first inverter.

According to the present invention, in particular, in the CMOS semiconductor device, the test circuit is connected to the first data input terminal and inverts the data input to the first data input terminal. An inverter, a two-input NAND circuit connected to the output terminal of the second inverter and the test signal input terminal, and a pMOS connected to the output terminal of the two-input NAND circuit and driven by the output of the two-input NAND circuit. A transistor, a two-input AND circuit connected to the first data input terminal and the test signal input terminal, and an nM connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit.
An OS transistor, the pMOS transistor and the nMOS transistor are connected in series between the power supply line and the ground, and the pMO transistor is further connected to the pMO transistor.
A CMOS semiconductor device is obtained in which the potential of the common connection portion of the S transistor and the nMOS transistor serves as the input of the first inverter.

Further, according to the present invention, in the CMOS semiconductor device, the test circuit includes a two-input NAND circuit connected to the second data input terminal and the test signal input terminal, and the two-input NAND circuit. Connected to the output terminal of the two-input NAND circuit and driven by the output of the two-input NAND circuit.
A MOS transistor, a two-input AND circuit connected to the first data input terminal and the test signal input terminal, and an nMOS connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit. A transistor, the pMOS transistor and the nMOS transistor are connected in series between the power supply line and the ground, and the potential of the common connection portion of the pMOS transistor and the nMOS transistor is the first inverter. It is possible to obtain a CMOS semiconductor device which is characterized in that

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a CM according to an embodiment of the present invention.
The OS differential circuit will be described with reference to the drawings.

(First Embodiment) A CMOS differential circuit according to the first embodiment of the present invention has a circuit configuration as shown in FIG. That is, the CM according to the first embodiment of the present invention
The OS differential circuit has a data input terminal 1, a data inversion input terminal 2, and a test signal input terminal 3, and is composed of a differential amplifier section 5, a test circuit section 6 a, and a first inverter 7.

The test circuit section 6a includes a second inverter 16 connected to the data input terminal 1 and inverting the data input to the data input terminal 1, and a second inverter 1.
6, a two-input NAND circuit 17 connected to the output terminal of 6 and the test signal input terminal 3, a pMOS transistor 14 connected to the output terminal of the two-input NAND circuit 17 and driven by the output of the two-input NAND circuit 17, and a data input. A two-input AND circuit 18 connected to the terminal 1 and the test signal input terminal 3, and an output terminal of the two-input AND circuit 18, which is driven by the output of the two-input AND circuit 18.
It is composed of a MOS transistor 15a. Here, the pMOS transistor 14 and the nMOS transistor 15a are connected in series between the power supply 12 and the ground 13. Furthermore, pMOS transistor 14 and n
The common connection portion with the MOS transistor 15a is connected to the first inverter 7, and during the Iddq test,
pMOS transistor 14 and nMOS transistor 15
The potential of the common connection portion with a becomes an input signal to the first inverter 7, that is, a pseudo output of the differential amplifier section output 11.

The circuit operation of the CMOS differential circuit according to the first embodiment of the present invention having such a circuit configuration will be described with reference to a timing chart as shown in FIG.

2A to 2H show a timing chart of each node in the CMOS differential circuit of the first embodiment shown in FIG. Here, (a) is a timing chart of an input signal to the data input terminal 1, (b) is a timing chart of an input signal to the data inverting input terminal 2, and (c) is a test signal input terminal 3. 3D is a timing chart of the input signal of FIG. 3D, and FIG. 3D is a timing chart of the output signal from the output terminal 4. Further, (e) is a timing chart of the differential amplifier section output 11, and (f) is the pMOS of the test circuit section 6a.
It is a timing chart of the transistor gate 9,
(G) is a timing chart of the nMOS transistor gate 10 of the test circuit section 6a. Further, (h) shows a timing chart of the current of the power supply 12.

First, at time t ₀ , the data input terminal 1 is "L" (see (a)), the data inversion input terminal 2 is "H" (see (b)), and the test signal input terminal 3 is "L".
When ((c)) is input, the differential amplifier section output 11 becomes “H ′” (H> H ′) (see (e)), and the “H ′” signal is input to the first inverter 7. The output from the output terminal 4 becomes "L" (see (d)). At this time, a power supply current is generated in the differential amplifier section 5 and the first inverter 7 (see (h)).

Next, at time t ₁ , the input to the data input terminal 1 changes from "L" to "H" (see (a)), and the input to the data inversion input terminal 2 changes from "H" to "L". (See (b)), the differential amplifier output 11 changes from “H ′” to “L ′” (see (e)), and the output from the output terminal 4 changes from “L” to “H” (see (e)). (See (d)) Change. At this time, as in the case of time t ₀ , a power supply current is generated in the differential amplifier section 5 and the first inverter 7 (see (h)).

Next, at time t ₂ , when the input to the test signal input terminal 3 changes from "L" to "H" (see (c)), the pMOS transistor 8 of the differential amplifier section 5 is turned off. , The test circuit unit 6a operates, and the nMOS transistor gate 10 of the test circuit unit 6a is "L".
Changes to "H" (see (g)), and the test circuit unit 6a
The nMOS transistor 15a is turned on, and the differential amplifier section output 11 changes from "L '" to a pseudo output "L" (see (e)). However, the output from the output terminal 4 is
It remains “H” (see (d)). Here, the power supply current changes to "0" because the pMOS transistor 8 of the differential amplifier unit 5 is turned off and the differential amplifier unit 5 is disconnected (see (h)). At this time, the output logic value at the output terminal 4 of the CMOS differential circuit remains the output logic value at the time of normal operation, the power supply current becomes 0, and the Iddq test becomes possible.

Next, at time t ₃ , when the input to the test signal input terminal 3 changes from "H" to "L" (see (c)), the nMOS transistor gate 15a of the test circuit section 6a becomes "H". From "" to "L" (see (g)), and the differential amplifier section output 11 changes from the pseudo output "L" to the actual output "L '" ((e)).
reference). However, the output from the output terminal 4 remains "H" (see (d)). In addition, pM of the differential amplifier unit 5
The OS transistor 8 is turned on, a power supply current is generated in the differential amplifier section 5 (see (h)), and the CMOS differential circuit returns to normal operation.

Next, at time t ₄ , the input to the data input terminal 1 changes from "H" to "L" (see (a)), and the input to the data inversion input terminal 2 changes from "L" to "H". (See (b)), the differential amplifier section output 11 changes from "L" to "H" (see (e)), and the output from the output terminal 4 changes from "H" to "L" ((d ) See) change. At this time, a power supply current is generated in the differential amplifier section 5 and the first inverter 7 as at time t ₁ (see (h)).

Next, at time t ₅ , when the input to the test signal input terminal 3 changes from "L" to "H" (see (c)), the pMOS transistor 8 of the differential amplifier section 5 is turned on. The circuit is turned off, the test circuit section 6a operates, and the pMOS transistor gate 9 of the test circuit section 6a is turned on.
Changes from "H" to "L" (see (f)), and the pMOS transistor 14 of the test circuit section 6a changes from off to on. As a result, the output 11 of the differential amplifier unit becomes "H".
The output from the output terminal 4 remains "L" (see (d)), and the power supply current is the time t. It becomes “0” as in the case of _2. At this time, the output logic value at the output terminal 4 of the CMOS differential circuit remains the output logic value in the normal operation, the power supply current becomes 0, and the Iddq test becomes possible. Become.

Next, at time t ₆ , when the input to the test signal input terminal 3 changes from "H" to "L" (see (c)), the pMOS transistor gate 9 of the test circuit section 6a becomes " Change from L ”to“ H ”((f)
The output 11 of the differential amplifier section is a pseudo output “H”.
Changes to the actual output "H '" (see (e)).
At this time, the output from the output terminal 4 remains "L" (see (d)). Further, the pMOS transistor 8 of the differential amplifier section 5 is turned on from off, a power supply current is generated in the differential amplifier section 5 (see (h)), and the CMOS differential circuit returns to the normal operation.

In this way, the CM of the first embodiment is
The OS differential circuit cuts off between the differential amplifier unit 5 and the power supply, sets the power supply current to 0, performs the Iddq test of the CMOS differential circuit, and artificially creates the output of the differential amplifier unit for normal operation. It is possible to output the same logical value as.

(Second Embodiment) A CMOS differential circuit according to a second embodiment of the present invention will be described with reference to the drawings.

The CMOS differential circuit of the second embodiment is
The circuit configuration is as shown in FIG. Referring to FIG. 3, it can be seen that the circuit configuration is substantially the same as that of the CMOS differential circuit of the first embodiment, but the test circuit section 6a is different.

The test circuit section 6a in the CMOS differential circuit according to the second embodiment has a two-input NAND circuit 17 connected to the data inverting input terminal 2 and the test signal input terminal 3.
A pMOS transistor 14 connected to the output terminal of the two-input NAND circuit 17 and driven by the output of the two-input NAND circuit 17, and a two-input AND circuit 18 connected to the data input terminal 1 and the test signal input terminal 3, An nMOS transistor 15a connected to the output terminal of the two-input AND circuit 18 and driven by the output of the two-input AND circuit 18. Here, the pMOS transistor 14 and the nMOS transistor 15a are connected to the power source 1
It is connected in series between 2 and the ground 13. Further, the common connection portion of the pMOS transistor 14 and the nMOS transistor 15a is connected to the first inverter 7, and during the Iddq test, the potential of the common connection portion of the pMOS transistor 14 and the nMOS transistor 15a is the first inverter 7. Input signal, that is, a pseudo output of the differential amplifier section output 11.

In the CMOS differential circuit of the second embodiment, at the input of the two-input NAND circuit 17 which becomes the signal of the gate 9 of the pMOS transistor, like the CMOS differential circuit of the first embodiment, Instead of passing the input from the data input terminal 1 to the two-input NAND circuit 17 after passing through the second inverter 16, the input from the data inverting input terminal 2 is directly input to the two-input NAND circuit 17. . As a result, as compared with the CMOS differential circuit of the first embodiment, the number of the second inverter 16 is reduced by one, which has the advantage of reducing the circuit area.

The timing chart at each node of the circuit is the same as that of the CMOS differential circuit of the first embodiment.

[0041]

As described above, according to the present invention, it is possible to obtain a CMOS semiconductor device that facilitates highly accurate testing without lowering the failure detection rate when performing the Iddq test. Was given.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a CMOS differential circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart at each node of the CMOS differential circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a CMOS differential circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional CMOS differential circuit.

[Explanation of symbols]

 1 data input terminal 2 data inversion input terminal 3 test signal input terminal 4 output terminal 5 differential amplifier section 6a test circuit section (present invention) 6b test circuit section (conventional) 7 first inverter 8 pMOS transistor of differential amplifier section 9 pMOS transistor gate of test circuit section 10 nMOS transistor gate of test circuit section 11 differential amplifier section output 12 power supply 13 ground (GND) 14 pMOS transistor of test circuit section 15a nMOS transistor of test circuit section 15b nMOS transistor of test circuit section 16 Second Inverter 17 Two-Input NAND Circuit 18 Two-Input AND Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 27/092 H03K 19/094 B H03K 19/00 19/0948

Claims (4)

[Claims] 1. A power supply line, a data input terminal, a buffer circuit connected to the data input terminal and the power supply line, a CMOS circuit connected to the buffer circuit and the power supply line, and a CMOS circuit connected to the CMOS circuit. Data output terminal, a test circuit, a test signal input terminal for inputting a test signal that means to perform a test, the buffer circuit and the power supply line connected to the test signal input terminal when the test signal is input And a switch circuit for disconnecting the connection between the data input terminal and the data input terminal at the time of non-test, the data output terminal outputs data of a predetermined logical value to the data input terminal at the time of test. CMOS that is designed to perform the test by inputting the test signal to the test signal input terminal while fixing the input of In the semiconductor device, the test circuit includes the data input terminal and the CMOS.
The test circuit is connected in parallel with the buffer circuit, and the test circuit is further connected to the test signal input terminal and the power supply line, and the test signal is input to the test signal input terminal. CMOS, which has a function of keeping the logic between the data input terminal and the data output terminal the same as when not tested.
Semiconductor device. 2. The CMOS semiconductor device according to claim 1, wherein the data input terminal includes first and second data input terminals, and the data input to the second data input terminal is the first data input terminal. The buffer circuit is a differential amplifier connected to the first and second data input terminals, and the CMOS circuit has a first value. CMOS semiconductor device characterized by being an inverter of. 3. The CMOS semiconductor device according to claim 2, wherein the test circuit is a second inverter that is connected to the first data input terminal and inverts data input to the first data input terminal. A two-input NAND circuit connected to the output terminal of the second inverter and the test signal input terminal; and a pMOS connected to the output terminal of the two-input NAND circuit and driven by the output of the two-input NAND circuit.
A transistor, a two-input AND circuit connected to the first data input terminal and the test signal input terminal, and an nMOS transistor connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit The pMOS transistor and the nMOS transistor are connected in series between the power line and the ground, and the pMOS transistor and the nMOS are further connected.
A CMOS semiconductor device, wherein a potential of a common connection portion with a transistor serves as an input of the first inverter. 4. The CMOS semiconductor device according to claim 2, wherein the test circuit is a two-input NAND circuit connected to the second data input terminal and the test signal input terminal,
A pMOS transistor connected to an output terminal of the two-input NAND circuit and driven by an output of the two-input NAND circuit; a two-input AND circuit connected to the first data input terminal and the test signal input terminal; An nMOS transistor connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit, wherein the pMOS transistor and the nMOS transistor are connected in series between the power supply line and the ground, Further, the pMOS transistor and the nMOS
A CMOS semiconductor device, wherein a potential of a common connection portion with a transistor serves as an input of the first inverter.