JPH09130235A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the operation of a digital phase locked loop(PLL) circuit by removing a pulse noise narrower than the width of a signal by providing a pulse removing circuit inside a digital PLL ring oscillator. SOLUTION: A ring oscillator 1 is formed by connecting an odd number of inverters 11-1n in the shape of ring so as to circulate a pulse signal. In this case, concerning the ring oscillator circuit 1 one stage of pulse signal delay circuit is composed of two inverters, and these delay circuits are provided for the desired number of stages. Then, any one of outputs from the respective delay circuits is alternatively selected by a multiplexer 2, and the selected output of the delay circuit becomes the output signal of the multiplexer 2 and is inputted to the first stage of the ring oscillator circuit 1. Further, a noise removing circuit 5 for removing the noise pulse of gridge and an inverter 6 for compensating the inversion of signal caused by this noise are inserted into the group of delay circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a digital PLL (Ph
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of an ase locked loop) circuit, and more particularly to a digital PLL circuit in which malfunction due to noise is reduced.

[0002]

2. Description of the Related Art An example of a conventional digital PLL circuit is shown in FIG.
This will be described with reference to FIG. In the figure, a ring oscillator circuit 1 serving as a local oscillator of a PLL circuit is configured by connecting an odd number of inverters 11 to 1n in a ring shape via a multiplexer 2, and oscillates by circulating a pulse signal.
As shown in FIG. 6A, the ring oscillator circuit shifts rightward while inverting the digital value output from each inverter, and the output of the final stage is returned to the initial stage. For example,
The initial value "11010" is sequentially shifted as shown in FIG. 7B, and a signal waveform that is repeated in a certain cycle is obtained at the output of the inverter.

The inverters 11 to 1n forming the ring oscillator circuit 1 form a one-stage pulse signal delay circuit by two inverters. This delay circuit is provided in the required number of stages. Any output of each delay circuit is selected by the multiplexer 2 and fed back to the first stage of the ring oscillator circuit 1. Further, the output signal of the inverter 11 is input to the phase comparator 3 together with the reference input signal.

The phase comparator 3 compares the phase of the output signal of the inverter 11 and the phase of the reference input signal, and supplies either the up signal UP or the down signal DN to the up / down counter 4 according to the comparison result. The phase comparator 3 outputs a down signal when the phase of the reference input signal is faster than the phase of the output signal of the multiplexer 2, and generates an up signal when the phase of the reference input signal is late. The up / down counter 4 is
The count value held is incremented by 1 in response to the up signal UP, and the count value is decremented by 1 in response to the down signal DN. This count value is given to the multiplexer 2 as a switching address signal, and the ring oscillator circuit 1
The number of stages of the delay circuit formed by the inverters is selected according to the count value. When the count value decreases by one, the number of stages of the delay circuit composed of two inverters decreases by one. When the number of stages of the delay circuit decreases, the oscillation frequency of the ring oscillator circuit 1 increases. On the contrary, the count value is 1
When the number of delay circuits increases, the number of stages of the delay circuit increases by one. When the number of stages of the delay circuit increases, the oscillation frequency of the ring oscillator circuit 1 decreases. The digital PLL circuit repeats such an operation to change the oscillation frequency and the phase so as to follow the reference input signal and synchronize the signals. As a result, the output of the digital PLL circuit is stable at the frequency which is synchronized with the reference input signal and which is obtained by multiplying or dividing the frequency of the reference input signal. Such a digital PLL circuit is incorporated in, for example, an LSI and is used when data processing is performed by obtaining an internal clock that is synchronized with an external clock and is a multiple of the external clock.

[0005]

As described above, in the digital PLL circuit using the ring oscillator circuit, the oscillation frequency is set by changing the number of stages of the delay circuit (inverter) of the ring oscillator circuit.

However, when the number of stages of the delay circuit is switched and changed by the multiplexer, glitch, which is pulse noise, may occur in the circulating pulse signal. For example, when the number of stages of the ring oscillator is 5 or more, when this glitch propagates in the ring, apparently double oscillation or triple oscillation is caused. As a result, even if the frequency is slightly changed, the oscillation frequency actually changes twice or more, and the PLL circuit does not operate stably.

Therefore, it is an object of the present invention to provide a PLL circuit whose operation is more stable by eliminating the problem caused by the occurrence of glitches in the ring oscillator when changing the value of the up / down counter. .

[0008]

In order to achieve the above object, a digital PLL circuit of the present invention comprises a ring oscillator for connecting an inverter in a ring shape to circulate a pulse signal, an output signal of the ring oscillator and a reference input signal. And a phase comparator for generating an up / down signal, an up / down counter for increasing / decreasing a holding value according to the up / down signal, and a connecting stage number of the inverter corresponding to the holding value. It is characterized by comprising a switch means and a pulse removing circuit provided in the ring oscillator to remove a noise pulse.

[0009]

In the ring oscillator circuit of the digital PLL circuit, a pulse removing circuit for preventing passage of a pulse having a pulse width less than the pulse width of a normal pulse signal and having a predetermined delay value or less is provided to remove a noise signal. To do.

As a result, the noise pulse which becomes the disturbance is removed, and only the normal pulse signal circulates in the ring oscillator circuit, and the oscillation frequency of the ring oscillator circuit is stabilized.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and description of such parts will be omitted.

In FIG. 1, a ring oscillator circuit 1 is constructed by connecting an odd number of inverters 11 to 1n in a ring shape so as to circulate a pulse signal. In the ring oscillator circuit 1, two inverters form a one-stage pulse signal delay circuit, and the delay circuit is provided in a desired number of stages. One of the outputs of each delay circuit is selectively selected by the multiplexer 2, and the output of the selected delay circuit becomes the output signal of the multiplexer 2 and is input to the first stage of the ring oscillator circuit 1.

In the above configuration, noise removal is performed in the delay circuit group connected in series in the ring oscillator circuit 1 that circulates the pulse signal, for example, in order to remove a glitch noise pulse before the delay circuit in the first stage. The circuit 5 and the inverter 6 for compensating the inversion of the signal by the noise removing circuit 5.
Is inserted. The other configuration is the same as the conventional configuration.

A configuration example of the noise removing circuit 5 is shown in FIG.
In the figure, the noise removing circuit 5 includes a flip-flop having one input of an input signal and composed of NAND gates 51 and 52, an inverter 53 for transmitting the input signal to the other input end of the flip-flop, and a delay. And a circuit 54. The delay circuit 54 is
It can be configured by an even number of inverters. The delay time is set by the number of inverters.

The operation of the noise removing circuit 5 will be described with reference to the timing chart of the signals of the respective parts shown in FIG. In the input signal A output from the multiplexer 2, the pulse signal portion, for example, "H" in the portion that should originally be "L"
The pulse glitch G is included. The input signal A is inverted by the inverter 53 and further delayed by the delay circuit 54 to become the signal B. The signal B is inverted through the NAND gate 52 to become the signal C. The signals A and B are supplied to the NAND gate 51, and the output signal C becomes "L" only in the section of "H". As a result, the glitch G having a pulse width narrower than the delay time of the signal delay circuit 54 does not appear in the output of the NAND gate 51 and the glitch is removed.
The output signal C is inverted by the inverter 6 and input to the inverter 12, and thereafter, the same operation as in the conventional circuit is performed.

FIG. 4 shows another configuration example of the noise removing circuit. The circuit shown in FIG. 9 corresponds to the circuits 5 and 6 shown in FIG. 1. The signal delay circuit 56 and the AND gate 57 remove the glitch of the "H" pulse, and the signal delay circuit 58 and the OR gate 59 make it "L". "Removing pulse glitches. As a result, both "H" and "L" glitches can be removed.

As described above, by providing the pulse removing circuit for removing the glitch in the ring oscillator circuit 1, it is possible to prevent the malfunction of the digital PLL circuit.

[0018]

As described above, according to the present invention,
When the number of stages of the delay circuit of the ring oscillator is changed, even if a glitch occurs, the pulse elimination circuit removes the glitch, so the problem of double or triple oscillation is eliminated, and the operation of the PLL circuit is stable. To do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital PLL circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a pulse removal circuit.

FIG. 3 is a time chart for explaining the operation of the pulse removal circuit.

FIG. 4 is a circuit diagram showing a configuration example of another pulse removal circuit.

FIG. 5 is a circuit diagram showing a configuration example of a conventional digital PLL circuit.

FIG. 6 is an explanatory diagram illustrating an operation of the ring oscillator.

Claims (2)

[Claims] 1. A ring oscillator that connects an inverter in a ring shape to circulate a pulse signal, a phase comparator that compares the phase of an output signal of the ring oscillator and a reference input signal, and generates an up-down signal, An up / down counter that increases / decreases a hold value according to an up / down signal, a switch unit that selects the number of connection stages of the inverter corresponding to the hold value, and a pulse remover that is provided in the ring oscillator to remove a noise pulse And a digital PLL circuit including the circuit. 2. The digital PLL circuit according to claim 1, wherein the pulse removing circuit removes switching noise generated in the switch means.