JP3132657B2 - Clock switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to a digital communication system for transmitting a digital signal synchronized with an input reference clock even if the phase of the input reference divided clock to be switched is shifted from that of the internal reference divided clock. The present invention relates to a clock switching circuit that suppresses a phase shift of an internal reference clock due to clock switching and generates a good internal reference clock.

[0002]

2. Description of the Related Art Regarding a clock switching circuit in a digital communication system for transmitting a digital signal synchronized with a reference clock, the stability of a reference clock in a device is the most important issue in transmitting a digital signal synchronized with the reference clock. Become. Regarding such a clock switching circuit, for example, Japanese Patent Application Laid-Open No. 09-326787 discloses that the number of clocks of a clock signal and a clock signal in a device is counted by a counting unit at a fixed period, and the number of clocks of the clock signal in the device is determined by a determination unit. And the number of clocks of a clock signal having a constant period are compared, and a clock signal having the same comparison result is output to the phase comparison unit selected by the selection unit.

Further, Japanese Patent Application Laid-Open No. 08-85803 has N phase detectors and a phase compensating circuit, and the phases of N input reference clocks are adjusted based on one reference input clock. It is disclosed that the clock switching circuit performs switching for clock selection later. Further, one of the clocks is delayed by a delay circuit based on the phase difference between a plurality of clocks having the same frequency, and a delayed clock or a non-delayed clock is selected by a clock switching circuit. It discloses that the selected clock is divided by 1 / N.
JP-A-07-170584 discloses a clock switching circuit for suppressing a phase shift of a reference clock in a device.
It is disclosed that the frequency divider is reset to a reset pulse from a reset pulse generator in order to match the phases of a plurality of input reference frequency-divided clocks and the internal reference frequency-divided clock.

In a clock switching circuit applied to a digital communication system for transmitting a digital signal synchronized with a reference clock as described above, the reference clock in the device is usually a reference clock selected from a plurality of input reference clocks. The clock of the voltage controlled oscillator is used in synchronization with the clock. When the input reference clock is switched, there is a phase difference between the input reference clock to be switched and the internal reference clock, and there is a phase fluctuation of the internal reference clock when the clock is switched. Therefore, even when the input reference clock is switched, it is necessary to output a stable internal reference clock with suppressed phase fluctuation.

FIG. 5 is a block diagram showing a configuration of an example of a conventional clock switching circuit. In FIG. 5, the first input reference clock has a frequency f1 in the first frequency dividing circuit 2.
To f0, and the frequency of the second input reference clock is divided from f2 to f0 in the second frequency dividing circuit 3. The clocks divided by the first frequency dividing circuit 2 and the second frequency dividing circuit 3 are input to the switching circuit 4, and the switching circuit 4 determines whether the clock is a divided clock of the first input reference clock by a clock switching signal,
The divided clock of the second input reference clock is selected and output.

The frequency-divided clock selected by the switching circuit 4 is input to a phase comparator 5, and a frequency-divided clock of the internal reference clock is output from a third frequency divider 7 that divides the internal reference clock from f3 to f0. It is input to the phase comparator 5, and the phase comparator 5 outputs a phase difference signal according to the phase difference between the input reference frequency-divided clock and the internal reference frequency-divided clock. The voltage controlled oscillator 6 outputs a clock having a frequency corresponding to the phase difference signal from the phase comparator 5 to output a clock synchronized with the frequency of the input reference clock, and supplies this to the device as a device internal reference clock. I do.

[0007]

Here, when switching the input reference clock, there is an uncertainty in the phase between the input reference divided clock to be switched and the internal reference divided clock. There is a problem that when the reference frequency-divided clock is switched, a phase shift occurs between the internal reference clock output from the voltage controlled oscillator 6. Due to the above problems, when a clock having phase uncertainty is switched, the stability of the internal reference clock is impaired in the conventional clock switching circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem. When switching an input reference clock, the phase of the input reference divided clock to be switched is changed to the phase of the internal reference divided clock. It is an object of the present invention to provide a clock switching circuit that can suppress the phase shift of the internal reference clock due to input reference clock switching by switching after the adjustment, and can generate a good internal reference clock.

[0009]

In order to solve the above-mentioned problems, the present invention is to continuously output a predetermined first input reference clock of a plurality of input reference clocks to a first frequency dividing circuit, At least one of the second input reference clocks is input to the corresponding second frequency divider circuit,
A clock control circuit for stopping the output of the second input reference clock to the second frequency dividing circuit when the count value of each of the second frequency dividing circuits becomes "0"; and dividing the frequency by the first frequency dividing circuit. A switching circuit for selecting one of the first input reference clock to be outputted and the second input reference clock to be divided and outputted by the second divider circuit, and a clock obtained by dividing the internal reference clock And the phase of the divided clock of the first input reference clock or the phase of the divided clock of the second input reference clock, and then the division of the first input reference clock to the switching circuit. A switching signal control circuit for switching to either the selected clock or the divided clock of the second input reference clock; and the first input reference clock or the 2 input reference clock phase and the third
A phase comparator for comparing the phase of the internal reference clock divided by the frequency dividing circuit and outputting a phase difference signal in accordance with the phase difference, and the selection by the phase difference signal output from the phase comparator A voltage-controlled oscillator that outputs the internal reference clock synchronized with the phase of the first input reference clock or the second input reference clock.

According to the present invention, when the first input reference clock is selected, the clock control circuit outputs the first input reference clock to the first frequency dividing circuit as it is, and the second input reference clock outputs the second frequency divided. When the clock is output to the circuit and the count value of the second frequency divider becomes “0”, the clock control circuit stops outputting the second input reference clock to the frequency divider. Conversely, when the second input reference clock is selected, the clock control circuit outputs the second input reference clock to the second frequency divider, outputs the first input reference clock to the first frequency divider, When the count value of the 1 divider circuit becomes “0”, the clock control circuit stops outputting the first input reference clock to the first divider circuit.

A third frequency dividing circuit for dividing either the first input reference clock output from the first frequency dividing circuit or the second input reference clock output from the second frequency dividing circuit and the internal reference clock is provided. When both of them become "0", the phase is selected by the switching circuit and output from the phase comparator under the control of the switching signal control. The phase comparator compares the phase of the first input reference clock or the second input reference clock selected and divided by the switching circuit with the third input reference clock.
It compares the phase of the internal reference clock divided by the frequency dividing circuit with the phase and outputs the phase difference signal to the voltage controlled oscillator. The voltage controlled oscillator outputs a clock synchronized with the phase of the first input reference clock or the second input reference clock selected by the phase difference signal as the internal reference clock.

[0012]

Next, an embodiment of a clock switching circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment according to the present invention. In FIG. 1, the same parts as those of the conventional clock switching circuit shown in FIG. According to the present invention, a plurality of input reference clocks can be input to the clock control circuit.
The embodiment exemplifies a case where a first input reference clock and a second input reference clock are input as input reference clocks for simplification of description.

In FIG. 1, a first frequency dividing circuit 2 and a second frequency dividing circuit 3 are provided corresponding to a first input reference clock and a second input reference clock input to a clock control circuit 1, respectively. . When the first input reference clock is selected by the clock control circuit 1, the selected first input reference clock is output to the first frequency dividing circuit 2 as it is, and the other input reference clocks, that is, the second input reference clock are used. The clock is output to the corresponding second frequency dividing circuit 3, and when the count of the second frequency dividing circuit 3 becomes "0", the output of the second input reference clock is stopped and the frequency division count value "0" is held. Like that.

Conversely, when the second input reference clock is selected, the selected second input reference clock is output to the second frequency divider 3 as it is, and the other input reference clocks are output. That is, the first input reference clock is output to the corresponding first frequency divider 2 and the first frequency divider 2
Is stopped, the output of the first input reference clock is stopped and the frequency division count value "0" is held. The selection of the output of the first input reference clock and the second input reference clock to the first frequency dividing circuit 2 and the second frequency dividing circuit 3 by the clock control circuit 1 depends on the output from the clock switching signal and the switching signal control circuit 8. Switching is performed according to the signal of the comparison result to be performed.

The outputs of the first frequency dividing circuit 2 and the second frequency dividing circuit 3 are output to a switching circuit 4, a clock control circuit 1, and a switching signal control circuit 8. In response to the switching signal from the switching signal control circuit 8, the switching circuit 4 outputs the first input reference clock divided by the first frequency divider 2 and the second input reference clock divided by the second frequency divider 3. Is switched and selected and output to the phase comparator 5. The phase comparator 5 outputs one of the phase of the first input reference clock and the phase of the second input reference clock selected by the switching circuit 4 and the internal reference clock divided by the third frequency divider 7. And outputs a phase difference signal corresponding to the phase difference to the voltage controlled oscillator 6.

The voltage controlled oscillator 6 outputs a clock synchronized with the phase of the selected first input reference clock or the second input reference clock based on the phase difference signal, and a part of the clock is output from the third frequency dividing circuit 7. And to the switching signal control circuit 8. This clock is used as an internal reference clock. With this configuration,
Even when there is a phase difference between the clock divided by the third divider 7 of the internal reference clock and the divided clock of the first input reference clock or the divided second input clock. The phase of the divided first input reference clock or the second input reference clock to be switched is adjusted to the phase of the internal reference clock divided by the third frequency dividing circuit 7, and then the first input reference clock is changed. Since the clock or the second input reference clock is switched, a phase shift of the internal reference clock can be prevented. In addition, the corresponding first input reference clock or second input reference clock of the unselected first input reference clock or second input reference clock to the first frequency dividing circuit 2 or the second frequency dividing circuit 3 of the second input reference clock. Since the supply is stopped, power consumption is suppressed.

Next, the internal configuration of the clock control circuit 1 will be described with reference to FIG. FIG. 2 is a block diagram showing the internal configuration of the clock control circuit 1. This figure 2
, The first input reference clock is input to a first input terminal of a two-input AND gate 25. The second input reference clock is the first input of the two-input AND gate 29.
It is designed to be input to the input terminal. The clock switching signal is input to a first input terminal of a two-input AND gate 23 and a first input terminal of a two-input AND gate 26, and also passed through an inverter 21 to a two-input AND gate 27.
And a second input terminal of a two-input AND gate 22.

The second input terminal of the AND gate 23 has a first input terminal.
When the frequency dividing circuit 2 reaches the count value “0”, it detects the count value and outputs a first reference clock frequency dividing counter “0” detection signal output from the first frequency dividing circuit 2. The output of the AND gate 23 is supplied to a reset input terminal R of a flip-flop circuit (hereinafter referred to as FF) 24. The signal of the comparison result output from the switching signal control circuit 8 is connected to the first input terminal of the AND gate 22,
The signal is input to a second input terminal of the AND gate 26.

The output of the AND gate 22 is input to the set input terminal S of the FF 24. This FF2
The fourth output terminal Q is output to the second input terminal of the AND gate 25. AND gate 25 uses this FF2
The output (first reference clock) is sent to the first frequency dividing circuit 2 by taking the AND logic of the output of the fourth reference clock and the first input reference clock. AND gate 22, 2 above
3, 25 and the FF 24 constitute a first input reference clock extracting means.

The AND gate 26 takes the AND logic of the clock switching signal and the comparison result signal output from the switching signal control circuit 8 and sends it to the set input terminal S of the FF 28. Further, when the count value of the second frequency dividing circuit 3 becomes “0”, the second reference clock frequency dividing counter “0” detection signal output from the second frequency dividing circuit 3 becomes the second level.
The signal is input from the frequency dividing circuit 3 to the second input terminal of the AND gate 27. The AND gate 27 takes the AND logic of the output of the inverter 21 and the detection signal of the second reference clock dividing counter “0”, and outputs the output to the FF 28
Is transmitted to the reset input terminal R. The output terminal Q of the FF 28 is sent to the second input terminal of the AND gate 29. AND gate 29 is the second
The output (second reference clock) is sent to the second frequency dividing circuit 3 by taking the AND logic of the input reference clock and the output of the output terminal Q of the FF 28. AND gate 26,
27, 29 and the FF 28 constitute a second input reference clock extracting means.

Next, a detailed internal configuration of the switching signal control circuit 8 of FIG. 1 will be described with reference to FIG. FIG. 3 is a block diagram showing the internal configuration of the switching signal control circuit 8. In FIG. 3, a first input terminal of a two-input AND gate 42 has an internal reference lock frequency obtained by dividing the internal reference clock output from the voltage controlled oscillator 6 of FIG. A counter “0” detection signal is input. Further, the selector 41 has a first reference clock,
That is, the first reference clock division counter “0” detection signal of the first frequency division circuit 2 is input, and the second reference clock division counter “0” detection of the second frequency division circuit 3 is detected. A signal is input.

The output of the selector 41 is inputted to the second input terminal of the AND gate 42. The signal of the comparison result from the output terminal of the AND gate 42 is F
It is sent to the set input terminal S of F43 and the clock control circuit 1 of FIG. Thus, the selector 41
And AND gate 42 constitute a comparison result output means. A clock switching signal is input to the selector 41 and the data input terminal D of the D-type FF 45. D-type FFs 45 to 48 are cascade-connected, and a clock input terminal C of each of the FFs 45 to 48 is configured to receive an internal reference clock. FF
The output signal output from the output terminal Q of the 45 is a 2-input EX
The signal is input to the first input terminal of the OR circuit 44 and is input to the data input terminal D of the FF 46.

The output signal output from the output terminal Q of the FF 46 is input to the second input terminal of the EX-OR circuit 44 and the data input terminal D of the FF 47. EX-O
The output of the R circuit 44 is input to the reset input terminal R of the FF 43. Set input terminal S of FF43
The signal of the comparison result output from the AND gate 42 is sent to the clock control circuit 1 in FIG. The output terminal Q of the FF 47 is input to the data input terminal D of the FF 48.

The enable input terminal EN of the FF 48 has a FF
An output signal output from the output terminal Q of the output terminal 43 is input. A switching signal is sent from the output terminal Q of the FF 48 to the switching circuit 4 in FIG. The FFs 43, 45 to 48, and the EX-OR circuit 44 constitute a switching signal holding unit.

Next, the operation of the first embodiment configured as described above will be described with reference to FIGS. FIG. 4 is a time chart for explaining the operation. First, the principle operation of the first embodiment with the configuration of the block diagram of FIG. 1 will be described. In the embodiment shown in FIG. 1, a case where a clock of a voltage controlled oscillator is synchronized with a selected input reference clock among a plurality of input reference clocks, and a clock output from the voltage controlled oscillator is used as an internal reference clock. An example is shown. The clock control circuit 1 receives a first input reference clock and a second input reference clock, outputs the first input reference clock to the first frequency divider 2, and outputs the second input reference clock to the second frequency divider 3
Output to

The clock control circuit 1 of FIG. 1 has a configuration as shown in FIG. 2, and the selected one, that is, the first input reference clock is output to the first frequency dividing circuit 2 as it is. The second input reference clock is supplied to the second frequency dividing circuit 3 until the count value of the second frequency dividing circuit 3 becomes “0”.
When the frequency division count of the second frequency divider 3 becomes “0”, the output of the second input reference clock is stopped and the count value of the second frequency divider 3 is held at “0”. . When the second input reference clock is selected, the second input reference clock is output to the second frequency divider 3 as it is, the first input reference clock is output to the first frequency divider 2 and the first input reference clock is output. When the count value of the frequency divider 2 becomes “0”, the output of the first input reference clock to the first frequency divider 2 is stopped. The switching circuit 4 selects either the first input reference frequency-divided clock from the first frequency divider 2 or the second input reference clock from the second frequency divider 3 based on a switching signal from the switching signal control circuit 8. And outputs it to the phase comparator 5.

In the phase comparator 5, the first input reference clock selected from the switching circuit 4 is divided by the first divider 2 and the second input reference clock is divided by the second divider 3. Of the selected clock and the clock obtained by dividing the reference clock in the device by the third frequency divider 7, and outputs a phase difference signal corresponding to the phase difference between the two clocks. Output to the voltage controlled oscillator 6. The voltage controlled oscillator 6 outputs a clock synchronized with the selected first input reference clock or the second input reference clock to the phase comparator 5.
The third frequency dividing circuit 7 divides the frequency of the internal reference clock and outputs it to the phase comparator 5 as described above.

Further, since the switching signal control circuit 8 of FIG. 1 is configured as shown in FIG. 3, the first reference clock frequency dividing counter “0” detection signal of the first frequency dividing circuit 2 by the clock switching signal, Alternatively, the detection signal of the second reference clock frequency dividing counter “0” of the second frequency dividing circuit 3 is supplied to the selector 4
1, the detection signal of the selected count “0”,
That is, the detection signal of the first reference clock division counter “0” or the detection signal of the second reference clock division counter “0” and the reference clock in the device are connected to the AND gate 42 of FIG.
And AND logic. The internal reference clock dividing counter “0” detection signal from the third frequency dividing circuit 7 for dividing the internal reference clock and the first reference clock dividing counter “0” detection signal selected by the selector 41, or When both of the two reference clock frequency division counter “0” detection signals reach count “0”, the first input reference clock is switched to the first frequency dividing circuit 2 and the second input reference clock to the second frequency dividing circuit 3. The clock supply is restarted and the switching circuit 4
To switch the first input reference clock and the second input reference clock.

Next, the operation of the first embodiment shown in FIG. 1 will be described in more detail with reference to the time chart of FIG. Now, consider a case where the first input reference clock and the second input reference clock are input to the clock control circuit 1 and the first input reference clock is selected as the internal reference clock by the switching circuit 4. Here, the frequency division number of the frequency division circuit of the first input reference clock, the second input reference clock, and the internal reference clock is 256. The first input reference clock and the second input reference clock are controlled by inputting a clock switching signal and a comparison result from the switching signal control circuit 8 to the clock control circuit 1 as a control signal, and respectively control the first frequency dividing circuit 2 , To the second frequency dividing circuit 3.

The count "0" detection signal from the first frequency divider 2 is used as a first input reference clock frequency divider counter "0" detection signal, and the count "0" from the second frequency divider 3 is used.
The clock control circuit 1 and the switching signal control circuit 8 use the detection signal as a second input reference clock division counter “0” detection signal.
When the frequency division count of the first frequency dividing circuit 2 and the second frequency dividing circuit 3 is “0”, the detection signals of the first frequency dividing circuit 2 and the second frequency dividing circuit 3 are “1”, respectively. Become. In the switching signal control circuit 8, the selector 41 uses the clock switching signal to generate a first reference clock frequency division counter “0” detection signal,
Either the second reference clock division counter “0” detection signal is selected, and the selected first reference clock division counter “0” detection signal or the second reference clock division counter “0” detection is selected. Third signal and internal reference clock
The comparison result signal detected by the AND gate 42 that both the internal reference clock frequency division counter “0” detection signal divided by the frequency division circuit is “0” is transmitted to the clock control circuit 1.

Here, the switching circuit 4 uses the first input reference clock when the clock switching signal from the switching signal control circuit 8 is "1" and the second input reference clock when the clock switching signal is "0".
It is assumed that the input reference clock is selected, and the frequency division counts of the first frequency divider 2, the second frequency divider 3, and the third frequency divider 7 are counted from 0 to 255 as shown in FIG. , Again counting from 0. 4 (H), FIG. 4 (J), and FIG. 4 respectively show frequency-divided clocks generated by the first frequency divider 2, the second frequency divider 3, and the third frequency divider 7.
As shown in (L), each frequency division count is 0 to 1
The frequency is divided so as to be “0” up to 27 and “1” from 128 to 255.

In FIG. 4, at time t1, as shown in FIG. 4A, the first input reference clock is selected as the internal reference clock, indicating a stable state. At time t2 in FIG. 4, as shown in FIG. 4B, a clock switching signal for switching the internal reference clock from the first input reference clock to the second input reference clock is input. The clock switching signal is delayed by FF 45 and FF 46 in FIG. 3 showing the internal configuration of the switching signal control circuit 8 and the change of the switching signal is subjected to exclusive logic by the EX-OR circuit 44 in FIG. 3 as shown in FIG. Fig. 3 shows the sum of the output 1-bit signals.
Input to the reset input terminal R of the FF 43 of
As shown in FIG. 4 (E), the output of the FF 43 in FIG. 3 becomes “0”, and the FF 48 in FIG. 3 enters the hold state with the first input reference clock selected.

The output of the selector 41 shown in FIG. 3 switches from the "0" detection signal at the first reference clock division counter to the "0" detection signal at the second reference clock division counter. Here, if the in-device reference clock frequency division counter “0” detection signal from the third frequency division circuit 7 matches the second reference clock frequency division counter “0” detection signal, the phase is in a state of coincidence. When the clock switching signal is input, they do not match because they are in an asynchronous state. However, since the second reference clock frequency division counter “0” detection signal is stopped in the state of “0”, it is necessary for the third frequency divider circuit 7 of the internal reference clock to count forward to “0”. Wait, time t
3, when the count becomes "0", the AND gate 42 of FIG. 3 performs the AND logic of the second reference clock division counter "0" detection signal and the internal reference clock division counter "0" detection signal. Accordingly, both counts “0” are detected, and as shown in FIG. 4 (D), “1” in a coincident state is output and sent to the clock control circuit 1 as a comparison result signal.

The comparison result signal is input to the set terminal of the FF 28 shown in FIG. That is, the comparison result signal is input to the second input terminal of the AND gate 26, and the clock switching signal is input to the first input terminal of the AND gate 26.
The output of the FF 28 in FIG. 2 becomes "1" by taking AND logic of these two inputs and outputting the result to the set input terminal S of the FF 28. As a result, the output “1” of the FF 28 is input from the output terminal Q of the FF 28 to the second input terminal of the AND gate 29. The second input terminal of the AND gate 29 has a second input terminal.
Since the input reference clock is input, the AND gate 29 takes the AND logic of these two signals to generate the second
The input reference clock is output to the second frequency dividing circuit 3.

Second frequency divider circuit The second input reference clock is output from the output terminal of the AND gate 29 which outputs the signal to FIG.
As shown in FIG. 4 (K), the second input reference clock frequency dividing counter of the second frequency dividing circuit 3 starts operating, and as shown in FIG. 4 (F), the switching signal to the switching circuit 4 is switched signal control. It is output from the output terminal of the FF 48 of the circuit 8. As a result, the switching circuit 4 selects the second input reference frequency-divided clock and outputs it to the phase comparator 5. The phase comparator 5 compares the phase of the second input reference frequency-divided clock with the internal reference frequency-divided clock obtained by dividing the internal device reference clock by the third frequency dividing circuit 7, and as a result of the comparison, the two are compared. Switching is performed in a state where the phases match, thereby preventing the phase of the internal reference clock from fluctuating greatly.

At time t3, the first frequency dividing circuit 2 that divides the first input reference clock detects "0", so that the first reference clock counter "0" detection signal is sent to the clock control circuit 1. The clock signal is transmitted to the second input terminal of the AND gate 23 of FIG. 2 and the clock switching signal is input to the first input terminal of the AND gate 23. The output of the AND gate 23 is input to the reset input terminal R of the FF 24. Therefore, the output of the FF 24 becomes “0”,
Since the transmission of the first input reference clock to the first frequency dividing circuit 2 is stopped by the AND gate 25 of FIG.
As shown in (I), the frequency division count of the first frequency division circuit 2 of the first input reference clock keeps the state of “0”.

The same operation is performed when switching from the second input reference clock to the first input reference clock. That is, when the phase of the clock of the second frequency dividing circuit 3 and the phase of the clock of the third frequency dividing circuit 7 match, the third frequency dividing circuit 7 detects the internal reference clock frequency dividing counter “0” and outputs “1”. The result of comparison with a signal input to the first input terminal of the AND gate 42 and detected by the first frequency divider 2 selected by the selector 41 and detected by the second frequency divider counter “0” by the first frequency divider 2 is shown. 2 and input to the first input terminal of the AND gate 22. A clock switching signal inverted by the inverter 21 is input to a second input terminal of the AND gate 22, and the AND gate 25 outputs an output signal from the output terminal Q of the FF 24 to the first input terminal.
By outputting the input reference clock to the first frequency divider 2, it is possible to switch to the second input reference clock.

As described above, in the first embodiment, the phase fluctuation at the time of clock switching can be minimized, and the stability of the internal reference clock can be increased. In addition, since clock input of the unselected input reference clock to the frequency divider is prohibited, the power consumption of the frequency divider can be reduced. The present invention is not limited to the first embodiment. For example, the present invention can be similarly applied to a case where there are three or more input reference clocks.

[0039]

As described above, according to the present invention, when the input reference clock is switched, the phase of the selected input reference divided clock is adjusted to the phase of the internal reference divided clock before switching the clock. Since the clock is switched in the circuit, the phase shift of the internal reference clock output from the voltage controlled oscillator due to the clock switching can be suppressed, and a good internal reference clock can be generated. Since the clock input to the frequency dividing circuit of the input reference clock is stopped, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a clock switching circuit according to the present invention;

FIG. 2 is a block diagram showing a detailed internal configuration of a clock control circuit in the clock switching circuit of FIG. 1;

FIG. 3 is a block diagram showing a detailed internal configuration of a switching signal control circuit in the clock switching circuit of FIG. 1;

FIG. 4 is a timing chart for explaining the operation of the clock switching circuit of FIG. 1;

FIG. 5 is a block diagram showing a configuration of a conventional clock switching circuit.

[Explanation of symbols]

1 ... clock control circuit, 2 ... first frequency divider circuit, 3 ...
2nd frequency dividing circuit, 4 switching circuit, 5 phase comparator, 6
... Voltage controlled oscillator, 7... Third frequency divider circuit, 8... Switching signal control circuit, 21.
5, 26, 27, 29, 42 ... AND gate, 24,
28, 43, 45 to 48: flip-flop circuit (FF), 41: selector, 44: EX-OR circuit circuit.

Claims (8)

(57) [Claims] 1. A method of continuously outputting a predetermined first input reference clock of a plurality of input reference clocks to a first frequency dividing circuit, and at least one other second input reference clock corresponding to a corresponding second input reference clock. A clock control circuit for inputting to the frequency dividing circuit and stopping the output of the second input reference clock to the second frequency dividing circuit when the count value of each of the second frequency dividing circuits becomes “0”; A switching circuit for selecting one of the first input reference clock divided and output by the frequency dividing circuit and the second input reference clock divided and output by the second frequency dividing circuit; After the phase of the clock obtained by dividing the reference clock and the phase of the divided clock of the first input reference clock or the phase of the divided clock of the second input reference clock match, A switching signal control circuit for switching to either a frequency-divided clock of the input reference clock or a frequency-divided clock of the second input reference clock; and the first input reference clock or the second input selected by the switching circuit A phase comparator that compares the phase of the reference clock with the phase of the internal reference clock divided by the third frequency divider and outputs a phase difference signal according to the phase difference; A voltage-controlled oscillator that outputs the internal reference clock synchronized with the phase of the first input reference clock or the second input reference clock selected by the phase difference signal. . 2. The clock control circuit according to claim 1, wherein three or more input reference clocks are input.
A clock switching circuit as described. 3. The switching signal control circuit according to claim 1, wherein the first input reference clock is divided by a first frequency dividing circuit by "0".
The second frequency divider of the the detection signal the second input reference clock frequency dividing count "0" by the third frequency divider circuit of the internal reference clock and either the detection signal divider counter "0" detection signal and the Comparison result output means for outputting, as a comparison result, a clock frequency-divided by the first frequency divider circuit or the second frequency-divider circuit which coincides with the clock signal to the clock control circuit; A clock switching signal for switching to one of a reference clock and the second input reference clock is delayed so that the comparison result output means selects the clock divided by the first frequency divider or the second frequency divider. 2. The clock switching circuit according to claim 1, further comprising: switching signal holding means for holding and outputting a switching signal to the switching circuit. 4. The comparison result output means outputs a first reference clock division counter “0” detection signal output from the first frequency division circuit in response to the clock switching signal and a second detection signal output from the second frequency division circuit. A selector for selecting one of the two reference clock division counter “0” detection signals, and a first reference clock division counter “0” output from the selector
The AND logic of either the detection signal or the second reference clock division counter “0” detection signal and the internal reference clock division counter “0” detection signal output from the third division circuit is calculated. 4. The clock switching circuit according to claim 3, further comprising: a first AND gate that outputs a comparison signal to the clock control circuit. 5. The switching signal holding means outputs a switching signal to the switching circuit by a first flip-flop circuit set by an output of the first AND gate and an output of the first flip-flop circuit. The second flip
An exclusive OR of a flip-flop circuit, a plurality of D-type flip-flop circuits connected in cascade to sequentially delay the clock switching signal, and an output signal of a predetermined stage of the plurality of flip-flop circuits EX-OR causing the second flip-flop circuit to hold the selected state of the selected first input reference clock or the second input reference clock by resetting the first flip-flop circuit The clock switching circuit according to claim 3, further comprising a circuit. 6. The clock control circuit, wherein the phase of the clock obtained by dividing the second input reference clock by the second frequency divider and the internal reference clock are divided by the third frequency divider. First reference clock extracting means for outputting the first input reference clock to the first frequency dividing circuit when the phases of the clocks coincide with each other; and a phase of the clock of the first frequency dividing circuit and a clock of the third frequency dividing circuit. 2. The clock switching circuit according to claim 1, further comprising: a second input reference clock extracting unit that outputs the second input reference clock to the second frequency dividing circuit when the phases match. Wherein said first input reference clock Extraction means,
A second AND gate for taking an AND logic of the inverted signal of the comparison result and said clock switching signal output from the switching signal control circuit, a third flip-flop circuit which is set by the second AND gate, said first A third AND gate for performing AND logic between one input reference clock and the output of the third flip-flop circuit to output the first input reference clock to the first frequency divider circuit; A fourth AND gate for resetting the third flip-flop circuit by performing AND logic with a first input reference clock frequency dividing counter “0” detection signal output from the 1 frequency dividing circuit. The clock switching circuit according to claim 6. 8. The second input reference clock extracting means,
A fifth AND gate for performing an AND logic between a comparison result output from the switching signal control circuit and the clock switching control signal, a fourth flip-flop circuit set by an output of the fifth AND gate, A sixth AND gate for performing an AND logic operation on the output of the 4-flip-flop circuit and the second input reference clock and outputting the second input reference clock to the second frequency divider; and an inverted signal of the clock switching signal And a seventh AND gate for resetting the fourth flip-flop circuit by ANDing the detection signal of the second input reference frequency division counter “0” output by the second frequency division circuit with the detection signal. The clock switching circuit according to claim 6, wherein