JPH09127201A - Method for verifying field programmable gate array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To verify the operating speed of a developed anti-fuse type field programmable gate array (FPGA) accurately by performing delayed simulation again based on the recalculated delayed value of each signal after resetting the circuit constants. SOLUTION: At the measuring/resetting stage, anti-fuse conduction resistance is measured for an FPGA programmed based on design information. Each resistance thus measured is stored in the memory area of an EWS or the like and reset as the circuit constant of a delayed value calculating means. At the stage for recalculating delayed value, delayed value of each signal pulse of the circuit is recalculated from the reset circuit constant. At the stage for performing delayed simulation again, delayed simulation is performed again based on a circuit diagram, test pattern information, and the delayed value of each signal pulse. According to the method, operating speed and operating frequency of a developed anti-fuse type FPGA can be verified accurately regardless of fluctuation in the conduction resistance of anti-fuse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying a field programmable gate array (hereinafter referred to as an FPGA), and more particularly to a method for verifying an anti-fuse type FPGA.
The present invention relates to a PGA verification method.

[0002]

2. Description of the Related Art A fuse that conducts after programming, that is, an anti-fuse type FPGA, allows the customer to program the element arrangement and wiring of a logic-designed circuit. It is used for specification confirmation and product trial production at the time of product development, and for small-scale production at the start of mass production. In order to further shorten the anti-fuse type FPGA development TAT, general EWS (Eng)
innering Work Station), PC
(Personal Computer) and the like, and a logic simulation, a layout and wiring design of circuit elements, and a delay simulation are performed based on the design information, and are verified before programming. Thereafter, programming is performed using a writing device or the like, and a low-speed function test is performed.

The EWS and the like used at this time generally include support means for supporting creation of circuit diagram and test pattern information, logic simulation means for performing a logic simulation based on circuit diagram and test pattern information, and circuit diagram information. And a delay value calculating means for calculating each signal path delay value of the circuit from a circuit constant of the circuit element, and a delay simulation means for performing delay simulation based on each signal path delay value. ing. The writing device or the like also includes programming means for inputting verified design information and programming an antifuse of the FPGA, and test means for performing a low-speed function test on a circuit formed on the FPGA by programming.

FIG. 2 shows an antifuse type FP showing a conventional FPGA verification method using the EWS, the writing device and the like.
It is a flowchart of the development flow by GA. Referring to FIG. 2, this FPGA development flow includes a logic design step 1
1, a logic simulation step 12, a placement and routing step 13, a delay value calculation step 14, a delay simulation step 15, a programming step 16, and a low-speed function test step 17.

A description will be given in accordance with the order of steps in the FPGA development flow. First, a logic design step 11 is a step in which a customer performs a logic design of an FPGA based on specifications, and information of a circuit diagram and test patterns is provided by supporting means such as EWS. create.

The logic simulation step 12 is a verification step of the logic design step 11, and performs logic simulation by logic simulation means such as EWS based on the circuit diagram and test pattern information created in the logic design step 11. In the case of NG, the process returns to the logic design step 11.

The placement and routing step 13 is a step of placing and routing circuit elements by placement and routing means such as EWS based on the circuit diagram and information verified in the logic simulation step 12.

The delay value calculation step 14 and the delay simulation step 15 are verification steps of the placement and routing step 13. The delay value calculating step 14 calculates each signal path delay value of the circuit from the circuit constant of the circuit element by delay value calculating means such as EWS, and the delay simulation step 15 includes information of the circuit diagram and the test pattern and each signal path delay value. , Delay simulation is performed by delay simulation means such as EWS. N
In the case of G, the process returns to the placement and routing step 13 or the logic design step 11.

The programming step 16 is a step of programming the anti-fuse of the FPGA by programming means such as a writing device based on the placement and wiring design information verified in the delay simulation step 15. The programmed anti-fuse conducts and constitutes a circuit designed and verified in steps 11 to 15.

Low-speed function test step 17
Is a verification step of the FPGA programmed in the programming step 16. Generally, on the customer side, a low-speed function test is performed by a test means such as a writing device on the basis of input design information to determine the quality of the programmed FPGA.

In the delay verification method shown in the development flow using the FPGA, when calculating each signal path delay value of the circuit, a constant value of the worst case and the best case is usually prepared as the characteristic value of the transistor of the FPGA. , And externally designated by selecting one of them. Further, a constant value is uniformly set in the chip as a conduction resistance value after programming the antifuse of the FPGA.

[0012]

SUMMARY OF THE INVENTION An anti-fuse type F
The operating speed of PGA is based on transistor, anti-fuse,
It is determined by characteristics such as wiring. In particular, the transistor characteristics are different for each chip, and the conduction resistance after programming the anti-fuse also differs depending on the position of each chip and each anti-fuse, so that the distribution of the operating speed of the anti-fuse type FPGA is expanded. . However, the FPG included in the development flow by the conventional FPGA
In the verification method A, since a constant value is set as the characteristic value of the transistor and the antifuse of the FPGA, the probability that the delay simulation result before programming does not necessarily guarantee the operation speed of the programmed FPGA increases.

Although the connection function of the circuit can be confirmed by a low-speed function test after programming, it cannot be confirmed whether or not the circuit operates at a desired operating frequency. It was necessary to use a high-speed function tester. However, when a chip is mounted on a board for evaluation, the discovery of defects is delayed, leading to an increase in the development period and development costs. In addition, since the high-speed function tester is expensive, the development investment cost for the customer is large. .

Accordingly, an object of the present invention is to shorten the development period and reduce the development cost in a development flow using an anti-fuse type FPGA.

[0015]

Therefore, the present invention provides a logic simulation step for performing a logic simulation based on information of a logic designed circuit diagram and a test pattern, and a circuit element arranged and wired based on the information of the circuit diagram. In a field programmable gate array verification method, comprising: a delay value calculating step of calculating each signal path delay value of the circuit from a circuit constant; and a delay simulation step of performing a delay simulation based on the signal path delay values. A measuring / resetting step of measuring the conduction resistance of the antifuse and resetting the circuit constant after programming the field programmable gate array having a fuse; and a delay value for recalculating the signal path delay values after the measuring step. A calculation step includes a re-delay simulation step of re-delay simulation on the basis of each signal path delay values.

Further, in order to further increase the verification accuracy, the measuring / resetting step measures the characteristics of the transistors constituting the field programmable gate array and the conduction resistance and resets the circuit constant.

[0017]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart of a development flow of an antifuse type FPGA showing an embodiment of an FPGA verification method of the present invention. Referring to FIG. 1, the FP of this embodiment
The GA verification method includes a logic simulation step 12,
Along with the verification step included in the conventional FPGA verification method shown in FIG. 2 including the delay value calculation step 14, the delay simulation step 15, and the low-speed function test step 17, after programming the FPGA having an anti-fuse that becomes conductive by programming. ,
A measurement / reset step 21 for measuring the conduction resistance of the antifuse and resetting the circuit constant, and a delay value recalculation step 2 for recalculating each signal path delay value after this measurement step.
2 and a re-delay simulation step 23 for performing delay simulation again based on each signal path delay value.

The conventional anti-fuse type FP shown in FIG.
The same steps as those of the development flow by the GA are not described repeatedly, and the measurement / resetting step 21, the delay value recalculation step 22, the redelay simulation step 23
Will be described in detail.

In the measurement / resetting step 21, first, the conduction resistance value of the antifuse of the FPGA programmed based on the design information verified by the logic design and the placement and wiring design is measured by measuring means such as a writing device.
The conduction resistance value of this anti-fuse is determined by applying a voltage to each anti-fuse during programming and measuring the flowing current to determine whether or not the anti-fuse has been programmed. it can. Thereafter, the conduction resistance value of each antifuse is stored in a memory area such as EWS used as a delay value calculating means, and is reset as a circuit constant in the delay value calculating means such as EWS.

The delay value recalculation step 22 and the redelay simulation step 23 are re-verification steps based on the circuit constants measured and reset in the measurement / resetting step 21. The delay value recalculation step 22 is EW
The signal path delay value of the circuit is recalculated from the circuit constants reset by the delay value calculation means such as S. The re-delay simulation step 23 includes the circuit diagram and test pattern information and the re-calculated signal path delay. Based on the value, re-delay simulation is performed by delay simulation means such as EWS. As a result, if the programmed FPGA becomes NG, it is removed as a defective product.

In the development flow of the anti-fuse type FPGA including the above-described FPGA verification method of the present embodiment, after the programming of each FPGA chip, re-delay simulation is performed using the measured value of each anti-fuse conduction resistance in the chip. Therefore, the operation speed and operation frequency of the developed anti-fuse type FPGA can be verified with high accuracy without being affected by the variation of each anti-fuse conduction resistance after programming.

As an embodiment of the FPGA verification method of the present invention, each FP is measured in the measurement / resetting step 21.
After the programming of the GA chip, an example is described in which each antifuse conduction resistance in the chip is measured and reset as a circuit constant in delay value calculation means such as EWS.
At the same time, the transistor characteristics of each FPGA chip can also be measured and reset as circuit constants in delay value calculation means such as EWS. Thereby, the operating speed and operating frequency of the developed anti-fuse type FPGA can be verified with higher accuracy. At this time, the transistor characteristics of each of the FPGA chips are measured at the time of each FPGA chip test before shipment from the factory, and the measured values are recorded in a plurality of antifuses of each FPGA chip.
It is also possible to read out when programming the PGA chip.

[0024]

As described above, the FP according to the present invention
The GA verification method is to measure the antifuse conduction resistance in each chip after programming each FPGA chip and
It is reset as a circuit constant in the delay value calculating means such as S, each signal path delay value of the circuit is recalculated from the reset circuit constant, information of the circuit diagram and the test pattern, and each recalculated signal path delay. Since the re-delay simulation is performed based on the value, the operating speed and operating frequency of the developed anti-fuse type FPGA can be verified with high accuracy without being affected by variations in the anti-fuse conduction resistance after programming.

Further, the ratio of the anti-fuse type FPGA which is determined to be defective after the board is assembled can be suppressed to almost zero, and rework in the development flow using the anti-fuse type FPGA is reduced. And development costs can be reduced.

Further, since the same sort as the high-speed function test can be performed, an expensive high-speed function tester is not required, and there is an effect that the development investment cost for the customer can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart of a development flow showing an embodiment of an FPGA verification method of the present invention.

FIG. 2 is a flowchart of a development flow showing a conventional FPGA verification method.

[Explanation of symbols]

 Reference Signs List 11 logic design step 12 logic simulation step 13 placement and wiring step 14 delay value calculation step 15 delay simulation step 16 programming step 17 low-speed function test step 21 measurement / resetting step 22 delay value recalculation step 23 re-delay simulation step

Claims (2)

[Claims] 1. A logic simulation step of performing a logic simulation based on information of a logic designed circuit diagram and a test pattern, and each signal path delay of the circuit based on circuit constants of circuit elements arranged and wired based on the information of the circuit diagram. A delay value calculating step of calculating a value, and a delay simulation step of performing a delay simulation based on each of the signal path delay values, wherein after programming of the field programmable gate array having an anti-fuse conducting by programming, A measuring / resetting step of measuring the conduction resistance of the antifuse and resetting the circuit constant; a delay value recalculating step of recalculating the signal path delay values after the measuring step; Field programmable gate arrays verification method characterized by comprising a re-delay simulation step of re-delay simulation based on the value, the. 2. The field programmable gate array verification method according to claim 1, wherein said measuring / resetting step measures characteristics of said transistors constituting said field programmable gate array and said conduction resistance and resets said circuit constants. .