JPH087269B2 - Electronic clock - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electronic timepiece having a logic regulation means for performing a logic regulation operation and a step motor drive means.

[Outline of Invention]

The present invention relates to an electronic timepiece having a logical slowing / fastening means for performing a logical slowing / fastening operation and a step motor driving means, and a timing circuit for inputting an output signal of a frequency dividing circuit and an output signal of an input circuit to perform a timing operation, and a timing circuit. As a configuration having step motor driving means for inputting the output signal of (1) and outputting a driving signal for driving the step motor, and start control means for prohibiting the simultaneous operation of the logical slowing / fastening means and the step motor driving means, It is possible to easily avoid the simultaneous operation of the logical slowing / fastening means and the stepping motor driving means, and in particular, the stepping motor driving is performed at an arbitrary timing,
This is a function that makes it possible to easily realize a multifunction electronic timepiece with a logical slowdown / quick movement.

[Conventional technology]

As for the technique of performing a slow operation using a logic circuit, for example, as disclosed in Japanese Patent Laid-Open No. 49-96769, it is known that the output timing of a frequency dividing circuit is changed by an electronic circuit. Has been. These logical slow-and-fast systems are widely used because they are more resistant to time deterioration and temperature change and require less mounting area than the system in which a slow-moving operation is performed by adding a variable capacitor or a variable resistor to the outside. A technique combining a timepiece microprocessor and a logic regulation circuit is disclosed in, for example, Japanese Patent Laid-Open No. 57-
As disclosed in Japanese Unexamined Patent Publication No. 13386, it is known that a micro instruction of a program causes a slow-moving operation at a slow-moving timing of a frequency dividing circuit.

[Problems to be Solved by the Invention]

When adding the logical slowdown / fasten function to the conventional single-function analog electronic timepiece, it is possible to avoid simultaneous operation of both by performing the step motor drive and the logical slowdown / fast operation at different timings in advance. there were.

However, when an analog multifunctional timepiece that drives a step motor at an arbitrary timing is equipped with the logic slowdown / fastening method shown in the prior art, step motor drive and logic slowdown / fast operation timing become a problem. . That is, the logical slowing / quicking operation is normally performed regularly in a cycle of 10 seconds, while the stopwatch and timer operations are performed at arbitrary timing. Therefore, when the operation timings of the both agree with each other, the driving waveform changes due to the logical slowing / quicking operation, and the result that the step motor does not rotate normally occurs. Therefore, a means for efficiently avoiding the simultaneous operation is required. .

[Object of the Invention] An object of the present invention is to utilize the flexibility of program processing,
It is an object of the present invention to provide a logic slow-moving means and a means capable of easily avoiding the simultaneous operation of the stepping motor driving means, and to provide an analog multi-function timepiece with a logic slow-moving and wide range of adaptation.

[Means for solving the problem]

In order to solve the above problems, the present invention provides an electronic timepiece having a logic slowdown / fastening means for performing a slowdown / fastening operation and a step motor drive means, and inputs an output signal of a frequency dividing circuit and an output signal of an input circuit to perform a time counting operation. Timing circuit, a step motor driving means for inputting the output signal of the timing circuit and outputting a driving signal for driving the step motor, and a start control for prohibiting the simultaneous operation of the logical slowing / quickening means and the step motor driving means. As a configuration having the means, the logical slowing-down means and the step motor driving means are avoided to be seated at the same time, and a reliable operation of the step motor is guaranteed.

[Action]

The frequency dividing circuit inputs the output signal of the oscillation circuit and divides the frequency. The input circuit inputs the correction signal. The logic regulation means performs the logic regulation operation by setting or resetting the frequency dividing circuit. The step motor drive means operates according to the output signal of the frequency dividing circuit.

The time counting circuit inputs the output signal of the frequency dividing circuit and the output signal of the input circuit and performs a time counting operation. The step motor drive means inputs the output signal of the clock circuit and outputs a drive signal for driving the step motor. The start control means prohibits the logic slowing down means and the step motor driving means from operating at the same time.

In addition, the electronic timepiece of the present invention, as described below,
Performs an operation that prohibits the simultaneous operation of the logic slowing / fastening means and the step motor driving means.

1) Simultaneous operations can be avoided by detecting the presence / absence of an operation signal of the logic slowing / fastening means when the step motor driving process is performed. Even when the operation signal is generated,
Since the operation time of the logical slowdown is usually a short time, the start delay time can be minimized by the means for waiting the start operation of the step motor until the operation signal stops.

2) Simultaneous operations can be avoided by detecting the presence / absence of an operation signal of the step motor when performing the operation processing of the logical regulation. However, even when the operation signal is generated, it rarely overlaps with the step motor drive in the normal use condition, and even if the logical adjustment operation is not performed, the rate change of the day is affected. If there is not, the operation processing can be simplified by a means for ignoring the logical operation start-up operation.

3) A means for counting the start-up cycle of the logical slowdown and rapid operation, and a stop of the operation signal even when the operation signal is continuously generated, such as an electronic timepiece of a specification in which a high-speed step motor drive is performed for a relatively long time. After that, according to the contents of the count, the daily rate moderateness can be adjusted by the means for correcting the logical moderated activation means.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system block diagram of an electronic timepiece according to the present invention. In the electronic timepiece system in FIG. 1, the operation processing procedure is stored in the ROM 7, and the operation processing procedure of the ROM 7 is decoded by the arithmetic processing circuit 4 and the operation is performed by controlling other peripheral circuits. . With such a system configuration, diversifying consumer needs can be met in a short time only by changing the operation processing procedure of the ROM 7. FIG. 11 shows an embodiment of each operation processing means stored in the ROM 7.

In FIG. 1, the logical regulation means 10 which is a feature of the present invention is shown.
Then, the step motor drive means 20 is operated by the control signal from the arithmetic processing circuit 4. The logical speed-up means 10 is
The step speed is controlled by setting or resetting a specific stage flip-flop of the frequency dividing circuit 2, and the step motor drive means 20 operates a display hand (not shown) via a train wheel. .

Further, the interrupt control circuit 5 generates an interrupt signal INT to the arithmetic processing circuit 4 in response to the timing signal from the frequency dividing circuit 2 and the input signal from the input circuit 6. The arithmetic processing circuit 4 starts its operation by the interrupt signal INT and the output signal of the system clock generating circuit 3, and the control signal generated from the arithmetic processing circuit 4 is sent to each peripheral circuit via the BUS 9. By performing the interrupt operation in this way, the current consumption of the system is reduced.

FIG. 2 shows a logical regulation means 10 which is one of the features of the present invention.
It is a functional block diagram of. In FIG. 2, the frequency dividing circuit 2
A logic regulation circuit 130 generates a logic regulation signal for setting or resetting a flip-flop of a specific stage. The logic slowing / abbreviating circuit 130 starts its operation by a start signal VCW from a starting means 120 based on the timing signal from the frequency dividing circuit 2 and the slow / fast data from the slow / fast data register 100. The starting means 120 starts the control signal VC from the control signal sent from the arithmetic processing circuit 4 via BUS9.
It creates W. Further, the operation signal generating means 110
Operates to generate an operation signal while the activation signal VCW is being output, and to output the operation signal to the BUS 9 when there is a request from the arithmetic processing circuit 4.

Next, the detailed operation of the logic slowing / fastening means 10 will be described with reference to FIG. FIG. 3 is a circuit embodiment of the logic regulation means 10. The speed data register 100 is a bit register group 1
It consists of 01-105. The writing of data to each register is performed by writing the data sent from the input circuit 6 to the BUS 9 by the read signal from the arithmetic processing circuit 4. The data stored in the register groups 101 to 105 are
It is possible to send to the logic regulation circuit 130 to perform a total of 32 ways of regulation operation. The activation means 120 and the operation signal generation means 110 include flip-flops 122 and 123, a gate circuit 121,
It is composed of a three-state buffer 124. Logic regulation circuit 1
The operation of 30 is performed by resetting the flip-flops 122 and 123 by the output of the gate circuit 121. At the logic regulation timing of the logic regulation circuit 130 shown in this circuit embodiment, since the operation is performed in synchronization with the 128 Hz signal output from the frequency divider circuit 2, the activation signal VCW is 1 at maximum.
28Hz 2 cycles will be output. When there is a request from the arithmetic processing circuit 4 for this activation signal VCW, BUS9
It is the three-state buffer 124 that outputs to the. In FIG. 6, the output of the gate circuit 121 is set to "1" and the flip-flop 1
It is a flowchart figure which shows the logic speed-up / down processing routine which resets 22 and 123. As shown in FIG. 6, the logical slowing / quickening process is used in combination with the time counting, which is the specific implementation content of the time counting processing means 30 shown in FIG. That is, the logical slowdown process is performed in a 10-second cycle, such as when a carry of 60 seconds occurs as a result of counting the seconds or when the 1-second digit becomes 0. In addition, the registers used for this processing, such as seconds, minutes, and hours, can be built into RAM8.

FIG. 4 is a functional block diagram of the step motor drive means 20 which is another feature of the present invention. In FIG. 4, the waveform for driving the display hand is created by the motor drive waveform synthesis circuit 250 and output by the motor driver 240. The timing signal for synthesizing the motor drive waveform is the reference clock CL output from the frequency dividing circuit 2.
And a signal obtained by dividing the reference clock CL by the frequency dividing circuit 230. Starting means 210 shown in FIG.
Is to generate the activation signal MOTOR from the control signal sent from the arithmetic processing circuit 4 via BUS9. Further, the operation signal generation means 200 operates so as to generate an operation signal while the activation signal MOTOR is being output, and to output the operation signal to the BUS 9 when there is a request from the arithmetic processing circuit 4. is there.

Next, the detailed operation of the step motor drive means 20 will be described with reference to FIG. FIG. 5 shows a step motor driving means.
20 is a circuit embodiment of 20 circuits. Motor drive waveform synthesis circuit 250
Is mainly composed of a forward rotation drive waveform synthesis circuit 251, a reverse rotation drive waveform synthesis circuit 252, and a reset pulse generation circuit 254. The forward rotation and reverse rotation drive waveforms of the step motor and the synthesizing circuit are well known and will not be described here.
The signals synthesized by the drive waveform synthesizing circuits 251 and 252 are output from the motor driver 240 via the gate circuits 255 and 256. Whether the drive waveform output from the motor driver 240 is the normal rotation drive waveform or the reverse rotation drive waveform,
It is determined by the value of the register 212. Further, the register 211 includes a motor drive waveform summing circuit 250 and a frequency dividing circuit.
Starting means 21 for generating a start signal MOTOR for operating 230
It is 0. Further, the register 212 can also be referred to as the activation means 210 in the sense that the drive waveform is designated and the synthesizing circuit is operated. When there is a request from the arithmetic processing circuit 4 for this activation signal MOTOR, it is the 3-state buffer 213 that outputs to the BUS 9, and this is the operation signal generation means 200. The register 211 is reset by the reset signal from the reset pulse generation circuit 254. Since the reset pulse creation circuit 254 creates a reset pulse after the drive waveform is output, the activation signal MOTOR holds "1" while the drive waveform is output.

Finally, another feature of the present invention, the activation control means 31, 32
Will be described. As shown in FIG. 11, start-up control means 31, 32 for the logical regulation and step motor, respectively,
It can be stored in the ROM 7 similarly to other operation processing means. As shown in FIG. 5, the step motor drive waveform is generally synthesized with the timing signal from the frequency dividing circuit 2 as a reference. Therefore, if the logical slowing / quickening operation and the stepping motor driving operation are overlapped, the normal composite waveform is not obtained, and the result that the stepping motor does not rotate normally occurs. The activation control means 31 and 32 are means for avoiding simultaneous drive of both, and are means for appropriately prioritizing and performing operation processing.

FIG. 7 is a flow chart showing an embodiment of the logical slow start control means 31. While the output signal MOTORBUSY of the three-state buffer 213 shown in FIG. 5 is "1", the logical slowing / quicking operation is waited for, and the start signal VCW is set to "1" immediately after changing to "0".
Then, the logical slowing / quickening operation is performed. Such a logical slowdown / quick start control is suitable when the step motor drive is completed in a short time, and the startup delay time of the logical slowdown / quick operation can be minimized.

FIG. 8 is a flow chart showing another embodiment of the logical slow start control means 31. In this example, MOTORBUS
When the Y signal is "1", the startup control is performed so as to ignore the logical slowing / quickening operation. Such start-up control of logic slowdown is rare in actual use because the overlap of the step motor drive and the drive of the logic slowdown operation is rare, and even if the single logic slowdown operation is neglected, the rate of the day is moderately increased. It is suitable when there is no effect and can simplify the circuit configuration.

FIG. 9 is a flow chart showing another embodiment of the logical slow start control means 31. In this example, MOTORBUS
When the Y signal is "1", the number of activations of the logical slowing / fastening operation is counted by the counting means, and when the MOTORBUSY signal is "0", the logical slowing / fastening operation is collectively performed. Such a logical speed-up / start-up control is suitable when the stepping motor drive is continuously performed for a relatively long time, and the daily rate speed-up / down amount can be reliably adjusted.

FIG. 10 is a flowchart showing an embodiment of the step motor start control means 32. While the output signal VCWBUSY of the 3-state buffer 124 shown in FIG. 3 is "1", the step motor drive operation is waited, and immediately after the output signal VCWBUSY changes to "0", the start signal MOTOR is set to "1" to drive the step motor. Is being done. In such step motor drive start control, the logical delay operation is completed in a relatively short time, and thus the start delay time can be minimized.

〔The invention's effect〕

The electronic timepiece of the invention includes a clock circuit for inputting an output signal of a frequency divider circuit and an output signal of an input circuit to perform a clock operation, and a drive signal for inputting an output signal of the clock circuit to drive a step motor. It is possible to easily avoid the simultaneous operation of the logical slow-and-fast and the step motor drive by the configuration having the output step motor drive means and the start-up control means for prohibiting the simultaneous operation of the logical slow-and-forward means and the step motor drive means. In addition, since both processes can be efficiently performed, it becomes possible to easily realize an analog multifunctional electronic timepiece with logical slowdown / advancement that allows a step motor drive at an arbitrary timing. The effect is very large.

[Brief description of drawings]

FIG. 1 is a system block diagram of an electronic timepiece according to the present invention, FIG. 2 is a functional block diagram of logic slowdown / fastening means, FIG. 3 is a circuit embodiment diagram of logic slowdown / fastening means, and FIG. 4 is a step motor. 5 is a functional block diagram of the driving means, FIG. 5 is a circuit embodiment diagram of the step motor driving means, FIG. 6 is a flow chart showing the logical slowdown / fastening process, and FIG. 7 is a first implementation of the logical slowdown / quick start control means. An example diagram, FIG. 8 is a second embodiment diagram of the logical slow / quick start control means, FIG. 9 is a third embodiment diagram of the logical slow / quick start control means, and FIG. 10 is a step motor start control means. FIG. 11 shows an embodiment of each processing means stored in the ROM. 1 ... Oscillation circuit 2 ... Dividing circuit 3 ... System clock generating circuit 4 ... Arithmetic processing circuit 5 ... Interrupt control circuit 6 ... Input circuit 7 ... ROM 8 ... RAM 9 ... BUS 10 ... … Logic slow / fast means 20 …… Step motor drive means 30 …… Timekeeping processing means 31 …… Logic slow / quick start control means 32 …… Step motor start control means 33 …… Input processing means 34 …… Hand position data processing means 100 to 105 ... slow / fast data register 110-124 ... logical slow / fast operation signal generating means and starting means 130-146 ... logical slow / quick circuit 200-214 ... step motor operation signal generating means and starting means 220 ... gate circuit 230 …… Division circuit 240 …… Motor driver 250-256 …… Motor drive waveform synthesis circuit

Claims (4)

[Claims] 1. An oscillator circuit, a divider circuit for inputting and dividing an output signal of the oscillator circuit, an input circuit for inputting a correction signal, and a logic by setting or resetting the divider circuit. In an electronic timepiece having a logical slowing / fastening means for performing a slowing / fastening operation and a stepping motor driving means for operating by an output signal of the frequency dividing circuit, a clock is provided by inputting the output signal of the frequency dividing circuit and the output signal of the input circuit. A timing circuit for performing an operation, a step motor driving means for inputting an output signal of the timing circuit and outputting a driving signal for driving a step motor, and a simultaneous operation of the logical slowing / forwarding means and the step motor driving means. An electronic timepiece comprising: a start-up control unit that prohibits. 2. The starting control means prohibits the starting operation of the other when the logical slowing down means or the step motor driving means is operating until the operation is stopped, and 2. The electronic timepiece according to claim 1, further comprising a start-up operation standby means for starting the other operation after the operation of 1. 3. The starting control means has a starting operation generation stopping means which does not carry out the starting operation of the other one of the logical slowing / fastening means and the step motor driving means when the other is operating. Electronic clock as described. 4. The activation control means includes an operation cycle counting means for counting the cycle of the operation when one of the logical slowing / fastening means and the step motor driving means is operating, and the operation is stopped. 2. The electronic timepiece according to claim 1, further comprising correction operation means for operating the other one of the logical slowdown / expansion means and the step motor drive means, which is not in operation, based on the counting result of the operation cycle counting means.