JPH0870124A - Fabrication of silicon carbide semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a silicon carbide semiconductor device having low ON resistance and excellent in switching characteristics by removing a first thermal oxide by wet etching and then depositing a second thermal oxide on the bottom face and side face of a trench thereby improving the MOS interface characteristics. CONSTITUTION: A trench 6 is made in a p-type epitaxial layer 3 at a predetermined position. The trench 6 has a side face 6a extending perpendicularly to the surface of the p-type epitaxial layer 3 and a bottom face 6b extending in parallel therewith. A first oxide is then deposited on the wall of the trench by thermal oxidation. Consequently, the damage layer on the inner wall of the trench is oxidized. The thermal oxide is then removed by means of hydrofluoric acid thus removing the damage layer from the inner wall of the trench. Subsequently, a gate oxide 7 is deposited by thermal oxidation. Consequently, a thin gate oxide 7a is deposited on the side face 6a of the trench 6 and a thick gate oxide 7b is deposited on the bottom face 6b of the trench 6. Furthermore, a thick gate oxide 7c is deposited on an n<+> source region 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon carbide semiconductor device, which is used, for example, in a method for manufacturing an insulated gate field effect transistor, especially a vertical MOSFET for high power. It is suitable.

[0002]

2. Description of the Related Art In recent years, a vertical power MOSFET using a silicon carbide single crystal material has been proposed as a power transistor. In order to reduce the loss of the power transistor, it is necessary to reduce the on-resistance, and as a device structure capable of effectively reducing the on-resistance, the trench gate type power MOSFET shown in FIG. 13 (for example, Japanese Patent Laid-Open No. 4-239778). Is proposed. Groove gate type power MO in FIG.
The SFET comprises a first semiconductor region 31 on a silicon carbide substrate 30.
And the second semiconductor region 3 is formed on the first semiconductor region 31.
2 is formed, and further, the third semiconductor region 33 is formed in a predetermined region of the second semiconductor region 32. Further, a recess 34 is formed penetrating the third semiconductor region 33 and the second semiconductor region 32 to reach the first semiconductor region 31, and the recess 36 is filled with a gate 36 via a gate insulating film 35. Has been done. An insulating film 37 is formed on the upper surface of the gate 36, and an electrode film 38 is formed on the third semiconductor region 33 including the insulating film 37.

Generally, when manufacturing a trench gate type power MOSFET as shown in FIG. 13, after forming the recess 34 in the trench gate portion, the surface of the recess 34 is oxidized by thermal oxidation to insulate the gate. The film 35 is formed on the side surface and the bottom surface, and then the gate electrode (gate 36) is formed to complete the basic structure of the trench gate portion.

[0004]

However, in the case of manufacturing the trench gate type power MOSFET as shown in FIG. 13, the inner wall of the trench gate portion is different by using the dry etching method, particularly the reactive ion etching method (RIE method). Since it is formed under the isotropic etching condition, a damage layer is formed on the inner wall of the groove. This is because there is currently no etching solution that can efficiently etch silicon carbide substrates.
This is because the etching method such as the dry etching method is the easiest. Here, the damaged layer is a layer having crystal defects formed when etching is performed by physically applying ions as in the RIE method, or a surface to be etched is unevenly etched when etching is performed by chemical etching. It means an uneven layer or the like that is generated due to this. And
In this damaged layer, the MOS interface characteristics are deteriorated and the ON resistance is increased and the switching characteristics are deteriorated.

In order to remove the damaged layer on the inner wall of the groove, it is possible to remove the damaged layer by uniformly wet etching the surface to be etched.
As is well known in wet etching, there is a problem that it is very difficult to uniformly remove the damaged layer. Further, since the corners of the groove bottom are formed by anisotropic dry etching, corners are formed at the corners of the groove bottom, and electric field concentration occurs. Therefore, the breakdown voltage between the gate and the drain is lowered. In order to round the corners, it is conceivable to perform dry etching with weak anisotropy or to thermally oxidize the corners, but dry etching with weak anisotropy is so-called side etching in which the side wall of the groove gradually expands. Therefore, there is a problem that it is difficult to miniaturize the groove, and it is difficult to control the thermal oxide film thickness in thermal oxidation because the dependence of the thermal oxidation rate in silicon carbide on the plane orientation is not clear. There was a problem.

An object of the present invention is, firstly, to remove the damaged layer on the inner wall of the groove to improve the MOS interface characteristics, to produce a silicon carbide semiconductor device having excellent switching characteristics and low on-resistance. To get. Secondly, it is possible to obtain a method for manufacturing a silicon carbide semiconductor device in which the gate-drain breakdown voltage can be improved by rounding the corners of the bottom of the groove and side etching is reduced.

[0007]

According to a first aspect of the present invention, which is configured to achieve the above object, a groove having a bottom surface and a side surface is formed by dry etching on a surface of a semiconductor substrate made of silicon carbide. A forming step, a first oxide film forming step of forming a first thermal oxide film on the bottom surface and the side surface of the groove, and an oxide film removing step of removing the first thermal oxide film by wet etching, After the oxide film removing step, a second oxide film forming step of forming a second thermal oxide film on the bottom surface and the side surface of the groove is included.

According to a second aspect of the invention, in addition to the structure of the first aspect, the semiconductor substrate made of silicon carbide has a hexagonal (0001) carbon face or a hexagonal ( 0001) surface close to carbon surface, cubic {1
11} carbon face or a face close to a cubic {111} carbon face, and the plane orientation of the bottom surface of the groove in the trench forming step is the same as the plane orientation of the semiconductor substrate. It is characterized in that they are configured to be substantially the same.

Further, according to the invention of claim 3, in the manufacturing method of claim 1 or 2, the second thermal oxide film is a side surface oxide film formed on the side surface of the groove. The bottom surface oxide film formed on the bottom surface of the groove is thicker than the side surface oxide film. further,
According to a fourth aspect, in addition to the invention according to any one of the first to third aspects, the second thermal oxide film forming step is a step of simultaneously forming the side surface oxide film and the bottom surface oxide film. It is characterized by

According to a fifth aspect of the present invention, in the method of manufacturing a silicon carbide semiconductor device according to any one of the first to fourth aspects, the side surface of the groove in the groove forming step is the semiconductor substrate. Is characterized by having a surface substantially perpendicular to the surface of the. According to the invention of claim 6, in the method of manufacturing the silicon carbide semiconductor device according to any one of claims 1 to 5, the surface regions of the bottom surface and the side surface of the groove in the groove forming step are Each of them includes a lattice defect, and the formation of the first oxide film is a step of forming the first thermal oxide film having a thickness of the surface region including at least the lattice defect. . .

According to the invention of claim 7, it is composed of two layers of a first conductivity type low resistance layer and a first conductivity type high resistance layer formed on the low resistance layer, and The upper surface side of the high resistance layer serves as the front surface side, and the lower surface side of the low resistance layer serves as the back surface side.
A semiconductor layer forming step of forming a semiconductor layer made of conductivity type single crystal silicon carbide; a semiconductor area forming step of forming a first conductivity type semiconductor area in a predetermined area in the semiconductor layer; A groove forming step of penetrating the semiconductor region and the semiconductor layer to reach the high-resistance layer of the first conductivity type; and a first thermal oxide film formed on an inner wall of the groove. An oxide film forming step, an oxide film removing step of removing the first thermal oxide film by etching so as to remove the first thermal oxide film, and a second thermal oxide film forming step on the inner wall of the groove after the oxide film removing step And a gate electrode layer on the second thermal oxide film, a first electrode layer on the surface of the semiconductor layer and the surface of the semiconductor region, and a second electrode layer on the back surface side of the semiconductor substrate. And an electrode forming step of forming respective electrode layers of It is an butterfly.

According to the invention described in claim 8, in the method for manufacturing a silicon carbide semiconductor device according to claim 7, (0001) carbon whose surface orientation on the surface side of the semiconductor substrate made of silicon carbide is hexagonal Plane or cubic {11
1} carbon surface, and the groove bottom portion of the groove in the groove forming step is substantially the same as the surface orientation of the semiconductor substrate.

According to a ninth aspect of the invention, in the method of manufacturing a silicon carbide semiconductor device according to the seventh or eighth aspect, in the groove forming step, a predetermined depth is formed in the groove forming region from a surface of the semiconductor layer. It is characterized in that it has a local thermal oxidation step of forming the local thermal oxide film and a local oxide film removing step of removing the local thermal oxide film. According to the invention of claim 10, in the method of manufacturing a silicon carbide semiconductor device according to any one of claims 7 to 9, the groove forming step is performed in the groove forming region by a predetermined distance from a surface of the semiconductor layer. And a vertical processing step of forming the groove having a depth of 5 such that the side wall of the groove is substantially perpendicular to the surface of the semiconductor layer.

According to the eleventh aspect, in the method for manufacturing the silicon carbide semiconductor device according to any one of the first to tenth aspects, the first oxide film forming step and the second oxide film forming step. Among them, in at least one of the steps, the Si ₃ N ₄ film is directly formed on the surface of the semiconductor substrate.

[0015]

In general, when forming a groove on the surface of a silicon carbide substrate, a damage layer is formed on the inner wall of this groove. According to the invention described in claim 1, the first
In the oxide film forming step, the first thermal oxide film is formed by thermally oxidizing the surface of the damaged layer, and then the first thermal oxide film is used as a layer having crystal defects in the damaged layer or an uneven layer. Wet etching is performed so that the film is removed.
As a result, the damaged layer on the inner wall can be removed and the inner wall is flattened. Therefore, the second
The thermal oxidation film has a uniform rate of thermal oxidation, and the second thermal oxide film also has a uniform rate.

According to the second aspect of the present invention, the plane orientation of the semiconductor substrate is a hexagonal (0001) carbon face or a cubic {111} carbon face. Then, the bottom of the groove is made to have a surface substantially the same as the plane orientation of the semiconductor substrate. Hexagonal (0001) carbon face or cubic {11}
It was found that the 1} carbon surface has a higher thermal oxidation rate than the other surfaces. Therefore, this thermal oxidation forms a thin oxide film on the side wall of the groove and a thick oxide film on the bottom of the groove. By removing these thermal oxide films, side etching can be reduced and the inner wall of the groove can be etched.

According to the third aspect of the invention, in the second oxide film forming step, a thin oxide film is formed on the sidewall of the groove and a thick oxide film is formed on the bottom of the groove by this thermal oxidation. According to the invention as set forth in claim 4, the side oxide film and the bottom oxide film can be formed at the same time to shorten the process. According to the fifth aspect of the present invention, the side surface of the groove is formed with a surface substantially perpendicular to the surface of the semiconductor substrate.

According to the sixth aspect of the invention, the first thermal oxide film is formed in the thickness of the surface region including the lattice defect generated in the groove forming step. Therefore, the damaged layer can be removed from the surface of the groove formed after the first oxide film is removed. According to the invention described in claim 7, by forming the first thermal oxide film in the groove and removing the first thermal oxide film, the damaged layer on the side surface of the groove to be the channel portion is efficiently removed. It Therefore, the second on the groove side
The surface of the conductive semiconductor layer serves as a channel,
When a current flows between the drains, it is possible to manufacture a silicon carbide semiconductor device having improved MOS interface characteristics, excellent switching characteristics, and low on-resistance. Further, since the corners of the bottom of the groove are rounded, the breakdown voltage between the gate and the drain can be improved.

According to the eighth aspect of the present invention, the plane orientation of the semiconductor substrate is a hexagonal (0001) carbon face or a cubic {111} carbon face. Then, the bottom of the groove is made to have a surface substantially the same as the plane orientation of the semiconductor substrate. Hexagonal (0001) carbon face or cubic {11}
It was found that the 1} carbon surface has a higher thermal oxidation rate than the other surfaces. Therefore, this thermal oxidation forms a thin oxide film on the side wall of the groove and a thick oxide film on the bottom of the groove. By removing these thermal oxide films, side etching can be reduced and the inner wall of the groove can be etched.

According to the ninth aspect of the present invention, the groove forming step includes a local thermal oxidation step of forming a thermal oxide film in the groove forming region and an oxide film removing step of removing the thermal oxide film.
Thereby, at the same time as forming the groove, damage to the inner wall of the groove can be removed in advance before the first oxide film forming step. Therefore, according to the present invention, the damaged layer can be removed more efficiently.

According to the tenth aspect of the present invention, the sidewall of the groove in which the channel is formed is formed substantially perpendicular to the surface of the semiconductor substrate. Generally, in a silicon substrate, selective oxidation is performed by forming an oxidation resistant mask Si ₃ N ₄ film via a pad oxide film, because the silicon substrate is caused by stress at the interface between the Si ₃ N ₄ film and the silicon substrate. This was to reduce the occurrence of defects in the film and to suppress the peeling of the Si ₃ N ₄ film.
Meanwhile almost no defects on the substrate different in physical properties from the silicon in the single crystal substrate such as a silicon carbide substrate, Si ₃ N
It has been confirmed by experiments that no peeling of the _four films occurs. Therefore, according to the invention of claim 11, since the oxidation resistant Si ₃ N ₄ film is formed directly on the substrate surface without the pad oxide film, the first oxide film forming step or the second oxide film forming step The surface of the semiconductor substrate can be protected from thermal oxidation in the oxide film forming step. Moreover, in the oxide film formation process using the conventional pad oxide film, bird's beak (thermal oxide film shape in which thermal oxidation was performed in a wedge shape in the lateral direction from the edge of the Si ₃ N ₄ film) was a problem. However, it is possible to prevent the occurrence of such bird's beaks, and it is possible to form finer grooves.

[0022]

【Example】

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional view of a groove gate type power MOSFET (vertical type power MOSFET) of the present embodiment.

The n ⁺ -type single crystal silicon carbide (hereinafter referred to as SiC) substrate 1 as the low resistance layer is made of hexagonal SiC (000
1) It has a carbon surface as a surface, has low resistance, and has a carrier density of about 5 × 10 ¹⁸ cm ⁻³ . This n ⁺ type single crystal Si
An n ⁻ -type epitaxial layer 2 as a high resistance layer and a p-type epitaxial layer 3 as a semiconductor layer are sequentially laminated on a C substrate 1. The n ⁻ type epitaxial layer 2 has a carrier density of about 1 × 10 ¹⁶ cm ⁻³ and a thickness of about 10 μm. The p-type epitaxial layer 3 has a carrier density of about 1 × 10 ¹⁷ cm ⁻³ and a thickness of about 2 μm, and the surface 4 of the p-type epitaxial layer 3 serves as an element surface.

In this embodiment, an n ⁺ type single crystal SiC substrate 1 is used.
And the n ⁻ type epitaxial layer 2 form a semiconductor substrate 14. A predetermined region on the surface 4 of the p-type epitaxial layer 3 has an n ⁺ source region 5 as a semiconductor region.
And the carrier concentration of the n ⁺ source region 5 is 1 × 1.
The junction depth is about 0.5 μm at about 0 ¹⁹ cm ⁻³ . A groove 6 is formed at a predetermined position on the surface 4 of the p-type epitaxial layer 3. This groove 6 is an n ⁺ source region 5
And has a side surface 6a penetrating the p-type epitaxial layer 3 to reach the n ⁻ -type epitaxial layer 2 and perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface 6b parallel to the surface of the p-type epitaxial layer 3.

Inside the groove 6, a gate electrode layer 8 is arranged with a gate thermal oxide film 7 as a gate insulating film interposed therebetween. Here, the inner wall of the groove 6 is etched by a combination of thermal oxidation at 1100 ° C. for about 5 hours and removal of the thermal oxide film. This removes the damaged layer and rounds the groove corners. After that, the gate thermal oxide film 7
Is formed by a single thermal oxidation step at 1100 ° C. for about 5 hours, and a thin gate thermal oxide film 7a having a thickness of about 50 nm located on the side surface 6a of the trench 6 and a thickness located on the bottom surface 6b of the trench 6 are formed. It is composed of a thick gate thermal oxide film 7b of about 500 nm. Further, the gate thermal oxide film 7 is also formed on the n ⁺ source region 5, and the gate thermal oxide film 7c in this region is also thickened to about 500 nm. This is because the hexagonal (0001) carbon surface or the cubic {111} carbon surface has a higher thermal oxidation rate than the other surfaces. A thin oxide film and a thick oxide film are formed at the bottom of the groove.

The gate electrode layer 8 is the gate thermal oxide film 7
Of the first polysilicon layer 8a and the second polysilicon layer 8b which are in contact with each other and are doped with phosphorus. An interlayer insulating film 9 having a thickness of about 1 μm is arranged on the gate electrode layer 8. Furthermore, the n ⁺ source region 5 including the interlayer insulating film 9 is also included.
On the surface of p-type epitaxial layer 3 and the surface of p-type epitaxial layer 3.
A source electrode layer 10 is disposed as an electrode layer of, and the source electrode layer 10 is in contact with both the n ⁺ source region 5 and the p-type epitaxial layer 3. On the back surface of the n ⁺ -type single crystal SiC substrate 1, a drain electrode layer 11 as a second electrode layer that is in contact with the substrate 1 is provided.

Manufacturing of this trench gate type power MOSFET
The process will be described in detail with reference to FIGS. First, the figure
As shown in Fig. 2, the plane orientation of the surface is (0001) carbon.
Low resistance n which is a surface⁺Type monocrystalline SiC substrate 1 is prepared
It And that n⁺On the surface of the single crystal SiC substrate 1
Carrier density is 1 × 10¹⁶cm^-3About 10 μm thick
Degree n ^-Type epitaxial layer 2 and carrier density 1
× 10¹⁷cm^-3P-type epitaxy with a thickness of about 2 μm
The char layer 3 is sequentially laminated. In this way, n⁺Type
Crystal SiC substrate 1 and n^-With the epitaxial layer 2
The semiconductor substrate 14 is formed.

Subsequently, as shown in FIG. 3, the mask material 12 is used for the p-type epitaxial layer 3 by an ion implantation method so that the carrier concentration on the surface is about 1 × 10 ¹⁹ cm ⁻³ and the junction depth is 0.1. An n ⁺ source region 5 of about 5 μm is formed.
Next, after removing the mask material 12, as shown in FIG.
Reactive ion etching (RI
By the method E), a trench 6 penetrating the n ⁺ source region 5 and the p type epitaxial layer 3 and reaching the n ⁻ type epitaxial layer 2 is formed. The groove 6 has a side surface 6 a perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface 6 b parallel to the surface of the p-type epitaxial layer 3.

Then, as shown in FIG. 5, a thermal oxide film 15 as a first thermal oxide film 11 is formed on the inner wall of the groove by thermal oxidation.
It is formed by a thermal oxidation process at 00 ° C. for about 5 hours. By this thermal oxidation, the damage layer on the inner wall of the groove formed by the RIE method is oxidized, and the side surface 6a of the groove 6 has a thickness of about 50 nm and the bottom surface 6b of the groove 6 has a thickness of about 500 nm. Form 15. Thereafter, as shown in FIG. 6, after removing the thermal oxide film 15 with hydrofluoric acid, the mask material 13 is removed.
Is removed. By removing the thermal oxide film 15,
The damage layer on the inner wall of the groove is removed.

Subsequently, as shown in FIG. 7, a gate thermal oxide film 7 is formed by a single thermal oxidation process at 1100 ° C. for about 5 hours by the thermal oxidation method. By this thermal oxidation, the side surface 6a of the groove 6 is located. The thickness of the gate thermal oxide film 7a is about 50 nm and the thickness of the bottom surface 6b of the trench 6 is 500 n.
A gate thermal oxide film 7b having a thickness of about m is formed. Further, a thick gate thermal oxide film 7c having a thickness of about 500 nm is formed on n ⁺ source region 5.

Subsequently, as shown in FIG. 8, the inside of the trench 6 is sequentially backfilled with the first and second polysilicon layers 8a and 8b. Then, as shown in FIG. 1, on the gate thermal oxide film 7 including the first and second polysilicon layers 8a and 8b,
The interlayer insulating layer 9 is formed by the CVD method, and the gate thermal oxide film 7 and the interlayer insulating layer 9 on the surface of the n ⁺ source region 5 and the p type epitaxial layer 3 at the source contact planned position are removed. Then, the source electrode layer 10 is formed on the n ⁺ source region 5, the p type epitaxial layer 3 and the interlayer insulating layer 9, and the drain electrode layer 11 is formed on the back surface of the n ⁺ type single crystal SiC substrate 1 to form a trench gate. Type SiC power MOS
Complete the FET.

As described above, the trench gate type power M of this embodiment is used.
In the OSFET, the n ⁺ type single crystal SiC substrate 1 (first conductivity type low resistance layer) and the n ⁻ type epitaxial layer 2 (first conductivity type high resistance layer) formed on the n ⁺ type single crystal SiC substrate 1 are used. 2) and the surface direction of the surface of the n ⁻ -type epitaxial layer 2 is a (0001) carbon surface, a semiconductor substrate 14 made of hexagonal single-crystal silicon carbide, and a surface of the semiconductor substrate 14. Are formed on the surface, and the surface orientation is (00
01) p type epitaxial layer 3 (second conductivity type semiconductor layer) made of hexagonal single crystal silicon carbide which is a carbon surface
When, n ⁺ source region formed in a predetermined region of the p-type epitaxial layer 35 (the semiconductor region of the first conductivity type), n ⁺
A groove 6 penetrating the source region 5 and the p-type epitaxial layer 3 to reach the n ⁻ -type epitaxial layer 2 and having a side surface 6 a perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface 6 b parallel to the surface of the p-type epitaxial layer 3. And the side surface 6a of the groove 6
And the bottom surface 6b, there is no damage layer on the inner wall of the groove, and a groove rounded at the corner of the groove bottom is formed. Further, the gate thermal oxide film 7 serving as a gate insulating film is thicker on the bottom surface 6b of the groove 6 than on the side surface 6a of the groove 6, and is formed inside the gate thermal oxide film 7 in the groove 6. Gate electrode layer 8, the source electrode layer 10 (first electrode layer) formed on the surface of the p-type epitaxial layer 3 and the surface of the n ⁺ source region 5, and the drain electrode formed on the back surface side of the semiconductor substrate 14. Layer 11 (second electrode layer)
It has and.

Therefore, when the surface of the p-type epitaxial layer 3 on the side surface 6a of the groove 6 serves as a channel and a current flows between the source and the drain, the damaged layer on the inner wall of the groove is removed, so that the MOS interface characteristics can be improved. Also, since the corner of the bottom of the groove is rounded, the breakdown voltage between the gate and drain is increased. Furthermore, since the gate thermal oxide film 7a on the side surface 6a of the groove 6 is thin, the threshold voltage can be lowered (for example, 2V), and the groove 6
The gate thermal oxide film 7b on the bottom surface 6b of the
The breakdown voltage between the drains can be increased (for example, 500 V or more), the parasitic capacitance can be reduced, and high speed operation can be performed. As a result, the manufacturing cost can be reduced and the manufacturing yield can be improved.

In the first embodiment, the groove side surface is perpendicular to the semiconductor surface, but the invention is not limited to this.
By changing the conditions of the IE method, the method can be applied even when the groove side surface has a desired inclination angle, and in this case, the same effect can be obtained. In the above embodiment, the mask material 13 is an oxidation resistant mask, for example, a Si ₃ N ₄ film is used to prevent the substrate surface from being oxidized, and Si ₃ N _{4 is used.}
It is possible to prevent generation of so-called bird's beak in which thermal oxidation is laterally performed in a wedge shape from the end portion of the film.

In FIG. 14, an oxide film is formed through the pad oxide film 41.
The case of forming 13 will be described. Semiconductor substrate surface
First, the pad oxide film 41 is formed, and further,
Si₃N _FourA mask material 13 made of a film or the like is formed. Its state
By using the mask material 13 by etching or the like.⁺Source
N penetrates through the region 5 and the p-type epitaxial layer 3^-Type epita
A groove reaching the axial layer 2 is formed (FIG. 14A).
After that, an oxide film 43 is formed in the groove as shown in FIG.
I will make it, but at this time n⁺Oxidation progresses toward the source region 5
As a result,⁺Birdsby in source area 5
42 will be generated. As a result, n⁺Source
Region 5 becomes thinner and sheet resistance R1 increases
Occurs. On the other hand, the manufacturing method in the above embodiment
As described above, in the present invention, the oxidation resistance is
Forming the transparent mask material 13 directly on the semiconductor substrate
Has solved such a problem. That is, FIG. 15 (a)
Oxidation resistant mask directly on the semiconductor substrate, as shown in
For example Si₃N_FourForm a film and use the mask material 13 in that state
By etching etc.⁺Source region 5 and p-type epitaxy
N penetrates the axial layer 3^-Reaches the epitaxial layer 2
Forming a groove. Then, as shown in FIG.
An oxide film 44 is formed on the inner wall. At this time n⁺Source area 5
Is not oxidized by bird's beak,⁺Source
The groove is formed without increasing the sheet resistance R1 in the area.
Can be made. (Second Embodiment) A second embodiment of the present invention will be described below.
Will be described with reference to the drawings.

The second embodiment differs from the first embodiment only in the groove forming method, and only the manufacturing process thereof will be described in detail with reference to FIGS. In the second embodiment, after the n ⁺ source region of FIG. 3 of the first embodiment is formed, as shown in FIG.
6 For example, a Si ₃ N ₄ film having a thickness of about 200 nm is formed, and the groove formation region 18 is formed by dry etching using the mask material 17.
The oxidation resistant film 16 is removed.

Then, as shown in FIG. 10, after forming a groove 19 having a groove depth of about 1 μm by dry etching or the like, the mask material 17 is removed. Then, as shown in FIG.
A thermal oxide film 20 having a thickness of about 2 μm is formed by a local thermal oxidation method at 1100 ° C. By this step, the groove 21 having the inclined side surface is formed.

[0038] Thereafter, as shown in FIG. 12, the thermal oxide film 20 by removing the hydrofluoric acid, less damage in about depth 2 [mu] m, has the inclined side surface, further n ⁺
A trench 21 penetrating the source region 5 and the p-type epitaxial layer 3 and reaching the n ⁻ -type epitaxial layer 2 is formed. After forming the groove in this way, the process is as shown in FIG. 5 of the first embodiment.

In the second embodiment, it is not always necessary to form the groove 19 before the local thermal oxidation step, and the required groove depth of the groove 21 may be obtained only by the local thermal oxidation step. The present invention is not limited to the above-described first embodiment and second embodiment. For example, only the n-channel type has been described.
It goes without saying that the same effect can be obtained also in the p-channel type in which semiconductor type n and p are exchanged. Also, the film thickness of the thermal oxide film in the groove is not limited to the film thickness used in the examples (about 50 nm on the side surface and about 500 nm on the bottom surface), and the film on the bottom surface of the groove is more than the film thickness on the side surface of the groove. Any configuration may be used as long as the thickness is thicker. Further, the thermal oxidation and the removal of the thermal oxide film before forming the gate oxide film are repeated not only once but also a plurality of times, so that the roundness of the corner portion of the groove bottom can be made large. Further, the plane orientation of the semiconductor substrate is not limited to the hexagonal (0001) carbon face in the embodiment, but may be, for example, a cubic (111) carbon face.

[Brief description of drawings]

FIG. 1 is a sectional view of a silicon carbide semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross sectional view for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.

3 is a cross sectional view for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.

FIG. 4 is a cross sectional view for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.

5 is a cross sectional view for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.

6 is a cross sectional view for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.

7 is a cross sectional view for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.

8 is a cross sectional view for illustrating a manufacturing process for the silicon carbide semiconductor device shown in FIG.

FIG. 9 is a cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device of the second embodiment of the present invention.

FIG. 10 is a cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device in the second embodiment of the present invention.

FIG. 11 is a cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device in the second embodiment of the present invention.

FIG. 12 is a cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device in the second embodiment of the present invention.

FIG. 13 is a cross-sectional view of a conventional silicon carbide semiconductor device.

14A and 14B are cross-sectional views of a silicon carbide semiconductor device when an oxide film is formed via a pad oxide film.

15A and 15B are cross-sectional views of a silicon carbide semiconductor device when an oxide film is directly formed on a semiconductor substrate.

[Explanation of symbols]

1 n ⁺ type single crystal SiC substrate as a low resistance layer 2 n ⁻ type epitaxial layer as a high resistance layer 3 p type epitaxial layer as a semiconductor layer 5 n ⁺ source region as a semiconductor region 6 groove 6a side face 6b bottom face 7 gate Thermal oxide film 8 Gate electrode layer 9 Interlayer insulating film 10 Source electrode layer as first electrode layer 11 Drain electrode layer as second electrode layer 13 Mask material (oxidation resistance) 14 Semiconductor substrate 15 Thermal oxide film 16 Acid resistance Oxide film 18 Groove forming region 20 Thermal oxide film 21 Groove having inclined side surfaces 30 Silicon carbide substrate 31 First semiconductor region 32 Second semiconductor region 33 Third semiconductor region 34 Recess 35 Gate insulating film 36 Gate 37 Insulation Film 38 Electrode film 41 Pad oxide film 42 Bird's beak

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ken Miyajima 1-1-1, Showa-cho, Kariya city, Aichi prefecture Nihon Denso Co., Ltd.

Claims (11)

[Claims] 1. A groove forming step of forming a groove having a bottom surface and a side surface on a surface of a semiconductor substrate made of silicon carbide by dry etching, and forming a first thermal oxide film on the bottom surface and the side surface of the groove. No. 1 oxide film forming step, an oxide film removing step of removing the first thermal oxide film by wet etching, and a second thermal oxide film is formed on the bottom surface and the side surface of the groove after the oxide film removing step. And a second oxide film forming step. 2. A semiconductor substrate made of silicon carbide having a hexagonal (0001) carbon face, a face close to a hexagonal (0001) carbon face, and a cubic {11} face.
1} carbon face or a face close to a cubic {111} carbon face, and the plane orientation of the bottom face of the groove in the groove forming step is
2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the surface orientation of the semiconductor substrate is substantially the same as the surface orientation of the semiconductor substrate. 3. The second thermal oxide film includes a side surface oxide film formed on the side surface of the groove and a bottom surface oxide film formed on the bottom surface of the groove and thicker than the side surface oxide film. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein 4. The silicon carbide according to claim 1, wherein in the second thermal oxide film forming step, the side surface oxide film and the bottom surface oxide film are formed at the same time. Manufacturing method of semiconductor device. 5. The carbonization according to claim 1, wherein the side surface of the groove in the groove forming step has a surface substantially vertical to the surface of the semiconductor substrate. Method of manufacturing silicon semiconductor device. 6. The surface regions of the bottom surface and the side surface of the groove in the groove forming step each include a lattice defect, and the first oxide film formation includes the surface region including at least the lattice defect. 6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, which is a step of forming the first thermal oxide film having a thickness of. 7. A low resistance layer of the first conductivity type and a high resistance layer of the first conductivity type formed on the low resistance layer.
Also, a semiconductor made of a second conductivity type single crystal silicon carbide is provided on the front surface side of a semiconductor substrate made of single crystal silicon carbide in which the upper surface side of the high resistance layer is the front surface side and the lower surface side of the low resistance layer is the back surface side. A step of forming a semiconductor layer, a step of forming a semiconductor region of a first conductivity type in a predetermined region in the semiconductor layer, and a step of forming the semiconductor region and the semiconductor layer from the upper surface of the semiconductor region. A groove forming step of forming a groove penetrating to reach the first conductivity type high resistance layer; a first oxide film forming step of forming a first thermal oxide film on an inner wall of the groove; An oxide film removing step of removing by etching so as to remove the thermal oxide film; a second oxide film forming step of forming the second thermal oxide film on the inner wall of the groove after the oxide film removing step; A gate electrode layer on the thermal oxide film of the Wherein the first electrode layer on the surface of the semiconductor region, the manufacturing method of the second electrode layer on the back surface side of the semiconductor substrate, a silicon carbide semiconductor device which comprises an electrode formation step of forming, respectively. 8. The surface orientation of the surface side of the semiconductor substrate made of silicon carbide is a hexagonal (0001) carbon surface or a cubic {111} carbon surface, and the groove of the groove is formed in the groove forming step. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the bottom of the groove has a surface substantially the same as the surface orientation of the semiconductor substrate. 9. The groove forming step comprises a local thermal oxidation step of forming a local thermal oxide film having a predetermined depth from the surface of the semiconductor layer in the groove forming region, and a local thermal oxide film removing step. 9. The method for manufacturing a silicon carbide semiconductor device according to claim 7, further comprising an oxide film removing step. 10. The groove forming step comprises forming the groove having a predetermined depth from a surface of the semiconductor layer in the groove forming region,
10. The method for manufacturing a silicon carbide semiconductor device according to claim 7, further comprising a vertical processing step of forming the sidewall of the groove so as to be substantially vertical to the surface of the semiconductor layer. Method. 11. The first oxide film forming step and the second oxide film forming step.
At least one of the oxide film forming steps
Directly on the surface of the semiconductor substrate in ₃N_FourMembrane shaped
Any of claims 1 to 10, characterized in that
2. A method for manufacturing a silicon carbide semiconductor device according to claim 1.