JPH0865164A - D/a converter - Google Patents

Abstract

PURPOSE: To improve the resolution of an output voltage without increasing the number of capacitors by minutely controlling the potentials at other terminals of (n+1)-sets of capacitors. CONSTITUTION: A switch 18 is provided between ends on one side of capacitors 11-13 and one-side end of a capacitor 14 in a D/A converter 10. After the capacitor 14 shares a voltage in response to the input data, the switch 18 is opened to allow the capacitor 14 to hold the voltage thereacross. When the potential of the other-side end of the capacitor 14 is controller to be increased/decreased in this state, a voltage at one-side end of the capacitor 14 with respect to a ground potential is changed to activate a signal OE at a proper timing to close an output switch 21. Thus, a voltage at one-side end of the capacitor 14 at that time is extracted as a voltage VOUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is a digital / digital (digital / digital)
Analog) converter, especially TF for multi-gradation display
The present invention relates to a capacitor array type D / A converter suitable for use in a data driver for a T (Thin Film Transistor) liquid crystal panel. Flat panel displays typified by TFT liquid crystal panels are thin and lightweight,
Although it is widely used for display devices such as word processors and portable personal computers due to its power-saving feature, it has the drawback of being higher in cost than CRT-type displays. The price hinders the spread.

[0002]

2. Description of the Related Art FIG. 10 is a structural diagram of a TFT liquid crystal panel. In the TFT liquid crystal panel, a large number of data bus lines 1 and scan bus lines 2 are arranged in an intersecting manner, and TFTs 3 and pixel electrodes 4 are formed at each intersection.
An FT substrate 5 and a counter substrate 6 on which a uniform common electrode (not shown) is formed on the entire surface and which is arranged to face the TFT substrate 5.
And a liquid crystal is sandwiched between these two substrates 5 and 6.

When the scan bus lines 2 are line-sequentially selected and a predetermined ON voltage is applied, the selected scan
All the TFTs 3 for one row connected to the bus line 2 are turned on, and the voltage (display voltage) on the data bus line 1 at that time is written into the pixel electrode 4 through the TFT 3 in the on state, and The liquid crystal transmittance between the common electrodes changes, and a display gradation corresponding to the writing voltage (potential difference between the pixel electrode 4 and the common electrode) is obtained.

The most basic method for realizing N gradations is to prepare N kinds of reference voltages and select one of them according to the gradation of display data. However, in this method, since the reference voltage generating circuit becomes large in scale in proportion to the number of gradations, the limit is about 8 to 16 gradations. FIG. 11 is a principle diagram of a conventional multi-gradation method that exceeds 16 gradations. In this conventional example, 32-gradation display is realized using a stepwise reference voltage.

7 is a data memory for storing display data,
Reference numeral 8 is a decoder for decoding display data, and 9 is an analog for selecting one of eight kinds of reference voltages V _{0 to} V ₇ according to the decoding result of the decoder 8 and also for selecting one of the steps of the selected reference voltage. It is a switch part. In addition,
Here, for simplification of description, only one pixel (5 bits) of the display data is shown.

The eight types of reference voltages V _{0 to} V ₇ are shown in FIG.
As shown in (a), each stepwise voltage has four steps. In such a configuration, one of the reference voltages V _{0 to} V ₇ is selected by the upper 3 bits of the display data, and further one of the steps of the selected reference voltage is selected by the lower 2 bits. The signals AP and BP are stair selection timing signals. The rising timing and the falling timing of the signals AP and BP match each of the four steps as shown in FIG. 12B, and one of them is selected according to the combination of the lower 2 bits of the display data. Specify the timing.

According to this, it is possible to obtain gradations of a number obtained by multiplying the kind of reference voltage by the number of steps of stairs, that is, 8 kinds × 4 steps = 32 gradations.

[0008]

However, in order to realize, for example, 64 gradations by the method using the stepwise reference voltage, the number of steps is doubled to 8 steps, or
Or, it is necessary to double the reference voltage to 16 types,
The former is impractical in terms of timing (4 stages are limited within a limited period of one horizontal period), and the latter causes an increase in the scale of the reference voltage generation circuit, so that price increase is inevitably inevitable. There is a problem.

[0009]

It is therefore an object of the present invention to provide a capacitor array type D / A converter suitable for use in a data driver for a TFT liquid crystal panel for multi-gradation display.

[0010]

D / A converter of the present invention, in order to solve the problems] are each 2 ⁰ times the reference capacitance, 2 x ^1, ...,
One end of each of the first to nth capacitors having a capacity of 2 ^n-1 times is connected in common, and the other end is connected to the first to nth capacitors.
To the first potential and the second potential via complementary switches up to, and one end of the n capacitors is connected to the (n + 1) th capacitor of the reference capacitance and one end of the (n + 2) th switch via the (n + 1) th switch. And the other end of the (n + 1) th capacitor is connected to the first potential or the second potential.

Further, the data driver of the liquid crystal panel of the present invention is a reference voltage for selecting two adjacent reference voltages among a plurality of reference voltages having a stepwise voltage waveform according to the upper bits of the display data in pixel units. Selection means and the 2
The two reference voltages are a first potential and a second potential.
The D / A converter described, and the n-th D / A converter
ON / OFF means for turning on / off the n complementary switches of the D / A converter according to the middle bit of the display data in a state where the +1 switch is turned on, and the D / A.
With the (n + 1) th switch of the converter turned off,
A step voltage selection means for selecting one of the step voltages of the first potential or the second potential according to the lower bit of the display data, and the voltage selected by the step voltage selection means is supplied to the liquid crystal panel. It is characterized in that the write voltage is used.

Alternatively, the reference voltage is set to a constant potential, and the potential at the other end of the (n + 1) th capacitor of the D / A converter is changed according to a predetermined staircase voltage.

[0013]

In the D / A converter of the present invention, when the (n + 1) th switch is turned off, the voltage corresponding to the ON / OFF combination of the complementary switches is held in the (n + 1) th capacitor. Then, if the potential (first potential or second potential) on the other end side of the capacitor is changed in that state,
The voltage (output voltage) on one end side of the capacitor increases or decreases in response to the change.

Therefore, by finely manipulating the potential (first potential or second potential) on the other end side of the capacitor, the resolution of the output voltage can be improved without increasing the number of capacitors. Further, in the data driver of the liquid crystal panel of the present invention, for example, when 256 gradations are to be obtained, adjacent combinations of nine types of reference voltages (“8 sets in total” according to the upper 3 bits of 8-bit display data for one pixel )), Then control ON / OFF of the complementary switches according to the middle 3 bits of the same display data (the voltage difference among the voltages obtained by dividing the potential difference of one set of reference voltages into “8 divisions”). 8) × 8 divisions × by selecting one of the “4 steps” staircase voltage of the first or second potential according to the lower 2 bits of the same display data.
4 steps = 256 gradations are obtained.

Therefore, the number of stages of the reference voltage is 4 (32
The number of reference voltages can be reduced to 9 (increased by one at most compared to 32 gradations), and a large increase in circuit scale can be achieved at a low cost. Gradation can be achieved. Alternatively, it is preferable to change the voltage at the other end of the (n + 1) th capacitor by a predetermined step voltage because it is not necessary to superimpose the step voltage on the reference voltage and the reference voltage source can be simplified.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a D / A converter according to the invention described in claim 1. In the figure, reference numeral 10 is a capacitor array type D / A converter for converting n-bit input data into an analog voltage. Although n = 3 is set for simplification of description, the present invention is not limited to this.

11 to 14 are capacitors,
The capacitor 11 corresponds to the first capacitor, the capacitor 12 corresponds to the second capacitor, the capacitor 13 corresponds to the third capacitor (nth capacitor), and the capacitor 14 corresponds to the fourth capacitor (n + 1th capacitor). Equivalent to a capacitor). Reference numerals 15 to 17 denote first to third (nth) complementary switches, respectively.
Has a pair of switches (identified by adding a and b to the same symbol) in which one is on and the other is off.

Reference numeral 18 denotes a fourth switch (n + 1th switch).
H), 19 is a fifth switch (n + 2th switch),
Reference numeral 20 is a buffer, and 21 is an output switch. here,
The capacitance values of the first to fourth capacitors 11 to 14 are
The capacitance value of the capacitor 14 is 1C (C is an arbitrary reference capacitance)
Then, the capacitance value of the first capacitor 11 is 1C,
The capacitance value of the capacitor 12 is 2C, and the third capacitor 1
The capacitance value of 3 is 4C. That is, with respect to the reference capacitance C
2 each⁰2 times¹2 times ²Double (2^n-1Capacity)
have.

Next, the connection relation of each element will be explained. One ends of the three capacitors 11 to 13 are commonly connected, and the other ends of these capacitors 11 to 13 are respectively connected. It is connected to the first potential V _ref1 and the second potential V _ref2 via the first to third complementary switches 15 to 17. Specifically, the other end of the first capacitor 11 is connected to the first potential V _ref1 via one switch 15a of the first complementary switch 15 and is connected to the second potential V _ref1 via the other switch 15b. Connected to the potential V _ref2 of
The other end of the second capacitor 12 is connected to the second complementary switch 1
6 is connected to the first potential V _ref1 via one switch 16a and is connected to the second potential V _ref2 via the other switch 16b, and the other end of the third capacitor 13 is It is connected to a first potential V _{re f1} through one of the switches 17a of the third complementary switch 17, is connected to the second potential V _ref2 through the other switch 17b.

One end of each of the three capacitors 11 to 13 is connected to a fourth capacitor 14 via a fourth switch 18.
And the other end of the fourth capacitor and the fifth switch 19 are connected to the first potential V _ref1 (or the second potential V _ref2 ). . The voltage on the one end side of the fourth capacitor 14 is taken out as an output voltage VOUT via the buffer 20 and the output switch 21. Note that OE is an output enable signal, and when this signal OE becomes active (highly active for convenience), the voltage on the one end side of the fourth capacitor 14 is taken out as VOUT.

In such a configuration, n-bit (here, 3 bits) input data is used to turn on / off the first to third complementary switches 15 to 17. Specifically, the lower bits (bits having a weight value of 2 ⁰ ) of the 3-bit input data are for turning on / off the first complementary switch 15 and the same middle bits (bits having a weight value of 2 ¹ ). Is for turning on / off the second complementary switch 16, and the upper bits (bits having a weight value of 2 ² or 2 ^n-1 ) are for turning on / off the third complementary switch 17.

The first to third complementary switches 15 to 17 are
It is composed of a pair of switches with reference numerals a and b,
When the value of the bit of the input data is 0, one switch is turned on, and when it is 1, the other switch is turned off. Here, it is assumed that when the bit value is 0, the switch denoted by the symbol a is turned on, and when the bit value is 1, the switch denoted by the symbol b is turned on.

That is, when the input data is [000 ₍₂₎ ] (below), the switches 15a, 16a and 17
When a is on and [001 ₍₂₎ ] (below), the switches 15b, 16a and 17a are on and [010
₍₂₎ ] (below), switches 15a, 16b
And 17a are turned on and [011 ₍₂₎ ] (below)
Switches 15b, 16b and 17a are turned on.
When [100 ₍₂₎ ] (or less), switch 15
When a, 16a and 17b are turned on and [101 ₍₂₎ ] (below), switches 15b, 16a and 17b are turned on, and when [110 ₍₂₎ ] (below), switch 15a, 16b and 17b turn on, [111 ₍₂₎ ]
When (below), switches 15b, 16b and 1
7b turns on.

Looking at the potentials on the other end sides of the first to third capacitors 11 to 13 for each of the combinations of turning on of these switches, in [000 ₍₂₎ ], the first
~ The first potential V _ref1 is applied to the third capacitors 11 to 13, and at [001 ₍₂₎ ] the second capacitor 12
And the first potential V _ref1 is applied to the third capacitor 13 and the second potential V _ref1 is applied to the first capacitor 11.
_ref2 is added, and at [010 ₍₂₎ ], the first potential V _ref1 is applied to the first capacitor 11 and the third capacitor 13.
Is added, the second potential V _ref2 is applied to the second capacitor 12, and in [011 ₍₂₎ ], the first potential V _ref1 is applied to the third capacitor 13 and the first capacitor V _ref2 is added. The second potential V _ref2 is applied to 11 and the second capacitor 12, and at [100 ₍₂₎ ],
The first capacitor 11 and the second capacitor 12 have a first
With potential V _ref1 is applied, the second potential V _ref2 is applied to the third capacitor 13, [101 _(2)]
Then, the first potential V _ref1 is applied to the second capacitor 12, and the second potential V _ref2 is applied to the first capacitor 11 and the third capacitor 13, and [110
₍₂₎ ], the first potential V _{ref1 is applied} to the first capacitor 11.
Is added to the second capacitor 12 and the third capacitor
A second potential V _ref2 is applied to the capacitor 13 of
In [111 ₍₂₎ ], the first to third capacitors 11 to 1
A first potential V _ref1 is applied to 3.

Now, the first to third complementary switches 15 to 1
When the switches 15a, 16a and 17a of No. 7 are turned on (that is, the input data is [000 ₍₂₎ ]) and the fourth switch 18 and the fifth switch are turned on, all the capacitors (first to fourth Both ends of the capacitors 11 to 14) are short-circuited, and the retained charge is reset to zero. When the input data is set to, for example, [001 ₍₂₎ ] described above after this reset operation, the second potential V _ref2 is applied to the other end of the first capacitor 11 and the other capacitors (second, second The third and fourth capacitors 12, 13,
The first potential V _ref1 is applied to the other end of 14). As a result, a closed circuit such as V _ref2 → first capacitor 11 → fourth capacitor 14 → V _ref1 is formed. At this time,
The second and third capacitors 12 and 13 are connected in parallel to the fourth capacitor 14, and the parallel combined capacitance thereof is the second, third and fourth capacitors 12, 13 and 14.
Is the sum of the capacitance values of the second capacitor 12, the capacitance value 2C of the second capacitor 12 + the capacitance value 4C of the third capacitor 13 + the capacitance value 1C of the fourth capacitor 14 = 7C. That is,
When the input data is set to [001 ₍₂₎ ], the potential difference between V _ref1 and V _ref2 (hereinafter, “ΔV _ref ”) should be distributed to the capacitance value 1C of the first capacitor 11 and the combined capacitance value 7C. become.

Since the charges Q stored in the capacitors connected in series are equal to each other, the first capacitor 1
If the voltage across 1 is V ₁ and the voltage across the fourth capacitor 14 is V ₂ , then V ₁ = Q / 1C, V ₂ = Q / 7C, and ΔV _ref = V ₁ + V _{2. Therefore} , ΔV _ref = Q / 1C
It becomes + Q / 7C. Therefore, when ((001
₍₂₎ ]) has a fourth capacitor 14 with a 1/8 of ΔV _ref
Will be distributed.

Similar to the above, considering other combinations of ~, when ([010 ₍₂₎ ]), ΔV _ref
= Q / 2C + Q / 6C, and 2/8 of ΔV _ref is distributed to the fourth capacitor 14. ([0
11 ₍₂₎ ]), ΔV _ref = Q / 3C + Q / 5C
Therefore, 3/8 of ΔV _ref is distributed to the fourth capacitor 14. In the case of ([100 ₍₂₎ ]), ΔV _ref = Q / 4C + Q / 4C, and 4/8 of ΔV _ref is distributed to the fourth capacitor 14. When ([101 ₍₂₎ ]), ΔV _ref = Q / 5
C + Q / 3C, and the fourth capacitor 14 has ΔV
5/8 of _ref will be allocated. ([11
0 ₍₂₎ ]), ΔV _ref = Q / 6C + Q / 2C, and 6/8 of ΔV _ref is distributed to the fourth capacitor 14. In the case of ([111 ₍₂₎ ]), ΔV _ref = Q / 7C + Q / 1C, and 7/8 of ΔV _ref is distributed to the fourth capacitor 14.

In summary, the fourth capacitor 14
The voltage between both ends of can be expressed by the following equation (1). ([Data] / 2 ⁿ ) ΔV _ref (1) where [data]: value of input data (decimal notation) n: number of bits of input data Here, in the D / A converter 10 of the present embodiment. The point of the configuration is that the fourth switch 18 is provided between one end side of the first to third capacitors 11 to 13 and one end side of the fourth capacitor 14.

According to this, after the voltage according to the input data is distributed to the fourth capacitor 14, the fourth switch 1
When 8 is turned off, the voltage across the fourth capacitor 14 (see the above equation (1)) can be held as it is. Then, in this state, when the potential on the other end side of the fourth capacitor 14 (first potential V _ref1 ) is increased or decreased, the voltage on the one end side of the fourth capacitor 14 with respect to the ground potential is _calculated according to the following equation (2). Since it changes, V _ref1 + ([data] / 2 ⁿ ) ΔV _ref (2) If the output switch 21 is turned on by activating the signal OE at an appropriate timing, the fourth capacitor 14 at that time is turned on. The voltage on one end side (see the above formula (2)) can be taken out as the output voltage VOUT.

As described above, according to the D / A converter 10 of this embodiment, the fourth portion is provided between the one end side of the first to third capacitors 11 to 13 and the one end side of the fourth capacitor 14.
Since the switch 18 is provided, the fourth switch 18
Is turned off, the voltage across the fourth capacitor 14 (voltage corresponding to the input data) can be held, and the voltage across the fourth capacitor 14 and the other end of the fourth capacitor 14 (the first potential _Vref1 ) and output voltage VOUT
Can be

Therefore, the resolution of the D / A converter 10 of this embodiment is the least significant bit (LSB) of the input data.
In addition to being determined by the first potential V _ref1 ,
By changing the first potential V _ref1 with a width smaller than the value of the least significant bit of the input data, the number of input bits is not increased (in other words, without complicating the structure of the capacitor array). Therefore, the resolution can be easily improved.

2 to 4 are views showing an embodiment of the data driver of the liquid crystal panel according to the invention described in claim 2.
In FIG. 2, reference numeral 30 is a data driver IC (hereinafter abbreviated as “data driver”) of the TFT color liquid crystal panel. The data driver 30 is in charge of 192 data bus lines, but one pixel of the color liquid crystal panel is composed of 3 dots of R (red), G (green) and B (blue), and each dot is In this case, one data driver 30 is in charge of 64 pixels of one scan line since the data bus line is laid.

The data driver 30 comprises a shift register section 31, a first memory section 32, a second memory section 33, a decoder section 34 and a write voltage generating section 35. The shift register unit 31 sequentially shifts the data fetching start signal SPD generated once in the horizontal scanning period in the time axis direction in synchronization with the pixel clock CLKD, and sequentially shifts from the first pixel to the sixth pixel.
It outputs the respective data acquisition timing signals S _{1 to} S _{6 4} of up to 4 pixels. Note that S _OUT is a shift output to another data driver connected in cascade (a data driver in charge of 65 pixels and thereafter).

The first memory section 32 includes a shift register 31.
From the first pixel to the 64th pixel in response to the signals S _{1 to} S ₆₄ from
The display data (R _DATA , G _DATA , B _DATA ) up to the pixel is sequentially fetched. Each data is 8-bit serial data, and has a total storage capacity of 8 × 192 (bits). The second memory unit 33 receives a load input at the time when the data acquisition to the last cascade-connected first memory unit 32 is completed, that is, when the data acquisition for one scan line is completed (or an appropriate time thereafter). In response to the pulse signal LP, the data in the first memory section 32 is simultaneously fetched.

The decoder unit 34 decodes the data in the second memory unit 34 in dot units. The decoding operation is performed by decoding the upper 3 bits of 8 bits (hereinafter, "upper decoding") and the middle 3 bits. (Hereinafter referred to as "medium-order decoding") and lower 2-bit decoding (hereinafter referred to as "lower-order decoding"). The result of the upper decoding is used for selecting the reference voltage, the result of the middle decoding is used for D / A conversion, and the result of the lower decoding is used for selecting the staircase voltage.

The write voltage generator 35 is the same as in the above embodiment.
It includes the above D / A10 converter, and the decoder unit 3
Display data in dot units according to each decoding result of 4
Generates a writing voltage with a gradation according to the
Pressure scan bus line D ₁~ D₁₉₂Not shown through
Written on the pixel electrode of the liquid crystal panel (see reference numeral 4 in FIG. 10).
Imprint

The signals AP and BP are signals for designating the selection timing of the staircase voltage, and V _{0 to} V ₈ are nine kinds of reference voltages having four steps of staircase voltages. FIG. 3 is a partial block diagram of 1 dot (8 bits) of FIG. The write voltage generation unit 35 selects one of eight adjacent combinations of nine types of reference voltages V _{0 to} V ₈ according to the decoding result of the higher-order decoding unit 34 a of the decoder 34, and selects 1 set.
The power supply selection unit 35a that outputs the lower one of the pair of reference voltages as the first potential V _ref1 and the higher one of the reference voltages as the second potential V _ref2 , and the decoding results of the middle-order decoding unit 34b and the lower decoding unit 34c of the decoder 34. Also, the D / A converter according to the above-described embodiment, which generates a write voltage having a magnitude corresponding to the display data for one dot in accordance with the first and second potentials V _ref1 and V _ref2 from the power source selection unit 35a. 10 and 10.

Here, the power source selection section 35a includes the decoder 3
4 has a function as a reference voltage selecting unit described in the gist of the invention together with the upper decoding unit 34a of the decoder 3
4 has a function as an on / off means described in the gist of the invention, and a lower decoding part 34c of the decoder 34 functions as a staircase voltage selection means described in the gist of the invention. have.

FIG. 4 is a waveform diagram of the reference voltages V _{0 to} V ₈ and a write voltage output timing diagram. Reference voltage V ₀ ~
V ₈ has a stepwise voltage waveform that changes in four steps, and the potential difference between two adjacent reference voltages corresponds to 4 × S _{step when} the potential difference of one _step is V _step . One of the eight adjacent sets of these nine types of reference voltages V _{0 to} V ₈ is selected according to the result of upper decoding, and the lower one of the reference voltages of the one set is the first potential V _ref1 and the higher one. As the second potential V _ref2 , the D / A converter 10
D / A conversion operation (conversion operation according to the result of middle-level decoding) is performed. This D / A conversion operation is an on / off operation of the first to third complementary switches 15 to 17 in the above embodiment, and is performed during the D / A conversion period of FIG. 4B.

In FIG. 4B, the voltage on the one end side of the fourth capacitor 14 after the D / A conversion is changed according to the result of the intermediate decoding, as shown in the above equation (2). At the same time, it changes following the staircase waveform of the first potential V _ref1 . Then, one of the four rising / falling timings (a to d) of the signals AP and BP is designated by the result of the lower decoding, the signal OE becomes active at the designated timing, and the staircase voltage at that time is output. It is taken out as the voltage VOUT (writing voltage to the liquid crystal panel).

If "a" of the timing is designated (lower 2 bits → 00), the staircase voltage (base voltage) of the first stage is taken out as a write voltage, and "b" is designated (lower 2 bits → 01). If this is done, the staircase voltage of the second stage is extracted, and if “C” is designated (lower 2 bits → 10), then 3
If the staircase voltage of the fourth stage is taken out and "d" is designated (lower 2 bits → 11), the staircase voltage of the fourth stage is taken out.

FIG. 5A is a timing chart of ON / OFF operation of each switch of the D / A converter 10, and FIG.
Waveform diagram of a pair of adjacent reference voltages (first potential V _ref1 , second potential V _ref2 ) selected according to the upper 3 bits of the display data, and (c) fourth D / A converter 10 6 is a voltage waveform diagram on one end side of the capacitor 14 of FIG. During the ON period of the fifth switch 20, all the switches denoted by the symbol a of the first to third complementary switches 15 to 17 are also turned on. Therefore, in this period, the first to fourth capacitors 11 to 14 are all short-circuited at both ends,
The charges of these capacitors 11 to 14 are reset to zero. When the reset period ends, first, the first to third complementary switches 15 to 17 are turned on / off according to the input data (the middle 3 bits of the display data), and the selected 1 according to the upper 3 bits of the display data. A set of reference voltages (V _ref1 , V
Select the voltage between _ref2 ). Voltage selection subject prior equation (2), "ΔV _ref × 1/8" from the "[Delta] V _ref × 7 /
There are 7 types of voltages up to 8 "(more precisely, 8 types including V _ref1 ), and one of these 8 types of voltages becomes the voltage of the fourth capacitor 14. Next, before the start of the step voltage of V _ref1 , the fourth switch 18 is turned off, and the holding period of the voltage of the fourth capacitor 14 starts. Then, during this holding period, the fourth step follows the stepwise potential change of V _ref1 .
The voltage on one end side of the capacitor 14 changes, and one of the staircase voltages is selected according to the lower 2 bits of the display data and is output as the write voltage to the liquid crystal panel.

Therefore, the data driver 3 of this embodiment
According to 0, one set is selected from the adjacent combinations of the 9 types of reference voltages (8 sets in total) based on the decoding result of the upper 3 bits of the display data, and the potential difference between the one set of reference voltages is selected. (ΔV _ref ) is divided into eight, the middle 3 bits of the display data are D / A converted based on the divided voltage, and
Since the D / A conversion result is changed by the staircase voltage of the first potential V _{ref1 and} one of the staircase voltages is selected by the decoding result of the lower 2 bits of the display data, without increasing the number of stairs, Moreover, 8 sets × 8 divisions × 4 stages = 256 gradations can be obtained by increasing the number of reference voltages by one at most.

6 and 7 are D according to the invention described in claim 1.
It is a figure which shows the other Example of the / A converter. The same components as those in the above-described embodiment (FIG. 1) are designated by the same reference numerals and the description thereof will be omitted. In FIG. 6, 40
Is a sixth switch and 41 is a fifth capacitor. The sixth switch 40 is located between the other end of the fourth capacitor 14 and the first potential V _ref1, and turns on / off the application of the same potential to the other end. The fifth capacitor 41 has one end connected to the other end of the fourth capacitor 14 and the other end set to a predetermined staircase voltage VR, so that the potential of the other end of the fourth capacitor 14 is It is changed by the step voltage VR.

With this configuration, the first potential V _ref1
And it is no longer necessary to use a staircase voltage for the second potential V _ref2 . Therefore, all the reference voltages V _{0 to} V ₈ can be set to a constant potential, and the reference voltage source can be simplified. Figure 7
[FIG. 7] is a timing chart showing only a part peculiar to this embodiment. For other parts, see FIGS. 5A and 5C. The ON period of the sixth switch 40 is a period including the reset period and the D / A conversion period, and the voltage of the fourth capacitor 14 at the end of the ON period is the upper 3 bits of the display data and the middle level. It corresponds to 3 bits.

When the staircase voltage VR starts to change with a slight delay after the sixth switch 40 is turned off, the voltage on the one end side of the fourth capacitor 14 changes following this change.
This change is exactly the same as when the step voltage is used for the first potential V _ref1 and the second potential V _ref2 (that is, the embodiment of FIG. 1). Therefore, as in the embodiment of FIG. 1, if the output switch 21 is turned on according to the lower 2 bits of the display data, one of the staircase voltages appearing at one end of the fourth capacitor 14 is taken out as the write voltage. You can

8 and 9 show the D / A of this embodiment.
FIG. 4 is a configuration diagram of a data driver 30 ′ using a converter 10 ′, which corresponds to FIGS. 2 and 3 of the above embodiment, respectively. The difference from the data driver 30 of the above embodiment is that all the reference voltages V _{0 to} V ₈ are set to a constant potential and that the staircase voltage VR is used.

[0048]

According to the D / A converter of the present invention, the electric potential (first electric potential or second electric potential) on the other end side of the (n + 1) th capacitor is finely manipulated without increasing the number of capacitors. It is possible to improve the resolution of the output voltage. According to the data driver of the liquid crystal panel using the D / A converter of the present invention, when realizing 256 gradations, for example, the number of steps of the reference voltage is 4 (same as 32 gradations).
In addition to the above, the number of types of reference voltage can be suppressed to nine types (up to one type compared to 32 gray scales), and a large number of gray scales can be achieved inexpensively without causing a large increase in circuit scale. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a D / A converter of the present invention.

FIG. 2 is a block diagram of a data driver of a liquid crystal panel using the D / A converter of FIG.

FIG. 3 is a partial configuration diagram of FIG. 2.

4 is a timing chart of a data driver of a liquid crystal panel using the D / A converter of FIG.

5 is a timing chart of the D / A converter of FIG. 1 when applied to a data driver of a liquid crystal panel.

FIG. 6 is another configuration diagram of the D / A converter of the present invention.

FIG. 7 is a timing chart of a main part of FIG.

8 is a block diagram of a data driver of a liquid crystal panel using the D / A converter of FIG.

9 is a partial configuration diagram of FIG. 8. FIG.

FIG. 10 is a structural diagram of a liquid crystal panel.

FIG. 11 is a conventional configuration diagram of a data driver of a liquid crystal panel.

FIG. 12 is a timing chart of FIG.

[Explanation of symbols]

V _ref1 : First potential V _ref2 : Second potential V _{0 to} V ₈ : Reference voltage VOUT: Output voltage (writing voltage) 11: First capacitor 12: Second capacitor 13: Third capacitor (third capacitor n capacitor) 14: fourth capacitor (n + 1th capacitor) 15: first complementary switch 16: second complementary switch 17: third complementary switch (nth complementary switch) 18: fourth switch (N + 1st switch) 19: Fifth switch (n + 2th switch) 34a: Upper decoding section (reference voltage selecting means) 34b: Middle decoding section (on / off means) 34c: Lower decoding section (staircase voltage selection) Means) 35a: Power source selection section (reference voltage selection means)

Claims (3)

[Claims] Each 2 ⁰ times the 1. A reference capacity, 2 ^1-fold,
... One end of the first to ^n-th capacitors having a capacity of 2 ^n-1 times is commonly connected, and the other end of each of the first to n-th capacitors is connected through the first to the n-th complementary switches. Of the n capacitors and one end of the (n + 1) th capacitor of the reference capacitance and one end of the (n + 2) th switch through the (n + 1) th switch, and the (n + 1) th switch. The D / A converter in which the other end of the capacitor is connected to the first potential or the second potential. 2. A reference voltage selecting means for selecting two adjacent reference voltages among a plurality of reference voltages having a stepwise voltage waveform according to upper bits of display data in pixel units, and the two reference voltages. The D / A converter according to claim 1, wherein the first potential and the second potential are set, and the D / A converter according to the middle bit of the display data in a state in which the (n + 1) th switch of the D / A converter is turned on. /
On / off means for turning on / off the n complementary switches of the A converter, and in a state where the (n + 1) th switch of the D / A converter is turned off, according to the lower bit of the display data, the first potential or A data driver for a liquid crystal panel, comprising: a staircase voltage selecting unit that selects one of the staircase voltages having a second potential, wherein the voltage selected by the staircase voltage selecting unit is used as a write voltage to the liquid crystal panel. . 3. The liquid crystal according to claim 2, wherein the reference voltage is set to a constant potential, and the potential at the other end of the (n + 1) th capacitor of the D / A converter is changed according to a predetermined step voltage. Panel data driver.