JP2017203983A - Semiconductor device, system, and operation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that automatically adjusts the brightness of a display device.SOLUTION: A semiconductor device has an illuminance meter, a threshold value detection circuit, a timing controller, a digital-to-analog conversion circuit, a first display panel, and a second display panel. The illuminance meter is used to measure an illuminance of external light, and the threshold value detection circuit is used to set a threshold value for digital video data according to the illuminance. The timing controller produces signals for the first display panel or signals for the second display panel on the basis of the threshold value and video data transmitted from outside. The signals for the first display panel or signals for the second display panel are input to the same digital-to-analog conversion circuit, and the digital-converted signals are then input to the first display panel or second display panel.SELECTED DRAWING: Figure 3

Description

  One embodiment of the present invention relates to a semiconductor device, a system, and an operation method.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a processor, an electronic device, These driving methods, their manufacturing methods, their inspection methods, or their systems can be mentioned as examples.

  In recent years, improvements have been made in various aspects of display devices included in mobile phones such as smartphones, tablet information terminals, notebook PCs (personal computers), and the like. For example, display devices having features such as increasing the resolution, increasing the color reproducibility (NTSC ratio), reducing the drive circuit, and reducing power consumption have been developed.

  Further, as one of the improvements, there is a display device having a function of automatically adjusting the brightness of an image projected on the display device according to environmental light. Examples of the display device include a display device having a function of reflecting an environment light to project an image and a function of projecting a light emitting element to project an image. With this configuration, when the ambient light is sufficiently strong, the display mode (hereinafter referred to as a reflection mode) is used to display an image on the display device using the reflected light, or the ambient light is weak. In that case, the brightness of the image displayed on the display device can be adjusted as a display mode in which the light-emitting element is illuminated and an image is displayed on the display device (hereinafter referred to as a transmission mode or a self-light-emitting mode). In other words, the display device detects the ambient light using an illuminometer (sometimes referred to as an illuminance sensor) or the like, and changes the display method according to the intensity of the light, such as a reflection mode, a self-luminous mode, or An image can be displayed by selecting one of the modes using both of them.

  By the way, as a display device having a function of projecting an image by illuminating a light emitting element and a function of projecting an image by reflecting light of the environment, for example, a pixel circuit for controlling a liquid crystal element in one pixel, and a light emitting element Patent Documents 1 to 3 disclose a display device (hereinafter referred to as a hybrid (composite type) display device) having a pixel circuit that controls the above.

US Patent Application Publication No. 2003/0107688 International Publication No. 2007/041150 JP 2008-225381 A

  When realizing a display device having a function of projecting an image by illuminating a light emitting element and a function of projecting an image by reflecting light of the environment, a display panel having the former function and a display panel having the latter function Must be provided in the display device. In this case, since it is necessary to provide a driving circuit for each display panel in order to drive the former and the latter display panels, the area of the driving circuit on the display panel may increase. Further, when the number of driver circuits increases, the power consumption of the display device may increase.

  An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a module including a novel semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device using a module including a novel semiconductor device. Another object of one embodiment of the present invention is to provide a system using a novel semiconductor device.

  Another object of one embodiment of the present invention is to provide a semiconductor device with a small circuit area. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.

  Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not disturb the existence of other problems. Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described description and other problems. Note that in one embodiment of the present invention, it is not necessary to solve all the problems with respect to the above-described description and other problems.

(1)
One embodiment of the present invention includes a first operational amplifier, a second operational amplifier, and first to third circuits, and the first circuit includes first to nth switches (n is an integer of 2 or more); And the second circuit has first to nth selectors, and each of the first to nth selectors includes a first input terminal and a second input terminal. And the output terminal, the third circuit includes (n + 1) to (2n + 1) switches, and one terminal of the first switch is electrically connected to one of the pair of electrodes of the first capacitor. One terminal of the jth switch (j is an integer of 2 or more and n or less) is electrically connected to one of the pair of electrodes of the jth capacitive element, and one terminal of the jth switch The terminal is electrically connected to the other terminal of the (j−1) th switch, and the other terminal of the nth switch is the (nth 1) The first operational amplifier is electrically connected to one of the pair of electrodes, the non-inverting input terminal of the first operational amplifier is electrically connected to the other terminal of the nth switch, and the inverting input terminal of the first operational amplifier is The output terminal of the first operational amplifier is electrically connected, the non-inverting input terminal of the second operational amplifier is electrically connected to one terminal of the first switch, and the inverting input terminal of the second operational amplifier is connected to the second operational amplifier. The output terminal of the kth selector (k is an integer of 1 to n) is electrically connected to the other of the pair of electrodes of the (k + 1) th capacitive element, and is electrically connected to the output terminal. One terminal of the h switch (h is an integer not less than (n + 2) and not more than (2n + 1)) is electrically connected to the other terminal of the (h−1) th switch, and the other terminal of the (n + k) th switch. Is the second input of the kth selector. A wherein a is terminal and electrically connected.

(2)
Alternatively, according to one embodiment of the present invention, in the above (1), each of the first to (2n + 1) switches includes a first transistor, and the channel formation region of the first transistor includes indium, an element M (element M Is a semiconductor device including an oxide containing at least one of aluminum, gallium, yttrium, or tin) and zinc.

(3)
Alternatively, one embodiment of the present invention includes the (2n + 2) switch and the (2n + 3) switch in (1) or (2), wherein one terminal of the (2n + 2) switch is The semiconductor device is electrically connected to a non-inverting input terminal of the first operational amplifier, and one terminal of the (2n + 3) switch is electrically connected to a non-inverting input terminal of the second operational amplifier. .

(4)
Alternatively, according to one embodiment of the present invention, in the above (3), each of the (2n + 2) switch and the (2n + 3) switch includes a second transistor, and the channel formation region of the second transistor is indium, element A semiconductor device including an oxide containing at least one of M (the element M is aluminum, gallium, yttrium, or tin) and zinc.

(5)
Alternatively, according to one embodiment of the present invention, in any one of the above (1) to (4), the switch includes a (2n + 4) switch and a (2n + 5) switch, and one terminal of the (2n + 4) switch Is a semiconductor device characterized in that it is electrically connected to the output terminal of the first operational amplifier, and one terminal of the (2n + 5) switch is electrically connected to the output terminal of the second operational amplifier.

(6)
Alternatively, according to one embodiment of the present invention, in the above (5), each of the (2n + 4) switch and the (2n + 5) switch includes a third transistor, and the channel formation region of the third transistor includes indium, element A semiconductor device including an oxide containing at least one of M (the element M is aluminum, gallium, yttrium, or tin) and zinc.

(7)
Alternatively, one embodiment of the present invention includes a first operational amplifier, a second operational amplifier, first to third switches, a first capacitor, a second capacitor, and a selector. A first input terminal; a second input terminal; and an output terminal, wherein one terminal of the first switch is electrically connected to one of the pair of electrodes of the first capacitor, and the other of the first switch Is electrically connected to one of the pair of electrodes of the second capacitive element, and the non-inverting input terminal of the first operational amplifier is electrically connected to the other terminal of the first switch. The input terminal is electrically connected to the output terminal of the first operational amplifier, the non-inverting input terminal of the second operational amplifier is electrically connected to one terminal of the first switch, and the inverting input terminal of the second operational amplifier is Electrically connected to the output terminal of the second operational amplifier, The output terminal of the Kuta is electrically connected to the other of the pair of electrodes of the second capacitive element, one terminal of the second switch is electrically connected to the other terminal of the three switches, and the other of the third switch This terminal is a semiconductor device characterized in that it is electrically connected to the second input terminal of the selector.

(8)
Alternatively, according to one embodiment of the present invention, the semiconductor device according to any one of (1) to (7), an illuminance meter, a fourth circuit, a fifth circuit, a first display panel, The illuminometer is electrically connected to the fourth circuit, the fourth circuit is electrically connected to the fifth circuit, and the fifth circuit is The system is electrically connected to the semiconductor device, the first display panel is electrically connected to the semiconductor device, and the second display panel is electrically connected to the semiconductor device. It is.

(9)
Alternatively, one embodiment of the present invention is the system operation method according to (8), including first to tenth steps, and the first step includes a step of measuring illuminance by an illuminometer. The second step includes a step of transmitting the illuminance from the illuminometer to the fourth circuit, and the third step is performed by the fourth circuit based on the illuminance and the second display by the fourth circuit. Generating a first data for determining a gray level of the panel; the fourth step includes a step of transmitting the first data from the fourth circuit to the fifth circuit; and a second data from the outside to the fifth circuit. Transmitting, and the fifth step includes a step of initializing the semiconductor device, and the sixth step corresponds to the first data and the second data in the fifth circuit according to the first data and the second data. 3rd data to send to 1 display panel And a step of transmitting third data from the fifth circuit to the semiconductor device, and a step of digital-analog converting the third data into fourth data in the semiconductor device, wherein the seventh step is , Transmitting the fourth data from the semiconductor device to the first display panel, and displaying an image on the first display panel. The eighth step includes a step of initializing the semiconductor device. Generating a fifth data to be transmitted to the second display panel according to the first data and the second data in the fifth circuit; and transferring the third data from the fifth circuit to the semiconductor device. And transmitting the fifth data to the sixth data by converting the fifth data into the sixth data in the semiconductor device, and the tenth step includes the sixth data from the previous semiconductor device. Send to the second display panel, comprising the step of displaying an image on the second display panel, the second data is an operation method, which is a video data.

  According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a module including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device using a module including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a system using a novel semiconductor device can be provided.

  Alternatively, according to one embodiment of the present invention, a semiconductor device with a small circuit area can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided.

  Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 10 is a block diagram illustrating an example of a semiconductor device and an example of a display portion. 3A and 3B illustrate an operation principle of a semiconductor device. FIG. 10 is a circuit diagram illustrating an example of a semiconductor device. FIG. 3 is a circuit diagram illustrating an example of a semiconductor device and an example of an analog switch. 6 is a timing chart illustrating an operation example of a semiconductor device. FIG. 6 is a circuit diagram for explaining an operation example of a semiconductor device. 10 is a flowchart illustrating a system using a semiconductor device. The block diagram which shows an example of a source driver circuit. The flowchart which shows the manufacture example of an electronic component, the perspective view of an electronic component, and the perspective view of a semiconductor wafer. The perspective view which shows the example of an electronic device. The figure which shows the structural example of a touchscreen. The figure which shows the structural example of the pixel of the display panel of a touchscreen. Sectional drawing which shows the structural example of a touchscreen. Sectional drawing which shows the structural example of a touchscreen. The schematic diagram which shows the example of the shape of the reflecting film of a display panel. The block diagram which shows the structural example of an input part. FIG. 10 is a circuit diagram illustrating pixels of a display portion. The perspective view which shows a display module.

Descriptions of “electronic device”, “electronic component”, “module”, and “semiconductor device” will be described. In general, an “electronic device” includes, for example, a personal computer, a mobile phone, a tablet terminal, an electronic book terminal, a wearable terminal, an AV device (AV), an electrical appliance, a housing facility device, a business facility device, It may refer to digital signage, an automobile, or an electrical product having a system. The “electronic component” or “module” refers to a processor, a storage device, a sensor, a battery, a display device, a light emitting device, an interface device, an RF tag (RF), a receiving device, and a transmitting device included in the electronic device. And so on. A “semiconductor device” is a device using a semiconductor element, or a drive circuit, a control circuit, a logic circuit, a signal generation circuit, a signal conversion circuit, or a potential level conversion to which a semiconductor element is applied, which an electronic component or module has. A circuit, a voltage source, a current source, a switching circuit, an amplifier circuit, a memory circuit, a memory cell, a display circuit, a display pixel, or the like may be used.

  In this specification, an oxide semiconductor is sometimes referred to as an OS (Oxide Semiconductor). Therefore, a transistor including an oxide semiconductor in a channel formation region may be referred to as an OS transistor.

(Embodiment 1)
In this embodiment, examples of semiconductor devices that can be included in a display device are described.

<Configuration example of semiconductor device>
FIG. 1 illustrates an example of a display portion and a drive circuit portion that can be provided in the display device. A semiconductor device 100 illustrated in FIG. 1 is a part of a source driver that can drive a pixel circuit including a liquid crystal element and a pixel circuit including a light-emitting element. The semiconductor device 100 includes an illuminance meter 101, a threshold detection circuit 102, a timing controller 103, and a circuit 104. The semiconductor device 100 is electrically connected to the display unit 110. Note that in this specification, the semiconductor device 100 and the display unit 110 may be collectively referred to as a system or an electronic device.

  The display unit 110 includes a display panel LP and a display panel OP. As the display panel LP, for example, a reflective liquid crystal panel having a liquid crystal element can be applied. In addition, for example, a light emitting device having a self light emitting element can be applied to the display panel OP. Examples of the self-light-emitting element include OLED (Organic Light Emitting Diode). In the present embodiment, the display panel LP will be described as a reflective liquid crystal panel, and the display panel OP will be described as an organic EL panel.

  The illuminance meter 101 is electrically connected to the threshold detection circuit 102, and the threshold detection circuit 102 is electrically connected to the timing controller 103. The timing controller 103 is electrically connected to the circuit 104, and the circuit 104 is electrically connected to the display panel LP and the display panel OP.

  The illuminometer 101 has a device that can measure the illuminance of external light. The illuminometer 101 can include, for example, a photodetector using a photodiode.

  The threshold detection circuit 102 has a function of acquiring the illuminance measured by the illuminance meter 101, determining the gradation of the display device according to the illuminance, and transmitting information on the gradation to the timing controller 103.

  The timing controller 103 has a function of allocating a digital video source (also referred to as video data or digital video data) serially transferred from the outside to each source line. In addition, the timing controller 103 determines each source line based on the allocated digital video data, the gradation information sent from the threshold detection circuit 102, and the display mode driven by the display unit 110. 1 has a function of generating an input signal to the digital-analog conversion circuit 200. The display mode indicates a driving method of the display unit 110, and includes a reflection mode (displays an image on the display panel LP), a transmission mode (displays an image on the display panel OP), and a pause mode (digital / analog conversion circuit 200). Stops the operation of.)). Further, the display mode may include a method (reflection + transmission mode) in which an image is displayed on both the display panel LP and the display panel OP. The digital-analog conversion circuit 200 will be described later.

  Note that there may be a plurality of input signals to the digital-analog conversion circuit 200 generated by the timing controller 103. Therefore, in FIG. 1, a plurality of wirings that electrically connect the timing controller 103 and the digital-analog conversion circuit 200 are illustrated.

  The circuit 104 includes a plurality of digital-analog conversion circuits 200 (denoted as DAC in FIG. 1). Each of the plurality of digital-analog conversion circuits 200 includes a plurality of terminals IT, a terminal OT, and a terminal LT.

  The plurality of terminals IT are electrically connected to the timing controller 103, and a signal generated by the timing controller 103 described above is transmitted to the terminal IT. The terminal OT is electrically connected to the display panel OP of the display unit 110, and the terminal LT is electrically connected to the display panel LP.

  The number of the digital / analog conversion circuits 200 included in the circuit 104 is determined by the number of pixel circuits connected to one scanning line (also referred to as a gate line or simply a wiring) in the display panel LP.

  Further, the number of pixel circuits in the row direction and the number of pixel circuits in the column direction in the display panel OP are equal to the number of pixel circuits in the row direction and the number of pixel circuits in the column direction in the display panel LP, respectively. That is, the number of digital-analog conversion circuits included in the circuit 104 is also determined by the number of pixel circuits selected for one selection signal line in the display panel OP.

<Determination method of gradation>
Next, a method for determining the gray level of the display device in accordance with the illuminance of external light using the threshold detection circuit 102 and the circuit 104 will be described.

  FIG. 2 is a diagram for explaining the relationship among the value of digital video data, the threshold value, the emission intensity of the display panel OP that represents the display image, and the reflection intensity of the display panel LP that represents the display image. FIG. Here, digital video data is described as 6 bits as an example.

  FIG. 2A schematically shows a digital video data signal. MSB indicates the most significant bit, LSB indicates the least significant bit, and th indicates a threshold value. The threshold value is a value corresponding to the illuminance measured by the illuminometer 101. The threshold value is determined by the threshold value detection circuit 102 and transferred to the timing controller 103 as gradation information.

  The timing controller 103 obtains a threshold value from the threshold value detection circuit 102, thereby providing a threshold value for the digital video data transferred from the outside to the timing controller 103. The digital video data is divided into an upper bit length and a lower bit length with a threshold as a boundary. The upper bit length contributes to the light emission intensity of the display panel OP, and the lower bit length contributes to the reflection intensity of the display panel LP, thereby determining the gradation of the display image.

  First, consider the case where the environment where the display device is used is dark. When the outside light is dark, the reflection intensity of the display panel LP becomes weak, so that the emission intensity of the display panel OP needs to be increased. Here, it is assumed that 2 bits are obtained as a threshold value by the illuminometer 101 and the threshold value detection circuit 102 in a dark environment (FIG. 2 (B-1)). That is, as described above, the upper bit length of 4 bits contributes to the emission intensity of the display panel OP, and the lower bit length of 2 bits contributes to the reflection intensity of the display panel LP.

  In one aspect of the present invention, when an image is displayed on the display panel OP, the value of the upper 4 bits is referred to, so the lower 2 bits that are not used are set to “00”. That is, when an image is displayed on the display panel OP, the digital data reflecting the threshold value is data in which the upper 4 bits are “0000” to “1111” and the lower 2 bits are “00”. It becomes. Further, when displaying an image on the display panel LP, since the lower 2 bits are referred to, the upper 4 bits that are not used may be ignored. Further, the value of the upper 4 bits may be appropriately determined as any value of “0000” to “1111” depending on the situation, depending on the case or as necessary.

  FIG. 2B-2 is a graph showing the relationship between the luminance of the display device and the value of the digital video data. The area without the hatching pattern indicates the light emission intensity of the display panel OP, and the area with the hatching pattern indicates the reflection intensity of the display panel LP.

  When the upper bit length is 4 bits, the upper bits have values from “0000” to “1111”. That is, the light emission intensity of the display panel OP is expressed in 16 levels from the upper bit “0000” to the upper bit “1111”. Further, from FIG. 2B-2, it is assumed that the light emission intensity of the display panel OP increases in order from the upper bit “0000”. The upper bit “0000” is not shown in FIG. 2B-2 because the emission intensity of the display panel OP is 0.

  The lower bit length has a value from “00” to “11”. That is, the reflection intensity of the display panel LP is expressed in four levels from the lower bit “00” to the lower bit “11”. The luminance shown in FIG. 2B-2 is shown by adding the four levels of reflection intensity of the display panel LP to each of the sixteen levels of emission intensity of the display panel OP.

  Incidentally, the gradation of the display panel LP is determined by the potential applied to the liquid crystal element included in the display panel LP, and the gradation of the display panel OP is determined by the potential applied to the gate of the driving transistor included in the display panel OP. That is, the gray levels of the display panel LP and the display panel OP can be determined by the potential. However, the potential used for gradation adjustment often differs depending on the display panel LP or the display panel OP. Therefore, in one embodiment of the present invention, two kinds of gradation adjustment potentials to be supplied to the semiconductor device 100 are prepared.

  The power supply potential for gradation adjustment of the display panel OP is Voel, and the power supply potential for gradation adjustment of the display panel LP is Vrlcd. In the display panel OP, as described above, the gradation is determined by the light emission intensity in 16 steps. Therefore, the potential applied to the display element of the display panel OP is a potential obtained by dividing the power supply potential Voel for gradation adjustment into 16 steps. (Fig. 2 (B-3)). In the display panel LP, the gradation is determined by the light emission intensity in four stages. Therefore, the potential applied to the display element of the display panel LP is any of the potentials obtained by dividing the power supply potential Vrlcd for gradation adjustment into four stages. It becomes. 2B-3, the potential when the upper 4 bits are “0000” is described as 0 potential, and the potential when the lower 2 bits are “00” is described as 0 potential. Then, those 0 potentials may be described as GND potentials.

  Next, consider a case where the environment in which the display device is used is bright. When the outside light is bright, the reflection intensity of the display panel LP is increased, so that the emission intensity of the display panel OP needs to be decreased. Here, it is assumed that 4 bits are obtained as a threshold value by the illuminometer 101 and the threshold value detection circuit 102 in an environment where the outside light is bright (FIG. 2 (C-1)). That is, 2 bits of the upper bit length contribute to the light emission intensity of the display panel OP, and 4 bits of the lower bit length contribute to the reflection intensity of the display panel LP.

  Note that in one aspect of the present invention, when an image is displayed on the display panel OP, the value of the upper 2 bits is referred to, so the lower 4 bits that are not used are set to “0000”. That is, when an image is displayed on the display panel OP, the digital data reflecting the threshold value is any one of “000000”, “010000”, “100000”, and “110000”. Further, when displaying an image on the display panel LP, the lower 4 bits are referred to, so the upper 2 bits that are not used are set to “00”. That is, when an image is displayed on the display panel LP, the digital data reflecting the threshold value is any one of “000000” to “001111”.

  FIG. 2C-2 is a graph showing the relationship between the luminance of the display device and the value of the digital video data, as in FIG. 2B-2.

  When the upper bit length is 2 bits, the upper bits have values from “00” to “11”. That is, the light emission intensity of the display panel OP is expressed in four stages from the upper bit “00” to the upper bit “11”. Further, from FIG. 2C-2, it is assumed that the light emission intensity of the display panel OP increases in order from the upper bit “00”. The upper bit “00” is not shown in FIG. 2C-2 because the emission intensity of the display panel OP is 0.

  The lower bit length has a value from “0000” to “1111”. That is, the reflection intensity of the display panel LP is expressed in 16 levels from the lower bit “0000” to the lower bit “1111”. FIG. 2C-2 shows the 16-stage reflection intensity of the display panel LP added to each of the 4-stage emission intensities of the display panel OP.

  That is, the potential applied to the display element of the display panel OP is one of potentials obtained by dividing the power supply potential Voel for gradation adjustment into four stages (FIG. 2 (C-3)). In the display panel LP, the potential applied to the display element of the display panel LP is any one of the potentials obtained by dividing the power supply potential Vrlcd for gradation adjustment into 16 stages. Note that in FIG. 2C-3, the potential when the upper 2 bits are “00” is described as 0 potential, and the potential when the lower 4 bits are “0000” is described as 0 potential. Then, those 0 potentials may be described as GND potentials.

<Configuration Example of Digital / Analog Conversion Circuit 200>
Next, a configuration example of the digital-analog conversion circuit 200 will be described. As described above, the digital-analog conversion circuit 200 needs to be a digital-analog conversion circuit that can generate a gradation signal dedicated to the display panel OP and a gradation signal dedicated to the display panel LP.

  FIG. 3 shows a digital / analog conversion circuit 200 </ b> A as a configuration example of the digital / analog conversion circuit 200. The digital-analog conversion circuit 200A is an example of a capacitance array type digital-analog conversion circuit, and has a function of converting an n-bit (n is an integer of 2 or more) digital signal into an analog signal. The digital-analog conversion circuit 200A includes an operational amplifier OP1, an operational amplifier OP2, a switch OSW, a switch LSW, a switch OSWG, a switch LSWG, a circuit 201, a circuit 202, and a circuit 203. The switch OSW, the switch LSW, the switch OSWG, and the switch LSWG are switches that electrically open and close between two terminals, respectively.

  The circuit 201 includes switches SWa [1] to SWa [n] and capacitors C [0] to C [n]. Note that each of the switches SWa [1] to SWa [n] is a switch that electrically opens and closes between two terminals, like the switch OSW, the switch LSW, the switch OSWG, and the switch LSWG. Note that the ratio of the capacitance values of the capacitive element C [0], the capacitive element C [1], and the capacitive element C [j] (j is an integer of 2 to n) satisfies the following expression. .

  One of the pair of electrodes of the capacitor C [0] is electrically connected to one terminal of the switch SWa [1], and the other of the pair of electrodes of the capacitor C [0] is electrically connected to the wiring GNDL. It is connected.

  The other terminal of the switch SWa [1] is electrically connected to one of the pair of electrodes of the capacitor C [1].

  One terminal of the switch SWa [j] (j is an integer of 2 to n) is electrically connected to the other terminal of the switch SWa [j−1], and the other terminal of the switch SWa [j]. The terminal is electrically connected to one of the pair of electrodes of the capacitor C [j].

  The non-inverting input terminal of the operational amplifier OP1 is electrically connected to one terminal of the switch OSWG, the other terminal of the switch SWa [n], and one of the pair of electrodes of the capacitor C [n]. The output terminal of the operational amplifier OP1 is electrically connected to one terminal of the switch OSW, and the other terminal of the switch OSW is electrically connected to the terminal OT. The other terminal of the switch OSWG is electrically connected to the wiring GNDL.

  The inverting input terminal of the operational amplifier OP1 is electrically connected to the output terminal of the operational amplifier OP1. That is, the connection configuration of the operational amplifier OP1 is a configuration of a voltage follower circuit.

  The non-inverting input terminal of the operational amplifier OP2 is electrically connected to one terminal of the switch LSWG, one terminal of the switch SWa [1], and one of the pair of electrodes of the capacitor C [0]. The output terminal of the operational amplifier OP2 is electrically connected to one terminal of the switch LSW, and the other terminal of the switch LSW is electrically connected to the terminal LT. The other terminal of the switch LSWG is electrically connected to the wiring GNDL.

  The inverting input terminal of the operational amplifier OP2 is electrically connected to the output terminal of the operational amplifier OP2. That is, the connection configuration of the operational amplifier OP2 is a configuration of a voltage follower circuit.

  The circuit 202 includes switches SE [1] to SE [n]. Each of the switches SE [1] to SE [n] has first to third terminals, and has a function of electrically connecting the first terminal to either the second terminal or the third terminal. Have. That is, each of the switches SE [1] to SE [n] has a selector function.

  The first terminal of the switch SE [1] is electrically connected to the other of the pair of electrodes of the capacitor [1], and the second terminal of the switch SE [1] is electrically connected to the wiring GNDL. . The first terminal of the switch SE [j] is electrically connected to the other of the pair of electrodes of the capacitor [j], and the second terminal of the switch SE [j] is electrically connected to the wiring GNDL. .

  The circuit 203 includes switches SWb [1] to SWb [n + 1]. The switches SWb [1] to SWb [n + 1] are electrically opened and closed between the two terminals, like the switches SWa [1] to SWa [n], the switch OSW, the switch LSW, the switch OSWG, and the switch LSWG. It is a switch that performs.

  One terminal of the switch SWb [1] is electrically connected to the wiring VLL, and the other terminal of the switch SWb [1] is electrically connected to the third terminal of the switch SE [1]. One terminal of the switch SWb [j] is electrically connected to the other terminal of the switch SWb [j-1], and the other terminal of the switch SWb [j] is connected to the third terminal of the switch SE [j]. Electrically connected. One terminal of the switch SWb [n + 1] is electrically connected to the other terminal of the switch SWb [n], and the other terminal of the switch SWb [n + 1] is electrically connected to the wiring VOL.

  The wiring VOL is a wiring for applying a potential for the display panel OP, and the wiring VLL is a wiring for applying a potential for the display panel LP. The wiring GNDL is a wiring for applying a ground potential (sometimes referred to as a GND potential).

  3 shows an operational amplifier OP1, an operational amplifier OP2, a terminal OT, a terminal LT, a switch OSW, a switch LSW, a switch OSWG, a switch LSWG, a wiring GNDL, a wiring VOL, a wiring VLL, a circuit 201, a circuit 202, a circuit 203, and a capacitor. Element C [0], Capacitor C [1], Capacitor C [j], Capacitor C [n], Switch SWa [1], Switch SWa [j], Switch SWa [n], Switch SE [1] , The switch SE [j], the switch SE [n], the switch SWb [1], the switch SWb [j], the switch SWb [n], and the switch SWb [n + 1] are only illustrated, and other elements, circuits, and wirings are shown. , And their reference numerals are omitted.

  Note that the digital-to-analog converter circuit according to one embodiment of the present invention is not limited to the digital-to-analog converter circuit illustrated in FIG. Depending on the situation, the configuration of the digital-analog conversion circuit 200A can be changed depending on circumstances or necessity. For example, when the parasitic capacitance between one terminal of the switch SWa [1] and the non-inverting input terminal of the operational amplifier OP2 corresponds to the capacitive element C [0], the capacitive element C [0] is not provided in the circuit 201. May be. Further, for example, depending on the size of the parasitic capacitance on the non-inverting input terminal side of the operational amplifier OP1 and the operational amplifier OP2, it is not necessary to satisfy the formula (E1), and the capacitance elements C [0] to C [n] What is necessary is just to design an electrostatic capacitance as an appropriate value.

  Note that as a switch such as the switch OSWG, the switch LSWG, the switch SWa [1] to the switch SWa [n], the switch SWb [1] to the switch SWb [n + 1], an electrical switch, a mechanical switch, or a MEMS element (Micro Electro (Mechanical Systems) may be used. For example, a transistor is preferably used as the electrical switch. In particular, when an n-channel transistor is used, the transistor includes an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin) and zinc in a channel formation region. desirable. That is, an OS transistor is desirable. By using the OS transistor, the off-state current of the transistor can be extremely small; thus, leakage of charges held in the capacitor C [0] to the capacitor C [n] can be prevented.

<Operation Example of Digital / Analog Conversion Circuit 200>
Next, an operation example of the digital-analog conversion circuit 200 will be described.

  In this operation example, the operation of the digital-analog conversion circuit shown in FIG. 4A, not the digital-analog conversion circuit 200A, will be described in order to avoid complicated explanation.

  The digital-analog conversion circuit 200B is an example of a circuit that converts a 6-bit digital signal into an analog signal. That is, the digital-analog conversion circuit 200B sets n to 6 in the digital-analog conversion circuit 200A. Therefore, the circuit 201 includes the capacitor C [0] to the capacitor C [6].

  Further, the digital-analog conversion circuit 200B in the digital-analog conversion circuit 200A includes the switch OSW as the transistor OTr, the switch LSW as the transistor LTr, and the switches SWa [1] to SWa [n] as the transistors Tra [1] to The transistor Tra [6], the switch OSWG is the transistor OTrG, the switch LSWG is the transistor LTrG, and the switches SWb [1] to SWb [n + 1] are the transistors Trb [1] to Trb [7].

  Note that a wiring is connected to the gate of each transistor in order to control the conduction and non-conduction of the above-described transistors. Specifically, the gate of the transistor OTr is electrically connected to the wiring OSL, and the gate of the transistor LTr is electrically connected to the wiring LSL. In addition, the gates of the transistors Tra [1] to Tra [6] are electrically connected to the wirings a [1] to a [6], respectively. The gate of the transistor OTrG is electrically connected to the wiring OGL, and the gate of the transistor LTrG is electrically connected to the wiring LGL. The gates of the transistors Trb [1] to Trb [7] are electrically connected to the wirings b [1] to b [7], respectively.

  In the digital-analog conversion circuit 200B, in the digital-analog conversion circuit 200A, the switches SE [1] to SE [6] are changed to selectors SC [1] to SC [6]. Further, the first to third terminals of the switch SE [J] (J is an integer of 1 to 6) are referred to as a terminal SCT1, a terminal SCT2, and a terminal SCT3, respectively.

  The selector SC [J] will be described with reference to FIG. The selector SC [J] includes an analog switch SWc1, an analog switch SWc2, and an inverter circuit INV.

  The terminal SCT1 is electrically connected to the first input / output terminal of the analog switch SWc1 and the first input / output terminal of the analog switch SWc2. The terminal SCT2 is electrically connected to the second input / output terminal of the analog switch SWc2. The terminal SCT3 is electrically connected to the second input / output terminal of the analog switch SWc1. The wiring c [J] is electrically connected to the first control terminal of the analog switch SWc1, the first control terminal of the analog switch SWc2, and the input terminal of the inverter circuit INV. The output terminal of the inverter circuit INV is electrically connected to the second control terminal of the analog switch SWc1 and the second control terminal of the analog switch SWc2.

  That is, from the circuit diagram of the selector SC [J] shown in FIG. 4B, by applying a high-level potential to the wiring c [J], the analog switch SWc1 is in a conductive state, and in addition, the analog switch SWc2 is in a nonconductive state. It becomes. Further, by applying a low-level potential to the wiring c [J], the analog switch SWc1 is turned off, and the analog switch SWc2 is turned on.

  Note that the configuration of the selector SC [J] is not limited to the circuit diagram shown in FIG. 4B, and the analog switch SWc1 and / or the analog switch SWc2 may be omitted.

  Note that when the series of operations of the digital-analog conversion circuit 200B and the selector SC [J] in FIGS. 4A and 4B are performed, the wiring OSL, the wiring LSL, the wiring OGL, the wiring LGL, and the wiring a [1] To wiring a [6], wiring b [1] to wiring b [7], and wiring c [1] to wiring c [6] are transmitted from the timing controller 103. That is, the input signal generated by the timing controller 103 based on the digital video data, the threshold value sent from the threshold value detection circuit 102, and the display mode driven by the display unit 110 is Sent to the wiring. Therefore, the wiring OSL, the wiring LSL, the wiring OGL, the wiring LGL, the wiring a [1] to the wiring a [6], the wiring b [1] to the wiring b [7], and the wiring c [1] to the wiring c [6]. Each is electrically connected to a plurality of terminals IT.

  Next, an operation example of the digital-analog conversion circuit 200B will be described using the timing chart shown in FIG.

  The timing chart illustrated in FIG. 5 includes the wiring OSL, the wiring LSL, the wiring OGL, the wiring LGL, the wiring a [1] to the wiring a [6], the wiring b [1] to the wiring b [7], and the wiring c [1] to A change in potential of the wiring c [6], the terminal OT, and the terminal LT is shown. The wiring OGL, the wiring LGL, the wiring a [1] to the wiring a [6], the wiring b [1] to the wiring b [7], and the wiring c [1] to the wiring c [6] have high-level potentials (see FIG. 5, one of a high level potential and a low level potential (designated as Low in FIG. 5) is applied. Note that the potential applied to the wiring OGL, the wiring LGL, the wiring a [1] to the wiring a [6], the wiring b [1] to the wiring b [7], and the wiring c [1] to the wiring c [6] is It is not limited to the high level potential and the low level potential, and may be an analog potential.

  In addition, the wiring OSL, the wiring LSL, the wiring OGL, the wiring LGL, the wiring a [1] to the wiring a [6], the wiring b [1] to the wiring b [7], and the wiring c [1] to the wiring c [6]. Are electrically connected to the timing controller 103 via a plurality of terminals IT. That is, the wiring OSL, the wiring LSL, the wiring OGL, the wiring LGL, the wiring a [1] to the wiring a [6], the wiring b [1] to the wiring b [7], and the wiring c [1] to the wiring c [6]. Includes a digital video data input to the digital-analog conversion circuit 200B, a threshold value of the digital video data corresponding to the illuminance of external light, a signal for selecting a display mode driven by the display unit 110, and a digital-analog conversion circuit 200B. A signal is sent to initialize.

<< Initialization >>
First, the initialization operation will be described. By this operation, each potential held in the capacitor C [0] to the capacitor C [6] included in the digital-analog converter circuit 200B is set to zero potential. In the timing chart of FIG. 5, the period is described as Init, and the initialization operation is performed in the period from time T0 to time T1.

  From time T0 to time T1, a low-level potential is applied to each of the wiring OSL and the wiring LSL. As a result, each of the transistor OTr and the transistor LTr is turned off, and signals are not output from the terminal OT and the terminal LT.

  From time T0 to time T1, a high-level potential is applied to each of the wiring OGL and the wiring LGL. As a result, each of the transistor OTrG and the transistor LTrG becomes conductive, and the GND potential is applied to each of the non-inverting input terminal of the operational amplifier OP1 and the non-inverting input terminal of the operational amplifier OP2.

  Since the connection configuration of the operational amplifier OP1 and the operational amplifier OP2 is a voltage follower circuit configuration, the potential output to the output terminal is the potential input to the non-inverting input terminal.

  In addition, when each of the transistor OTrG and the transistor LTrG is turned on, the GND potential is also applied to one of the pair of electrodes of the capacitor C [0]. Since the other side of the pair of electrodes of the capacitor C [0] is connected to the wiring GNDL, the potential held by the capacitor C [0] is zero.

  In addition, from time T0 to time T1, a high-level potential is applied to each of the wirings a [1] to a [6]. Accordingly, the transistors Tra [1] to Tra [6] are turned on, and the GND potential is applied to one of the pair of electrodes of the capacitors C [1] to C [6].

  Further, a low-level potential is applied to each of the wirings c [1] to c [6] from time T0 to time T1. Thus, the terminals SCT1 and SCT2 of the selectors SC [1] to SC [6] are electrically connected. Accordingly, the GND potential is applied from the wiring GNDL to the other of the pair of electrodes of the capacitor C [1] to the capacitor C [6].

  Therefore, the potential held by each of the capacitor C [1] to the capacitor C [6] is zero potential.

  In addition, from time T0 to time T1, a low-level potential is applied to each of the wirings b [1] to b [7]. Accordingly, each of the transistors Trb [1] to Trb [7] is turned off, so that no potential is applied from the wiring VOL and the wiring VLL to the digital-analog conversion circuit 200B.

  Note that since the terminals SCT1 to SCT3 of the selectors SC [1] to SC [6] are not electrically connected from the time T0 to the time T1, the selectors SC [1] to SC [6] A potential from the wiring VOL or the wiring VLL may be applied to each of the terminals SCT3. However, when all of the transistors Trb [1] to Trb [7] are turned on, current may flow between the wiring VOL and the wiring VLL, which may increase power consumption. In order to prevent this, at least one of the transistors Trb [1] to Trb [7] needs to be in a non-conductive state from time T0 to time T1.

<< OEL mode >>
Next, an operation example of the digital-analog conversion circuit 200B when displaying an image on the display panel OP after performing the initialization operation will be described. In the period from time T1 to time T2, a threshold corresponding to the external light is determined for the digital video data allocated to each source line by the timing controller 103. Thereby, the gradation of the digital video data is determined. Then, a digital signal based on the threshold value, digital video data, and display mode (self-emission mode or OEL mode) is sent to the digital-analog conversion circuit 200B. By converting the digital signal sent to the digital-analog conversion circuit 200B into an analog signal and sending it to the display panel OP, an image whose gradation has been adjusted can be displayed on the display panel OP.

  For example, the digital video data allocated to the target source line at time T1 is “110101”. Further, the threshold value determined by the external light intensity is set to the lower 2 bits. That is, since the upper 4 bits of the digital video data contribute to the emission intensity of the display panel OP, the analog value output from the terminal OT of the digital-analog conversion circuit 200B electrically connected to the source line is digital. The video data “110100” is analog-converted.

  From time T1 to time T2, a high level potential is applied to the wiring OSL and a low level potential is applied to the wiring LSL. As a result, the transistor OTr is turned on and the transistor LTr is turned off.

  From time T1 to time T2, a low level potential is applied to each of the wiring OGL and the wiring LGL. As a result, each of the transistor OTrG and the transistor LTrG is turned off.

  In addition, from time T1 to time T2, a high-level potential is applied to each of the wirings a [1] to a [6]. Accordingly, the transistors Tra [1] to Tra [6] are turned on.

  In addition, from time T1 to time T2, a low-level potential is applied to the wiring b [1], and a high-level potential is applied to each of the wirings b [2] to b [7]. Accordingly, the transistor Trb [1] is turned off, and the transistors Trb [2] to Tra [7] are turned on. Therefore, the potential Voel is applied from the wiring VOL to the terminals SCT3 of the selectors SC [1] to SC [7].

  Further, from time T1 to time T2, a potential corresponding to each bit of the digital video data “110100” is applied to each of the wirings c [1] to c [6]. Specifically, when the J-th bit is “1”, a high-level potential is applied to the wiring c [J], and when the J-th bit is “0”, the wiring c [J] is applied to the wiring c [J]. A low level potential is applied. That is, a high level potential is applied to the wiring c [3], the wiring c [5], and the wiring c [6], and a low level is applied to the wiring c [1], the wiring c [2], and the wiring c [4]. A level potential will be applied.

  Accordingly, the selector SC [3], the selector SC [5], and the selector SC [6] are electrically connected between the terminal SCT1 and the terminal SCT3 and are not electrically connected between the terminal SCT1 and the terminal SCT2. Thus, the selector SC [1], the selector SC [2], and the selector SC [4] are electrically disconnected between the terminal SCT1 and the terminal SCT3 and electrically connected between the terminal SCT1 and the terminal SCT2, respectively. Become. Accordingly, the other of the pair of electrodes of the capacitive element C [3], the capacitive element C [5], and the capacitive element C [6] includes a selector SC [3], a selector SC [5], and a selector SC [6]. The potential Voel input to each terminal SCT3 is applied. At the same time, the other of the pair of electrodes of the capacitor C [1], the capacitor C [2], and the capacitor C [4] is connected to the selector SC [1], the selector SC [2], The GND potential is applied via the terminals SCT1 to SCT3 of the selector SC [4].

  By the way, the ratio of the capacitance values of the capacitive elements C [0] to C [6] is C [0]: C [1]: C [2]: C [3]: C [4]: C [5]: C [6] = 1: 1: 2: 4: 8: 16: 32.

  Further, the connection configuration of the digital-analog conversion circuit 200B from time T1 to time T2 is equivalent to the circuit shown in FIG. That is, the potential applied to the non-inverting input terminals of the operational amplifier OP1 and the operational amplifier OP2 can be obtained from the above-described capacitance ratio and the connection configuration in FIG. The sum of the capacitive element C [3], the capacitive element C [5], and the capacitive element C [6], and the capacitive element C [0], capacitive element C [1], capacitive element C [2], and capacitive element C Since the ratio of the sum of [4] is 52:12, the potential of one of the pair of electrodes of the capacitive element C [1], the capacitive element C [2], and the capacitive element C [4] is 52 Voel / (52 + 12) = 13 Voel / 16. Therefore, the potential applied to the non-inverting input terminals of the operational amplifier OP1 and the operational amplifier OP2 is 13 Voel / 16. However, in this calculation, the influence of the parasitic resistance at each non-inverting input terminal of the operational amplifier OP1 and the operational amplifier OP2 is made extremely small.

  Therefore, the potential 13Voel / 16 is output from the terminal OT. At this time, since the transistor LTr is in a non-conductive state, no signal is output from the terminal LT.

  In the above description, the case where the value of the digital video data is “110101” and the threshold value is 2 bits has been described. Here, the potential output from the terminal OT when the digital video data is an arbitrary value and the threshold value is 2 bits will be described. Also in this case, all the bits below the threshold value of the digital video data are “0”, so that a low level potential is applied to each of the wiring c [1] and the wiring c [2] corresponding to the lower 2 bits. Is done. Since the upper 4 bits (values of 3 bits to 6 bits) take any one of 16 values “0000” to “1111”, each of the wirings c [3] to c [6] A potential corresponding to the value of each bit is input (specifically, as described above, when the J-th bit is “1”, a high-level potential is applied to the wiring c [J]. When the bit is “0”, a low-level potential is applied to the wiring c [J].) In other words, by setting the threshold value to 2 bits, the power supply potential Voel can be divided equally into 16 levels, and the potential output from the terminal OT can be any of the 16 levels depending on the value of the upper 4 bits. It is decided to one. Specifically, according to the values of “0000” to “1111” of the upper 4 bits, the GND potential, Voel / 16, Voel / 8, Voel 3/16, Voel / 4, Voel · 5/16, Voel, respectively. 3/8, Voel 7/16, Voel / 2, Voel 9/16, Voel 5/8, Voel 11/16, Voel 3/4, Voel 13/16, Voel 7/8 , Voel · 15/16 is output from the terminal OT.

  As described above, by performing the operation from the time T1 to the time T2, it is possible to transmit a gradation signal corresponding to the external light environment to the display panel OP.

  Note that a high-level potential is applied to each of the wirings a [1] to a [6], the wiring OGL, and the wiring LGL from the time T2 to the time T3. In addition, a low-level potential is applied to each of the wiring OSL, the wiring LSL, the wirings b [1] to b [7], and the wirings c [1] to c [6]. That is, initialization can be performed again by setting the potential of each wiring described above to the same potential applied from time T0 to time T1.

  Further, when the above-described gradation signal is supplied to the pixel included in the display panel OP, the channel formation region of the selection transistor of the pixel is indium, element M (the element M is aluminum, gallium, yttrium, or tin), or zinc. It is preferable to have an oxide containing at least one. That is, an OS transistor is desirable. By using the OS transistor, the off-state current of the selection transistor can be extremely reduced, so that the grayscale signal written to the pixel can be held for a long time. That is, in the OEL mode, the number of rewrites of the gradation signal to the pixels of the display panel OP by the digital-analog conversion circuit 200B can be reduced.

  In addition, since the gradation signal written to the pixel can be held for a long time, the pixel of the display panel LP is separated from the display panel OP before the gradation signal is rewritten to the next display panel OP. Can be sent. As a result, it is possible to simultaneously display an image having a gradation corresponding to the ambient light environment from both the display panel OP and the display panel LP.

<< RLCD mode >>
Next, an operation example of the digital-analog conversion circuit 200B when displaying an image on the display panel LP will be described. In the period from time T3 to time T4, a threshold corresponding to the external light is determined for the digital video data allocated to each source line by the timing controller 103. Thereby, the gradation of the digital video data is determined. Then, a digital signal based on the threshold value, the digital video data, and the display mode (reflection mode or RLCD mode) is sent to the digital-analog conversion circuit 200B. By converting the digital signal sent to the digital-analog conversion circuit 200B into an analog signal and sending it to the display panel LP, an image whose gradation has been adjusted can be displayed on the display panel LP.

  For example, the digital video data sent to the source line of interest at time T3 is “110101”, which is the same as at time T1. Further, the threshold value determined by the external light intensity is also set to the lower 2 bits similar to the time T1. That is, since the lower 2 bits of the digital video data contribute to the reflection intensity of the display panel LP, the analog value output from the terminal LT of the digital-analog conversion circuit 200B electrically connected to the source line is “ “01” is converted into an analog signal.

  At time T3, a low-level potential is applied to each of the wiring OGL and the wiring LGL. As a result, each of the transistor OTrG and the transistor LTrG is turned off.

  At time T4, a low-level potential is applied to the wiring a [3], and a high-level potential is applied to each of the wiring a [1] and the wiring a [2]. Accordingly, the transistor Tra [3] is turned off, and the transistors Tra [1] and Tra [2] are turned on. Note that each of the transistor Tra [4], the transistor Tra [5], and the transistor Tra [6] may be in a conductive state or a non-conductive state. That is, the potential applied to the wiring a [4] to the wiring a [6] may be either a high-level potential or a low-level potential (in the timing chart of FIG. 5, the wiring a [4] to the wiring a [6). ] Is a low level potential.)

  At time T5, a low-level potential is applied to the wiring b [3], and a high-level potential is applied to each of the wiring b [1] and the wiring b [2]. Accordingly, the transistor Trb [3] is turned off and the transistors Trb [1] and Trb [2] are turned on. Note that each of the transistor Trb [4], the transistor Trb [5], the transistor Trb [6], and the transistor Trb [7] may be either in a conductive state or a non-conductive state. That is, the potential applied to the wirings b [4] to b [7] may be either a high-level potential or a low-level potential (in the timing chart of FIG. 5, the wirings b [4] to b [7] ] Is a low level potential.)

  In addition, at time T5, a potential corresponding to each bit of the digital video data “01” is applied to each of the wirings c [1] to c [6]. Specifically, when the J-th bit is “1”, a high-level potential is applied to the wiring c [J], and when the J-th bit is “0”, the wiring c [J] is applied to the wiring c [J]. A low level potential is applied. That is, a high level potential is applied to the wiring c [1], and a low level potential is applied to the wiring c [2]. Note that the potential applied to the wirings c [3] to c [6] corresponding to the upper 4 bits may be either a high-level potential or a low-level potential (in the timing chart of FIG. 5, the wiring c [3 ] To the wiring c [6] are set to a low level potential).

  As a result, the selector SC [1] is electrically connected between the terminals SCT1 and SCT3 and is not electrically connected between the terminals SCT1 and SCT2, and the selector SC [2] to the selector SC [6]. The terminal SCT1 and the terminal SCT3 are electrically disconnected, and the terminal SCT1 and the terminal SCT2 are electrically connected. Therefore, the potential Vrlcd input to the terminal SCT3 of the selector SC [1] is applied to the other of the pair of electrodes of the capacitor C [1]. At the same time, the potential GND input to the terminals SCT2 of the selectors SC [2] to SC [6] is applied to the other of the pair of electrodes of the capacitors C [2] to C [6]. Is done.

  Further, at time T5, a low level potential is applied to the wiring OSL, and a high level potential is applied to the wiring LSL. Accordingly, the transistor OTr is turned off and the transistor LTr is turned on.

  Further, the connection configuration of the digital-analog conversion circuit 200B from time T5 to time T6 is equivalent to the circuit shown in FIG. That is, the potential applied to the non-inverting input terminals of the operational amplifier OP1 and the operational amplifier OP2 can be obtained from the above-described capacitance ratio and the connection configuration in FIG. Since the ratio of the capacitive element C [1] to the sum of the capacitive element C [0] and the capacitive element C [2] is 1: 3, the capacitive element C [0] and the capacitive element C [2] One potential of each pair of electrodes is Vrlcd / (1 + 3) = Vrlcd / 4. Therefore, the potential applied to the non-inverting input terminal of the operational amplifier OP2 is Vrlcd / 4. However, in this calculation, the influence of the parasitic resistance at each non-inverting input terminal of the operational amplifier OP2 is made extremely small.

  Therefore, the potential Vrlcd / 4 is output from the terminal LT. At this time, since the transistor OTr is in a non-conductive state, no signal is output from the terminal OT.

  In the above description, the case where the value of the digital video data is “110101” and the threshold value is 2 bits has been described. Here, the potential output from the terminal LT when the digital video data is an arbitrary value and the threshold value is 2 bits will be described. In this case as well, the bit value higher than the threshold value of the digital video data may not be referred to. The lower 2 bits below the threshold value take one of the four values “00” to “11”. (Specifically, as described above, when the J-th bit is “1”, a high-level potential is applied to the wiring c [J], and the J-th bit is “ When “0”, the low-level potential is applied to the wiring c [J].) That is, by setting the threshold value to 2 bits, the power supply potential Vrlcd can be equally divided into 4 stages, and the potential output from the terminal LT can be set to any of the 4 stages of height depending on the value of the lower 2 bits. It is decided to one. Specifically, the GND potential, Vrlcd / 4, Vrlcd / 2, and Voel · 3/4 are output from the terminal LT according to the values of “00” to “11” in the lower 2 bits, respectively.

  As described above, by performing the operation from the time T3 to the time T6, it is possible to transmit the gradation signal corresponding to the external light environment to the display panel LP.

  Note that from time T6 to time T7, a high-level potential is applied to each of the wirings a [1] to a [6], the wiring OGL, and the wiring LGL. In addition, a low-level potential is applied to each of the wirings b [1] to b [7] and the wirings c [1] to c [6]. That is, initialization can be performed again by setting the potential of each wiring described above to the same potential applied from time T0 to time T1. At time T4, similarly to time T1, a low-level potential is applied to each of the wirings a [1] to a [6], the wiring OGL, and the wiring LGL, and the wirings b [1] to b [7]. The low level potential is continuously applied to each of the wirings c [1] to c [6].

  In addition, when the grayscale signal described above is supplied to a pixel included in the display panel LP, the channel formation region of the selection transistor of the pixel is indium, element M (the element M is aluminum, gallium, yttrium, or tin), or zinc. It is preferable to have an oxide containing at least one. That is, an OS transistor is desirable. By using the OS transistor, the off-state current of the selection transistor can be extremely reduced, so that the grayscale signal written to the pixel can be held for a long time. That is, in the RLCD mode, the number of rewrites of the gradation signal to the pixels of the display panel LP by the digital-analog conversion circuit 200B can be reduced.

  Further, similar to the contents described in the OEL mode, the gradation signal written to the pixel can be held for a long time. Therefore, before rewriting the gradation information of the next display panel LP, the organic EL panel The gradation information can be rewritten. As a result, it is possible to simultaneously display an image having a gradation corresponding to the ambient light environment from both the display panel OP and the display panel LP.

<Operation method>
Next, an example of an operation method of adjusting the gray level of the display device by measuring the illuminance of external light in the semiconductor device 100 and the display portion 110 illustrated in FIG. 1 will be described.

  FIG. 7 shows a flowchart of the operation method. The operation method includes steps ST1 to ST10, and the gradation of the display device is adjusted by performing the operations of steps ST1 to ST10.

<< Step ST1 >>
In step ST1, the illuminance meter 101 measures the illuminance of external light. For example, when a photo detector using a photodiode is used as the illuminometer 101, the illuminance can be estimated by measuring the amount of current generated.

<< Step ST2 >>
In step ST2, processing for transferring the illuminance measured in step ST1 to the threshold detection circuit 102 is performed. At this time, the illuminance is transferred as analog data or digital data.

<< Step ST3 >>
In step ST3, an operation for acquiring a dynamic range of display luminance when the display unit 110 displays an image is performed. The dynamic range is determined by the threshold detection circuit 102 based on the illuminance data sent in step ST2. In addition, in step ST3, a threshold value of digital video data is acquired based on the dynamic range. Thereby, the upper bit length contributing to the light emission intensity of the display panel OP and the lower bit length contributing to the reflection intensity of the display panel LP are determined.

<< Step ST4 >>
In step ST4, digital video data is input to the timing controller 103 from the outside. In addition, the threshold information acquired in step ST3 is sent to the timing controller 103.

<< Step ST5 >>
In step ST5, the circuit 104 is initialized. Specifically, operations from time T0 to time T1 shown in the timing chart of FIG. 5 are performed by the plurality of digital-analog conversion circuits 200 included in the circuit 104.

<< Step ST6 >>
In step ST6 and step ST7, processing for transmitting a gradation signal to the display panel OP is performed. In step ST6, the timing controller 103 generates a signal for the display panel OP to be input to the circuit 104 based on the threshold value transferred in step ST4 and the digital video data. The signal is converted into an analog value to be input to the display panel OP by the circuit 104. The converted analog value is output to the terminal OT as a gradation signal. Specifically, the operation from time T1 to time T2 shown in the timing chart of FIG. 5 is performed.

<< Step ST7 >>
In step ST7, the gradation signal generated in step ST6 is transmitted to the display panel OP, and the gradation signal is held in the pixels included in the display panel OP. The display panel OP displays an image based on the gradation signal held in each pixel.

<< Step ST8 >>
In step ST8, the circuit 104 is initialized as in step ST5. Specifically, operations from time T2 to time T3 shown in the timing chart of FIG. 5 are performed by the plurality of digital-analog conversion circuits 200 included in the circuit 104.

<< Step ST9 >>
In step ST9 and step ST10, processing for transmitting a gradation signal to the display panel LP is performed. In step ST9, the timing controller 103 generates a signal for the display panel LP to be input to the circuit 104 based on the threshold value transferred in step ST4 and the digital video data. The signal is converted into an analog value to be input to the display panel LP by the circuit 104. The converted analog value is output to the terminal LT as a gradation signal. Specifically, the operation from time T3 to time T6 shown in the timing chart of FIG. 5 is performed.

<< Step ST10 >>
In step ST10, the gradation signal generated in step ST9 is transmitted to the display panel LP, and the gradation signal is held in the pixels included in the display panel LP. The display panel LP displays an image based on the gradation signal held in each pixel.

  The operation prior to step ST10 returns to step ST1, measures the illuminance again with the illuminometer, and updates the images and gradations displayed on the display panel OP and the display panel LP.

  The operation method of one embodiment of the present invention is not limited to the above-described steps ST1 to ST10. In this specification and the like, the processes shown in the flowchart are classified by function and shown as steps independent of each other. However, in actual processing or the like, it is difficult to separate the processing shown in the flowchart for each function, and a single step may involve a plurality of steps, or a single step may involve a plurality of steps. Therefore, the process shown in the flowchart is not limited to each step described in the specification, and can be appropriately replaced depending on the situation. Specifically, the order of steps, the addition of steps, the deletion, and the like can be performed according to circumstances, depending on circumstances, or as necessary.

  For example, the order in which the grayscale signals are sent to the display panel OP and the display panel LP is not limited to the flowchart of FIG. 7, and step ST6 and step ST7 may be interchanged with step ST9 and step ST10.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 2)
In this embodiment, an example in which the semiconductor device described in Embodiment 1 is applied to a source driver circuit is described.

<Source driver circuit>
FIG. 8 illustrates an example of a source driver circuit according to one embodiment of the present invention. The source driver circuit 300 includes an LVDS receiver 310 (Low Voltage Differential Signaling), a serial / parallel conversion circuit 320, a shift register circuit 330, a latch circuit 340, a level shifter 350, a circuit 360, a capacitance array circuit 370, an external A correction circuit 380, a BGR circuit 390 (Band Gap Reference), a bias generator 400, and a buffer amplifier 500 are included. In FIG. 8, the source driver circuit 300 has two bias generators 400. Note that the source driver circuit 300 is a driver circuit that handles 8-bit video data as an example.

  The LVDS receiver 310 is electrically connected to an external host processor. The LVDS receiver 310 has a function of receiving a video signal from the host processor, and the LVDS receiver 310 converts the differential signal into a single-ended signal and transmits the signal to the serial / parallel conversion circuit 320. In FIG. 8, analog voltage signals DA and DB0, analog voltage signals DA and DB1, analog voltage signals DA and DB2, analog voltage signals DA and DB3, analog voltage signals DA and DB4, analog voltage signals DA and DB5, Analog voltage signals DA and DB6 and analog voltage signals DA and DB7 are input to the LVDS receiver. Note that the LVDS receiver 310 is sequentially operated by the input of the clock signal CLOCK and the clock signal CLOCKB, and the LVDS receiver 310 can be set in a standby state (paused) by the standby signal STBY. The clock signal CLOCKB is an inverted signal of the clock signal CLOCK.

  The serial / parallel conversion circuit 320 is electrically connected to the LVDS receiver 310. The serial / parallel conversion circuit 320 has a function of receiving a single-ended signal from the LVDS receiver 310, and the serial / parallel conversion circuit 320 converts the single-ended signal into a parallel signal to obtain a BUS [127: 0] signal. Send to internal bus.

  The shift register circuit 330 is electrically connected to the serial parallel circuit, and the latch circuit 340 is electrically connected to the shift register circuit 330. The shift register circuit 330 has a function of designating timing for storing data on the internal bus in the latch circuit 340 of each line in synchronization with the serial-parallel conversion circuit 320.

  The level shifter 350 is electrically connected to the latch circuit 340. The level shifter 350 has a function of level-shifting each data when data of all lines is stored in the latch circuit 340.

  The circuit 360 is electrically connected to the level shifter 350. The circuit 360 receives threshold information (denoted as THRESHOLD in FIG. 8) calculated by the illuminometer and the threshold detection circuit described in Embodiment 1, and receives the threshold information and Based on the video data, a signal to be input to a capacitor array circuit 370 to be described later is generated.

  The timing controller 103 described in Embodiment 1 is configured by the LVDS receiver 310, the serial / parallel conversion circuit 320, the shift register circuit 330, the latch circuit 340, and the circuit 360. Note that the portion where the circuit 360 is provided is not limited to the source driver circuit 300 in FIG. For example, the serial / parallel conversion circuit 320 may have the function of the circuit 360 to output a signal based on the threshold information and video data.

  The capacitor array circuit 370 is electrically connected to the circuit 360. The capacitor array circuit 370 and the buffer amplifier 500 described later constitute the digital-analog conversion circuit 200 described in the first embodiment. The capacitor array circuit 370 is supplied with Voel that is a power supply potential to the display panel OP, Vrlcd that is a power supply potential to the display panel LP, and a ground potential GND, and outputs a potential corresponding to the signal to the buffer amplifier 500. That is, the capacitor array circuit 370 has a function of performing digital-analog conversion on each level-shifted data by supplying the potential.

  The buffer amplifier 500 is electrically connected to the capacitor array circuit 370. The buffer amplifier 500 has a function of amplifying the digital / analog-converted data and transmitting the amplified data (described as S [2159: 0] in FIG. 8) to the pixel array.

  The BGR circuit 390 has a function of generating a voltage that serves as a reference for driving the source driver circuit 300. The BGR circuit 390 is electrically connected to one and the other of the bias generator.

  One side of the bias generator 400 is electrically connected to the BGR circuit 390 and the buffer amplifier 500. One of the bias generators 400 has a function of generating a bias voltage for operating the buffer amplifier 500 from a reference voltage generated by the BGR circuit 390. Note that a standby signal STBY is input to one of the bias generators 400 at the same timing as the LVDS receiver 310, and one of the bias generators 400 can be put into a standby state (temporarily stopped) by this signal.

  The other of the bias generator 400 is electrically connected to the external correction circuit 380. The other of the bias generator 400 has a function of generating a bias voltage for operating the external correction circuit 380 from a reference voltage generated by the BGR circuit 390. When there is no need to operate the external correction circuit 380, a standby signal CMSTBY is transmitted to the other of the bias generator 400, and the other of the bias generator 400 is put into a standby state (pauses) by this signal. it can.

  The external correction circuit 380 is electrically connected to a transistor included in the pixel circuit. In the pixel array, when there is a variation in voltage-current characteristics in each pixel transistor, it affects the image projected on the display device, which causes a reduction in display quality of the display device. The external correction circuit 380 has a function of measuring the amount of current flowing through the pixel transistor and making the amount of current flowing through the pixel transistor appropriate according to the amount of current. The external correction circuit 380 receives the set signal CMSET, and the external correction circuit 380 is initialized by this signal. Further, the external correction circuit 380 receives the clock signal CMCLK, and the external correction circuit 380 operates by this signal. In addition, a signal (described as S [719: 0] in FIG. 8) from a transistor included in the pixel circuit is input to the external correction circuit 380, and a reference potential VREF1 that is separately applied to the external correction circuit 380, and a reference A determination relating to image correction is made with reference to the potential VREF2. The result of determination regarding the correction is transmitted as an output signal CMOUT [11: 0] to the image processor outside the source driver circuit 300. The image processor corrects the video data based on the contents of CMOUT [11: 0].

  Note that one embodiment of the present invention is not limited to the source driver circuit 300 illustrated in FIG. 8 and may not have the external correction circuit 380. For example, instead of the external correction circuit 380, a configuration in which a correction circuit is provided for each pixel included in the pixel array may be used.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component will be described with reference to FIGS.

<Electronic parts>
FIG. 9A illustrates an example in which the semiconductor device described in the above embodiment is applied to an electronic component as a memory device. Note that the electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

  A semiconductor device including a transistor, a capacitor, and the like as shown in Embodiment Mode 1 is completed by combining a plurality of detachable components with a printed board through an assembly process (post-process).

  The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step STP1), the back surface of the substrate is ground (step STP2). This is because by reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and to reduce the size of the component.

  A dicing process is performed in which the back surface of the substrate is ground to separate the substrate into a plurality of chips (step STP3). Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame for bonding (step STP4). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

  In this embodiment, when an element is formed on one surface of the substrate, one surface of the substrate is used as the surface, and the other surface of the substrate (the surface on the side where the elements of the substrate are not formed). ) Is the back side.

  Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a fine metal wire (wire) (step STP5). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

  The wire-bonded chip is sealed with an epoxy resin or the like and subjected to a molding process (step STP6). By performing the molding process, the inside of the electronic component is filled with resin, which can reduce damage to the built-in circuit part and wires due to mechanical external force, and can reduce deterioration of characteristics due to moisture and dust. it can.

  Next, the lead of the lead frame is plated. Then, the lead is cut and molded (step STP7). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

  Next, a printing process (marking) is performed on the surface of the package (step STP8). An electronic component is completed through a final inspection process (step STP9) (step STP10).

  The electronic component described above can include the semiconductor device described in the above embodiment. Therefore, it is possible to realize an electronic component with excellent reliability.

  FIG. 9B shows a schematic perspective view of the completed electronic component. FIG. 9B illustrates a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 4700 illustrated in FIG. 9B illustrates a lead 4701 and a circuit portion 4703. An electronic component 4700 illustrated in FIG. 9B is mounted on a printed board 4702, for example. A plurality of such electronic components 4700 are combined and each is electrically connected on the printed circuit board 4702 so that the electronic component 4700 can be mounted inside the electronic device. The completed circuit board 4704 is provided inside an electronic device or the like.

  Note that one embodiment of the present invention is not limited to the shape of the electronic component 4700 described above, and includes an element substrate manufactured in Step STP1. Further, the element substrate which is one embodiment of the present invention includes an element substrate which has been subjected to the grinding operation of the back surface of the substrate in step STP2. Further, the element substrate which is one embodiment of the present invention includes an element substrate which has been subjected to the dicing process in step STP3. For example, a semiconductor wafer 4800 shown in FIG. 9C corresponds to the element substrate. The semiconductor wafer 4800 has a plurality of circuit portions 4802 formed on the upper surface of the wafer 4801. Note that a portion without the circuit portion 4802 on the upper surface of the wafer 4801 is a spacing 4803, which is a region for dicing.

  Dicing is performed along the scribe line SCL1 and the scribe line SCL2 (sometimes referred to as a dicing line or a cutting line) indicated by a one-dot chain line. In order to facilitate the dicing process, the spacing 4803 is provided so that the plurality of scribe lines SCL1 are parallel, the plurality of scribe lines SCL2 are provided in parallel, and the scribe line SCL1 and the scribe line SCL2 are provided. It is preferable to provide it vertically.

  By performing the dicing process, a chip 4800a as shown in FIG. 9D can be cut out from the semiconductor wafer 4800. The chip 4800a includes a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit portions 4802 may be approximately the same as the margin of the scribe line SCL1 or the margin of the scribe line SCL2.

  Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. For example, a rectangular semiconductor wafer 4810 shown in FIG. The shape of the element substrate can be changed as appropriate in accordance with an element manufacturing process and an apparatus for manufacturing the element.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
In this embodiment, electronic devices including the semiconductor device described in Embodiment 1 are described.

  FIG. 10 illustrates a tablet information terminal 5200 which includes a housing 5221, a display portion 5222, operation buttons 5223, and a speaker 5224. Further, a display device to which a function as a position input device is added may be used for the display portion 5222. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device. Further, the operation button 5223 can include any one of a power switch for starting the information terminal 5200, a button for operating an application of the information terminal 5200, a volume adjustment button, a switch for turning on / off the display unit 5222, and the like. In the information terminal 5200 illustrated in FIG. 10, the number of operation buttons 5223 is four, but the number and arrangement of the operation buttons included in the information terminal 5200 are not limited thereto.

  Although not illustrated, the information terminal 5200 illustrated in FIG. 10 may have a microphone. With this configuration, for example, a call function such as a mobile phone can be added to the information terminal 5200.

  Although not illustrated, the information terminal 5200 illustrated in FIG. 10 may have a configuration including a camera. Although not illustrated, the information terminal 5200 illustrated in FIG. 10 may have a light-emitting device for use in flashlight or lighting.

  Although not illustrated, the information terminal 5200 illustrated in FIG. 10 includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature inside the housing 5221. It may be configured to have a function of measuring chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, infrared rays, and the like. In particular, the orientation of the information terminal 5200 shown in FIG. 10 (which direction the information terminal is oriented with respect to the vertical direction) is determined by providing a detection device having a sensor that detects the inclination, such as a gyroscope or an acceleration sensor. Thus, the screen display of the display unit 5222 can be automatically switched according to the orientation of the information terminal 5200.

  Although not illustrated, the information terminal 5200 illustrated in FIG. 10 may include a device that acquires biological information such as a fingerprint, a vein, an iris, or a voiceprint. By applying this configuration, an information terminal 5200 having a biometric authentication function can be realized.

  Although not illustrated, the information terminal 5200 illustrated in FIG. 10 may have a microphone. By applying this configuration, the information terminal 5200 can be provided with a call function. In some cases, the information terminal 5200 can be provided with a voice decoding function. By providing the information terminal 5200 with a voice decoding function, the information terminal 5200 can have a function of operating the information terminal 5200 by voice recognition, a function of reading a voice and a conversation and creating a conversation record, and the like. . Thereby, it can utilize, for example as minutes preparations, such as a meeting.

  Further, this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 5)
In this embodiment, an input / output device that can be provided in the tablet terminal in FIG. 10 described in Embodiment 4 is described.

  FIG. 11 is a diagram illustrating a configuration of a touch panel 2000TP1 that can be used for an input / output device. FIG. 11A is a top view of the touch panel, FIG. 11B-1 is a schematic diagram for explaining a part of the input portion of the touch panel, and FIG. 11B-2 is a schematic view of FIG. It is a schematic diagram explaining a part of structure shown to (). FIG. 11C is a schematic diagram illustrating part of the display portion included in the touch panel.

  12A is a bottom view illustrating part of the structure of the pixel of the touch panel illustrated in FIG. 11C, and FIG. 12B omits part of the structure illustrated in FIG. It is a bottom view to explain.

  13 and 14 are cross-sectional views illustrating the configuration of the touch panel. 13A is a cross-sectional view taken along the thick lines Z1-Z2, thick lines Z3-Z4, and thick lines Z5-Z6 in FIG. 11A, and FIG. 13B illustrates a part of FIG. It is.

  14A is a cross-sectional view taken along thick lines Z7-Z8, thick lines Z9-Z10, and thick lines Z11-Z12 in FIG. 11A, and FIG. 14B is a diagram for explaining a part of FIG. It is.

  FIG. 15 is a schematic diagram illustrating the shape of a reflective film that can be used for a pixel of a touch panel.

  FIG. 16 is a block diagram illustrating the configuration of the input unit of the touch panel.

  FIG. 17 is a circuit diagram illustrating a configuration of a pixel circuit included in the input / output device.

<Configuration example of input / output device>
The input / output device described in this embodiment includes a touch panel 2000TP1 (see FIG. 11A). The touch panel includes a display unit and an input unit.

<< Configuration Example of Display Unit >>
The display unit includes a display panel, and the display panel includes m pixels in the column direction and n pixels in the row direction, for a total of m × n pixels. In particular, in this embodiment, the pixel located in the i-th row (i is an integer of 1 to m) and j-th column (j is an integer of 1 to n) of the display panel is a pixel. 2100 (i, j).

  The pixel 2100 (i, j) includes a second conductive film, a first conductive film, a second insulating film 2506B, and a first display element 2110 (i, j) (FIG. 14 ( A)).

  The second conductive film is electrically connected to the pixel circuit 2200 (i, j). For example, a conductive film 2522B that functions as a source electrode or a drain electrode of a transistor used for the switch SWT1 in the pixel circuit 2200 (i, j) can be used for the second conductive film (see FIGS. 14A and 17). ).

  The first conductive film includes a region overlapping with the second conductive film. For example, the first conductive film can be used for the first electrode 2111 (i, j) of the first display element 2110 (i, j).

  The second insulating film 2506B includes a region sandwiched between the second conductive film and the first conductive film, and includes an opening 2602A in a region sandwiched between the first conductive film and the second conductive film. . The second insulating film 2506B includes a region sandwiched between the first insulating film 2506A and the conductive film 2524A. In addition, the second insulating film 2506B includes an opening 2602B. The second insulating film 2506B includes an opening 2602C (see FIGS. 13A and 14A).

  The first conductive film is electrically connected to the second conductive film in the opening 2602A. For example, the first electrode 2111 (i, j) is electrically connected to the conductive film 2522B. By the way, the first conductive film electrically connected to the second conductive film in the opening 2602A provided in the second insulating film 2506B can be referred to as a through electrode.

  The first display element 2110 (i, j) is electrically connected to the first conductive film.

  The first display element 2110 (i, j) has a function of controlling the reflection film and the intensity of light reflected by the reflection film. For example, the first conductive film, the first electrode 2111 (i, j), or the like can be used for the reflective film of the first display element 2110 (i, j). Similarly, the first conductive film, the first electrode 2111 (i, j + 1), or the like can be used for the reflective film of the first display element 2110 (i, j + 1), and the first display element 2110 (i, j + 1) can be used. , J + 2) can be formed using the first conductive film, the first electrode 2111 (i, j + 2), or the like (see FIG. 15A). Note that also in FIG. 15B described later, the first electrode 2111 (i, j), the first electrode 2111 (i + 1, j), and the first electrode 2111 (i + 2, j) are illustrated as reflective films. Show.

  The second display element 2120 (i, j) has a function of emitting light toward the second insulating film 2506B (see FIG. 13A).

  The reflective film has a shape in which a region that does not block the light emitted from the second display element 2120 (i, j) is formed.

  Further, the reflective film included in the pixel 2100 (i, j) of the display panel described in this embodiment includes one or a plurality of openings 2111H (see FIG. 15).

  The second display element 2120 (i, j) has a function of emitting light toward the opening 2111H. Note that the opening 2111H transmits light emitted from the second display element 2120 (i, j).

  For example, the opening 2111H of the pixel 2100 (i, j + 1) adjacent to the pixel 2100 (i, j) is in the row direction passing through the opening 2111H of the pixel 2100 (i, j) (the direction indicated by the arrow Ro1 in the drawing). (See FIG. 15A). Alternatively, for example, the opening 2111H of the pixel 2100 (i + 1, j) adjacent to the pixel 2100 (i, j) passes through the opening 2111H of the pixel 2100 (i, j) in the column direction (in the figure, with an arrow Co1). They are not arranged on a straight line extending in the direction shown (see FIG. 15B).

  For example, the opening 2111H of the pixel 2100 (i, j + 2) is disposed on a straight line extending in the row direction passing through the opening 2111H of the pixel 2100 (i, j) (see FIG. 15A). In addition, the opening 2111H of the pixel 2100 (i, j + 1) is arranged on a straight line orthogonal to the straight line between the opening 2111H of the pixel 2100 (i, j) and the opening 2111H of the pixel 2100 (i, j + 2). Established.

  Alternatively, for example, the opening 2111H of the pixel 2100 (i + 2, j) is disposed on a straight line extending in the column direction passing through the opening 2111H of the pixel 2100 (i, j) (see FIG. 15B). . For example, the opening 2111H of the pixel 2100 (i + 1, j) is on a straight line orthogonal to the straight line between the opening 2111H of the pixel 2100 (i, j) and the opening 2111H of the pixel 2100 (i + 2, j). It is arranged.

  Accordingly, the third display element that displays a color different from that of the second display element can be easily disposed at a position close to the second display element. As a result, a display panel that is highly convenient or reliable can be provided.

  Note that, for example, a material having a shape in which an end portion is cut out so that a region 2111E that does not block light emitted from the second display element 2120 (i, j) is formed is used for the reflective film. (See FIG. 15C). Specifically, the first electrode 2111 (i, j) whose end is cut so that the column direction (the direction indicated by the arrow Co1 in the drawing) is shortened can be used for the reflective film. Note that in FIG. 15C, the first electrode 2111 (i, j + 1) is illustrated as well as the first electrode 2111 (i, j).

  Thereby, for example, using a pixel circuit that can be formed using the same process, the first display element and the second display element that displays using a method different from the first display element, Can be driven. Specifically, power consumption can be reduced by using a reflective display element as the first display element. Alternatively, an image can be favorably displayed with high contrast in an environment with bright external light. Alternatively, an image can be favorably displayed in a dark environment by using the second display element that emits light. Further, diffusion of impurities between the first display element and the second display element or between the first display element and the pixel circuit can be suppressed by using the second insulating film. In addition, part of the light emitted from the second display element supplied with the voltage controlled based on the control information is not blocked by the reflective film included in the first display element. As a result, a display device that is highly convenient or reliable can be provided.

  In addition, the second display element 2120 (i, j) included in the pixel of the input / output device described in this embodiment is in a range in which display using the first display element 2110 (i, j) is visible. It arrange | positions so that it can visually recognize in a part. For example, the direction in which external light is incident on and reflected by the first display element 2110 (i, j) that displays by controlling the intensity of reflecting external light is indicated by a dashed arrow in the drawing (FIG. 14A). reference). The direction in which the second display element 2120 (i, j) emits light in a part of the range where the display using the first display element 2110 (i, j) can be visually recognized is indicated by a solid arrow in the drawing. (See FIG. 13A).

  Thereby, the display using the 2nd display element can be visually recognized in a part of field which can visually recognize the display using the 1st display element. Alternatively, the user can visually recognize the display without changing the posture of the display panel. As a result, a display panel that is highly convenient or reliable can be provided.

  The pixel circuit 2200 (i, j) is electrically connected to the signal line Sig1 (j). Note that the conductive film 2522A is electrically connected to the signal line Sig1 (j) (see FIGS. 14A and 17). For example, a transistor using the second conductive film as the conductive film 2522B functioning as a source electrode or a drain electrode can be used for the switch SWT1 of the pixel circuit 2200 (i, j).

  In addition, the display panel described in this embodiment includes the first insulating film 2506A (see FIG. 13A).

  The first insulating film 2506A includes a first opening 2603A, a second opening 2603B, and an opening 2603C (see FIG. 13A or FIG. 14A).

  The first opening 2603A includes a region overlapping with the first intermediate film 2540A and the first electrode 2111 (i, j) or a region overlapping with the first intermediate film 2540A and the second insulating film 2506B.

  The second opening 2603B includes a region overlapping with the second intermediate film 2540B and the conductive film 2524A. The opening 2603C includes a region overlapping with the intermediate film 2540C and the conductive film 2524B.

  The first insulating film 2506A includes a region sandwiched between the first intermediate film 2540A and the second insulating film 2506B along the peripheral edge of the first opening 2603A. The first insulating film 2506A includes: A region sandwiched between the second intermediate film 2540B and the conductive film 2524A is provided along the periphery of the second opening 2603B.

  In addition, the display panel described in this embodiment includes a scan line G2 (i), a wiring CSCOM, a third conductive film ANO, and a signal line Sig2 (j) (see FIG. 17).

  In addition, the second display element 2120 (i, j) of the display panel described in this embodiment includes a third electrode 2121 (i, j), a fourth electrode 2122, and a light-emitting material. A layer 2123 (j) (see FIG. 13A). Note that the third electrode 2121 (i, j) is electrically connected to the third conductive film ANO, and the fourth electrode 2122 is electrically connected to the fourth conductive film VCOM2 (FIG. 17). reference).

  The fourth electrode 2122 includes a region overlapping with the third electrode 2121 (i, j).

  The layer 2123 (j) containing a light-emitting material includes a region sandwiched between the third electrode 2121 (i, j) and the fourth electrode 2122.

  The third electrode 2121 (i, j) is electrically connected to the pixel circuit 2200 (i, j) at the connection portion 2601.

  In addition, the first display element 2110 (i, j) of the display panel described in this embodiment includes a layer 2113 containing a liquid crystal material, a first electrode 2111 (i, j), and a second electrode 2112. . The second electrode 2112 is disposed so that an electric field for controlling the alignment of the liquid crystal material is formed between the second electrode 2112 and the first electrode 2111 (i, j) (FIGS. 13A and 14A). reference).

  In addition, the display panel described in this embodiment includes an alignment film AF1 and an alignment film AF2. The alignment film AF2 is disposed so as to sandwich the layer 2113 containing a liquid crystal material between the alignment film AF1.

  In addition, the display panel described in this embodiment includes a first intermediate film 2540A and a second intermediate film 2540B.

  The first intermediate film 2540A includes a region in which the first conductive film is sandwiched between the second insulating film 2506B, and the first intermediate film 2540A is a region in contact with the first electrode 2111 (i, j). Is provided. The second intermediate film 2540B includes a region in contact with the conductive film 2524A.

  In addition, the display panel described in this embodiment includes a light-blocking film BM, an insulating film 2507, a functional film 2802P, and a functional film 2802D. In addition, the color film CF1 and the color film CF2 are provided.

  The light shielding film BM includes an opening in a region overlapping with the first display element 2110 (i, j). The coloring film CF2 is provided between the second insulating film 2506B and the second display element 2120 (i, j) and includes a region overlapping with the opening 2111H (see FIG. 13A).

  The insulating film 2507 includes a region sandwiched between the coloring film CF1 and the layer 2113 containing a liquid crystal material or between the light shielding film BM and the layer 2113 containing a liquid crystal material. Thereby, the unevenness | corrugation based on the thickness of colored film CF1 can be made flat. Alternatively, impurity diffusion from the light-blocking film BM, the coloring film CF1, or the like to the layer 2113 containing a liquid crystal material can be suppressed.

  The functional film 2802P includes a region overlapping with the first display element 2110 (i, j).

  The functional film 2802D includes a region overlapping with the first display element 2110 (i, j). The functional film 2802D is disposed so that the substrate 2802 is sandwiched between the functional film 2802D and the first display element 2110 (i, j). Thereby, for example, light reflected by the first display element 2110 (i, j) can be diffused.

  In addition, the display panel described in this embodiment includes a substrate 2801, a substrate 2802, and a functional layer 2581.

  The substrate 2802 includes a region overlapping with the substrate 2801.

  The functional layer 2581 includes a region sandwiched between the substrate 2801 and the substrate 2802. The functional layer 2581 includes a pixel circuit 2200 (i, j), a second display element 2120 (i, j), an insulating film 2502, and an insulating film 2501. The functional layer 2581 includes an insulating film 2503 and an insulating film 2504 (see FIGS. 13A and 13B).

  The insulating film 2502 includes a region sandwiched between the pixel circuit 2200 (i, j) and the second display element 2120 (i, j).

  The insulating film 2501 is provided between the insulating film 2502 and the substrate 2801 and includes an opening in a region overlapping with the second display element 2120 (i, j).

  An insulating film 2501 formed along the periphery of the third electrode 2121 (i, j) prevents a short circuit between the third electrode 2121 (i, j) and the fourth electrode.

  The insulating film 2503 includes a region sandwiched between the insulating film 2502 and the pixel circuit 2200 (i, j). The insulating film 2504 includes a region sandwiched between the insulating film 2503 and the pixel circuit 2200 (i, j).

  In addition, the display panel described in this embodiment includes a bonding layer 2811, a sealing material 2820, and a structure body KB1.

  The bonding layer 2811 includes a region sandwiched between the functional layer 2581 and the substrate 2801 and has a function of bonding the functional layer 2581 and the substrate 2801 together.

  The sealing material 2820 includes a region sandwiched between the functional layer 2581 and the substrate 2802 and has a function of bonding the functional layer 2581 and the substrate 2802 together.

  The structure KB1 has a function of providing a predetermined gap between the functional layer 2581 and the substrate 2802.

  In addition, the display panel described in this embodiment includes a terminal 2900A and a terminal 2900B.

  The terminal 2900A includes a conductive film 2524A and an intermediate film 2540B, and the intermediate film 2540B includes a region in contact with the conductive film 2524A. The terminal 2900A is electrically connected to the signal line Sig1 (j), for example.

  Terminal 2900A can be electrically connected to flexible printed circuit board FPC1 using conductive material ACF1.

  The terminal 2900B includes a conductive film 2524B and an intermediate film 2540C. The intermediate film 2540C includes a region in contact with the conductive film 2524B. The conductive film 2524B is electrically connected to, for example, the wiring VCOM1.

  The conductive material CP is sandwiched between the terminal 2900B and the second electrode 2112 and has a function of electrically connecting the terminal 2900B and the second electrode 2112. For example, conductive particles can be used for the conductive material CP.

  In addition, the display panel described in this embodiment includes a driver circuit GD and a driver circuit SD (see FIG. 11).

  The drive circuit GD is electrically connected to the scanning line G1 (i). The driver circuit GD includes, for example, a transistor MD (see FIG. 13A). Specifically, a transistor including a semiconductor film that can be formed in the same process as the transistor included in the pixel circuit 2200 (i, j) can be used for the transistor MD.

  The drive circuit SD is electrically connected to the signal line Sig1 (j). The drive circuit SD is electrically connected to the terminal 2900A, for example.

<< Configuration example of input unit >>
The input portion includes a region overlapping with the display panel (see FIG. 11, FIG. 13A, or FIG. 14A).

  The input portion includes a substrate 2803, a functional layer 2582, a bonding layer 2812, and a terminal 2901 (see FIGS. 13A and 14A).

  The input unit includes a control line CL (g), a detection signal line ML (h), and a detection element 2150 (g, h) (see FIG. 11B-2).

  The functional layer 2582 includes a region sandwiched between the substrate 2802 and the substrate 2803. The functional layer 2582 includes a sensing element 2150 (g, h) and an insulating film 2508.

  The bonding layer 2812 is provided between the functional layer 2582 and the substrate 2802 and has a function of bonding the functional layer 2582 and the substrate 2802 together.

  The detection element 2150 (g, h) is electrically connected to the control line CL (g) and the detection signal line ML (h).

  The control line CL (g) has a function of supplying a control signal.

  The detection element 2150 (g, h) is supplied with a control signal, and the detection element 2150 (g, h) supplies a detection signal that changes based on the control signal and a distance from an area close to the area overlapping the display panel. Is provided.

  The detection signal line ML (h) has a function of being supplied with a detection signal.

  The sensing element 2150 (g, h) has translucency.

  The sensing element 2150 (g, h) includes an electrode C (g) and an electrode M (h).

  The electrode C (g) is electrically connected to the control line CL (g).

  The electrode M (h) is electrically connected to the detection signal line ML (h), and the electrode M (h) has an electric field partially blocked by an electrode adjacent to the region overlapping the display panel. ) To form between.

  Accordingly, it is possible to detect an object that is close to a region overlapping the display panel while displaying image information using the display panel.

  The input portion described in this embodiment includes a substrate 2803 and a bonding layer 2812 (see FIG. 13A or FIG. 14A).

  The substrate 2803 is disposed so that the sensing element 2150 (g, h) is sandwiched between the substrate 2802 and the substrate 2802.

  The bonding layer 2812 is provided between the substrate 2802 and the detection element 2150 (g, h), and has a function of bonding the substrate 2802 and the detection element 2150 (g, h).

  The functional film 2802P is disposed so that the detection element 2150 (g, h) is sandwiched between the functional film 2802P and the first display element 2110 (i, j). Thereby, for example, the intensity of light reflected by the sensing element 2150 (g, h) can be reduced.

  The input portion described in this embodiment includes a group of detection elements 2150 (g, 1) to 2150 (g, q) and another group of detection elements 2150 (1, h) to 2150. (P, h) (see FIG. 16). Here, g is an integer of 1 or more and p or less, h is an integer of 1 or more and q or less, and p and q are integers of 1 or more.

  A group of the sensing elements 2150 (g, 1) to 2150 (g, q) includes the sensing elements 2150 (g, h) and are arranged in the row direction (direction indicated by an arrow Ro2 in the drawing).

  The other group of the sensing elements 2150 (1, h) to 2150 (p, h) includes the sensing elements 2150 (g, h), and the column direction (in the figure, indicated by an arrow Co2) intersecting the row direction. (Direction shown).

  The group of sensing elements 2150 (g, 1) to 2150 (g, q) arranged in the row direction includes an electrode C (g) electrically connected to the control line CL (g).

  Another group of sensing elements 2150 (1, h) to 2150 (p, h) arranged in the column direction has electrodes M (h) electrically connected to the sensing signal lines ML (h). Including.

  Further, the control line CL (g) of the touch panel described in this embodiment includes a conductive film BR (g, h) (see FIG. 13A). The conductive film BR (g, h) includes a region overlapping with the detection signal line ML (h).

  The insulating film 2508 includes a region sandwiched between the detection signal line ML (h) and the conductive film BR (g, h). Thereby, a short circuit of the detection signal line ML (h) and the conductive film BR (g, h) can be prevented.

  The touch panel described in this embodiment includes an oscillation circuit OSC and a detection circuit DC (see FIG. 16).

  The oscillation circuit OSC is electrically connected to the control line CL (g) and has a function of supplying a control signal. For example, a rectangular wave, a sawtooth wave, a triangular wave, or the like can be used as the control signal.

  The detection circuit DC is electrically connected to the detection signal line ML (h) and has a function of supplying a detection signal based on a change in potential of the detection signal line ML (h).

  Below, each element which comprises a touch panel is demonstrated. Note that these configurations cannot be clearly separated, and one configuration may serve as another configuration or may include a part of another configuration.

  For example, the first conductive film can be used for the first electrode 2111 (i, j). In addition, the first conductive film can be used as a reflective film.

  The second conductive film can be used for the conductive film 2522B having the function of the source electrode or the drain electrode of the transistor.

  The terminal 2901 can be electrically connected to the flexible printed circuit board FPC2 using the conductive material ACF2. The terminal 2901 is electrically connected to the detection element 2150 (g, h).

<< Configuration Example of Pixel Circuit >>
A structural example of the pixel circuit will be described with reference to FIG. The pixel circuit 2200 (i, j) is electrically connected to the signal line Sig1 (j), the signal line Sig2 (j), the scanning line G1 (i), the scanning line G2 (i), the wiring CSCOM, and the third conductive film ANO. Connected to. Similarly, the pixel circuit 2200 (i, j + 1) includes the signal line Sig1 (j + 1), the signal line Sig2 (j + 1), the scanning line G1 (i), the scanning line G2 (i), the wiring CSCOM, and the third conductive film ANO. And electrically connected.

  The pixel circuit 2200 (i, j) and the pixel circuit 2200 (i, j + 1) each include a switch SWT1 and a capacitor C11.

  The pixel circuit 2200 (i, j) and the pixel circuit 2200 (i, j + 1) each include a switch SWT2, a transistor M, and a capacitor C12.

  For example, a transistor including a gate electrode electrically connected to the scan line G1 (i) and a first electrode electrically connected to the signal line Sig1 (j) can be used for the switch SWT1. .

  The capacitor C11 includes a first electrode electrically connected to the second electrode of the transistor used for the switch SWT1, and a second electrode electrically connected to the wiring CSCOM.

  For example, a transistor including a gate electrode electrically connected to the scan line G2 (i) and a first electrode electrically connected to the signal line Sig2 (j) can be used for the switch SWT2. .

  The transistor M includes a gate electrode that is electrically connected to the second electrode of the transistor used for the switch SWT2, and a first electrode that is electrically connected to the third conductive film ANO.

  Note that a transistor including a conductive film provided so that a semiconductor film is interposed between a gate electrode and the gate electrode can be used for the transistor M. For example, a conductive film that is electrically connected to a wiring that can supply the same potential as the gate electrode of the transistor M can be used for the conductive film.

  The capacitor C12 includes a first electrode that is electrically connected to the second electrode of the transistor used for the switch SWT2, and a second electrode that is electrically connected to the first electrode of the transistor M. .

  Note that in the pixel circuit 2200 (i, j), the first electrode of the first display element 2110 (i, j) is electrically connected to the second electrode of the transistor used for the switch SWT1, so that the first display The second electrode of the element 2110 (i, j) is electrically connected to the wiring VCOM1. Accordingly, the first display element 2110 can be driven. Similarly, in the pixel circuit 2200 (i, j + 1), the first electrode of the first display element 2110 (i, j + 1) is electrically connected to the second electrode of the transistor used for the switch SWT1, and the first electrode The second electrode of the display element 2110 (i, j + 1) is electrically connected to the wiring VCOM1. Accordingly, the first display element 2110 can be driven.

  In the pixel circuit 2200 (i, j), the first electrode of the second display element 2120 (i, j) is electrically connected to the second electrode of the transistor M, and the second display element 2120 ( The second electrode i, j) is electrically connected to the fourth conductive film VCOM2. Accordingly, the second display element 2120 (i, j) can be driven. Similarly, in the pixel circuit 2200 (i, j + 1), the first electrode of the second display element 2120 (i, j + 1) is electrically connected to the second electrode of the transistor M, and the second display element 2120 is connected. The second electrode (i, j + 1) is electrically connected to the fourth conductive film VCOM2. Accordingly, the second display element 2120 (i, j + 1) can be driven.

<< Example of transistor structure >>
As the switch SWT1, the transistor M, and the transistor MD, bottom-gate or top-gate transistors can be used.

  For example, a transistor in which a semiconductor containing a Group 14 element is used for a semiconductor film can be used. Specifically, a semiconductor containing silicon can be used for the semiconductor film. For example, a transistor using single crystal silicon, polysilicon, microcrystalline silicon, amorphous silicon, or the like for a semiconductor film can be used.

  For example, a transistor in which an oxide semiconductor is used for a semiconductor film can be used. Specifically, an oxide semiconductor containing indium or an oxide semiconductor containing indium, zinc, and an element M (the element M is aluminum, gallium, yttrium, or tin) can be used for the semiconductor film.

  For example, a transistor whose leakage current in an off state is smaller than that of a transistor using amorphous silicon as a semiconductor film can be used for the switch SWT1, the transistor M, the transistor MD, or the like. Specifically, a transistor in which an oxide semiconductor is used for the semiconductor film 2560 can be used for the switch SWT1, the transistor M, the transistor MD, or the like.

  Accordingly, as compared with a pixel circuit using a transistor using amorphous silicon as a semiconductor film, the time during which the pixel circuit can hold an image signal can be lengthened. Specifically, the selection signal can be supplied at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute while suppressing the occurrence of flicker. As a result, fatigue accumulated in the user of the information processing apparatus can be reduced. In addition, power consumption associated with driving can be reduced.

  A transistor that can be used for the switch SWT1 includes a semiconductor film 2560 and a conductive film 2523 including a region overlapping with the semiconductor film 2560 (see FIG. 14B). A transistor that can be used for the switch SWT1 includes a conductive film 2522A and a conductive film 2522B that are electrically connected to the semiconductor film 2560.

  Note that the conductive film 2523 has a function of a gate electrode, and the insulating film 2505 has a function of a gate insulating film. In addition, the conductive film 2522A has one of a source electrode function and a drain electrode function, and the conductive film 2522B has the other function of the source electrode and the drain electrode.

  A transistor including the conductive film 2521 provided so that the semiconductor film 2560 is interposed between the conductive film 2523 and the conductive film 2523 can be used for the transistor M (see FIG. 13B).

  By applying the input / output device described above to the tablet-type information terminal 5200 illustrated in FIG. 10 described in Embodiment 4, an electronic device with excellent visibility, convenience, or reliability can be realized. it can.

<Application examples of display modules>
Next, application examples of the display module using the display panel in FIG. 11A will be described with reference to FIGS.

  A display module 4000 illustrated in FIG. 18 includes a touch panel 4004 connected to the FPC 4003, a display panel 4006 connected to the FPC 4005, a frame 4009, a printed board 4010, and a battery 4011 between an upper cover 4001 and a lower cover 4002. Note that the battery 4011, the touch panel 4004, and the like may not be provided.

  The display panel described in FIG. 11A can be used for the display panel 4006 in FIG.

  The shapes and / or dimensions of the upper cover 4001 and the lower cover 4002 can be changed as appropriate in accordance with the sizes of the touch panel 4004 and the display panel 4006.

  As the touch panel 4004, a resistive touch panel or a capacitive touch panel can be used by being overlapped with the display panel 4006 like the touch panel 2000TP1 illustrated in FIG. The counter substrate (sealing substrate) of the display panel 4006 can have a touch panel function. Alternatively, an optical sensor can be provided in each pixel of the display panel 4006 to provide an optical touch panel. A touch sensor electrode may be provided in each pixel of the display panel 4006 to form a capacitive touch panel. In this case, the touch panel 4004 can be omitted.

  The frame 4009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 4010 in addition to a protective function of the display panel 4006. The frame 4009 may have a function as a heat sink.

  The printed board 4010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 4011 provided separately may be used. The battery 4011 can be omitted when a commercial power source is used.

  The display module 4000 may be additionally provided with a member such as a polarizing plate, a retardation plate, and a prism sheet.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Additional notes regarding the description of this specification etc.)
The description of each component in the above embodiment will be added below.

<Supplementary Note on One Aspect of the Invention described in Embodiment>
The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined with each other as appropriate.

  Note that the content described in one embodiment (may be a part of content) is different from the other content described in the embodiment (may be a part of content) and one or more other implementations. Application, combination, replacement, or the like can be performed on at least one of the contents described in the form (may be part of the contents).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, another drawing (may be a part) described in the embodiment, or one or more different drawings. By combining at least one of the drawings (or a part thereof) described in the embodiment, more drawings can be formed.

<Notes on ordinal numbers>
In this specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, the constituent elements referred to as “first” in one embodiment of the present specification and the like may be omitted in other embodiments or in the claims.

<Additional notes regarding the description explaining the drawings>
Embodiments are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms, and that the forms and details can be variously changed without departing from the spirit and scope thereof. The Therefore, the present invention should not be construed as being limited to the description of the embodiments. Note that in the structures of the embodiments of the present invention, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

  In addition, in this specification and the like, terms indicating arrangement such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between the components appropriately changes depending on the direction in which each component is drawn. Therefore, the phrase indicating the arrangement is not limited to the description described in the specification, and can be appropriately rephrased depending on the situation.

  Further, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below, and is in direct contact with each other. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

  Further, in the present specification and the like, in the block diagram, the constituent elements are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In the drawings, some components may be omitted from the perspective views and the like for the sake of clarity.

  In the drawings, the same element, an element having a similar function, an element of the same material, or an element formed at the same time may be denoted by the same reference numeral, and repeated description thereof may be omitted. .

<Additional notes on paraphrased descriptions>
In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode. In this specification and the like, two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal. In addition, when a transistor described in this specification and the like has two or more gates (this structure is sometimes referred to as a dual gate structure), these gates may be referred to as a first gate and a second gate, , Sometimes called back gate. In particular, the phrase “front gate” can be rephrased as simply the phrase “gate”. Also, the phrase “back gate” can be rephrased simply as the phrase “gate”. Note that a bottom gate refers to a terminal formed before a channel formation region when a transistor is manufactured, and a “top gate” is formed after a channel formation region when a transistor is manufactured. Terminal.

  The transistor has three terminals called a gate, a source, and a drain. The gate is a terminal that functions as a control terminal for controlling the conduction state of the transistor. One of the two input / output terminals functioning as a source or drain serves as a source and the other serves as a drain depending on the type of the transistor and the potential applied to each terminal. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground potential (ground potential), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer”. Alternatively, in some cases or depending on circumstances, it is possible to replace with another term without using a phrase such as “film” or “layer”. For example, the term “conductive layer” or “conductive film” may be changed to the term “conductor” in some cases. Alternatively, for example, the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.

  Note that in this specification and the like, terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other depending on the case or circumstances. For example, it may be possible to change the term “wiring” to the term “signal line”. In addition, for example, the term “wiring” may be changed to a term such as “power supply line”. The reverse is also true, and there are cases where terms such as “signal line” and “power supply line” can be changed to the term “wiring”. A term such as “power line” may be changed to a term such as “signal line”. The reverse is also true, and a term such as “signal line” may be changed to a term such as “power line”. In addition, the term “potential” applied to the wiring may be changed to a term “signal” or the like depending on circumstances or circumstances. The reverse is also true, and a term such as “signal” may be changed to a term “potential”.

<Notes on the definition of words>
Below, the definition of the phrase referred in the said embodiment is demonstrated.

<< About Semiconductor >>
In this specification, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

  In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

  Note that the semiconductor impurities refer to components other than the main components constituting the semiconductor layer, for example. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When the impurities are included, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. In the case where the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

<< About Transistors >>
In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode). When a voltage is applied between the gate and the source, a channel is formed in the channel formation region, and a current flows between the source and the drain.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

<< About the switch >>
In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  An example of a mechanical switch is a switch using MEMS (micro electro mechanical systems) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

<< About connection >>
In this specification and the like, when X and Y are described as being connected, when X and Y are electrically connected, and when X and Y are functionally connected And the case where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the figure or text, and includes things other than the connection relation shown in the figure or text.

  X, Y, and the like used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do.

  Note that when X and Y are explicitly described as being electrically connected, when X and Y are electrically connected (that is, another element between X and Y). Or when X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And a case where X and Y are directly connected (that is, a case where another element or another circuit is not connected between X and Y). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

  Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

  For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source of the transistor ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

  In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

<< About parallel and vertical >>
In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

<< About trigonal and rhombohedral crystals >>
In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

LP display panel OP display panel IT terminal OT terminal LT terminal OP1 operational amplifier OP2 operational amplifier OSW switch LSW switch OSWG switch LSWG switch SWa [1] switch SWa [j] switch SWa [n] switch SE [1] switch SE [j] switch SE [N] Switch SWb [1] Switch SWb [j] Switch SWb [n] Switch SWb [n + 1] Switch C [1] Capacitor C [2] Capacitor C [3] Capacitor C [4] Capacitor C [ 5] Capacitor C [6] Capacitor C [j] Capacitor C [n] Capacitor OTr Transistor OTrG Transistor LTr Transistor LTrG Transistor Tra [1] Transistor Tra [2] Transistor Tra [3] Transistor Tra [4] Transistor Tra [5] Transistor Tra [6] Transistor a [1] Wiring a [2] Wiring a [3] Wiring a [4] Wiring a [5] Wiring a [6] Wiring SC [1] Selector SC [2] Selector SC [3] Selector SC [4] Selector SC [5] Selector SC [6] Selector SC [J] Selector SCT1 Terminal SCT2 Terminal SCT3 Terminal Trb [1] Transistor Trb [2] Transistor Trb [3] Transistor Trb [4] Transistor Trb [5] Transistor Trb [6] Transistor Trb [7] Transistor b [1] Wiring b [2] Wiring b [3] Wiring b [4] Wiring b [5] Wiring b [6] Wiring b [7] Wiring c [J] Wiring SWc1 Analog switch SWc2 Analog switch INV Inverter circuit OSL Wiring OGL Wiring LSL Line LGL wiring VOL wiring VLL wiring GNDL wiring ST1 step ST2 step ST3 step ST4 step ST5 step ST6 step ST7 step ST8 step ST9 step ST10 step STP1 step STP2 step STP3 step STP4 step STP5 step STP6 step STP7 step STP8 step STP9 step STP10 step Co1 Arrow Co2 Arrow Ro1 Arrow Ro2 Arrow SWT1 Switch SWT2 Switch M Transistor MD Transistor C11 Capacitor C12 Capacitor Sig1 (j) Signal line Sig2 (j) Signal line Sig1 (j + 1) Signal line Sig2 (j + 1) Signal line G1 (i) Scan Line G2 (i) Scan line CL (g) Control line ML (h) Detection signal line C g) Electrode M (h) Electrode BR (g, h) Conductive film CSCOM Wiring VCOM1 Wiring VCOM2 Fourth conductive film ANO Third conductive film FPC1 Flexible printed circuit board FPC2 Flexible printed circuit board ACF1 Conductive material ACF2 Conductive material AF1 Alignment film AF2 Alignment film BM Light shielding film CF1 Colored film CF2 Colored film KB1 Structure CP Conductive material GD Drive circuit SD Drive circuit OSC Oscillation circuit DC detection circuit 100 Semiconductor device 101 Illuminance meter 102 Threshold detection circuit 103 Timing controller 104 Circuit 110 Display unit 200 Digital / analog conversion circuit 200A Digital / analog conversion circuit 200B Digital / analog conversion circuit 201 circuit 202 circuit 203 circuit 300 source driver circuit 310 LVDS receiver 320 serial / parallel conversion circuit 33 Shift register circuit 340 Latch circuit 350 Level shifter 360 Circuit 370 Capacitance array circuit 380 External correction circuit 390 BGR circuit 400 Bias generator 500 Buffer amplifier 2000TP1 Touch panel 2100 (i, j) Pixel 2100 (i, j + 1) Pixel 2100 (i + 1, j) Pixel 2100 (i + 2, j) Pixel 2110 (i, j) First display element 2110 (i, j + 1) First display element 2111 (i, j) First electrode 2111 (i, j + 1) First electrode 2111 (I, j + 2) first electrode 2111 (i + 1, j) first electrode 2111 (i + 2, j) first electrode 2111E region 2111H opening 2112 second electrode 2113 layer 2120 (i, j) second Display element 2120 (i, j + 1) Second display element 2121 ( i, j) Third electrode 2122 Fourth electrode 2123 (j) Layer 2150 (g, h) Sensing element 2150 (g, 1) Sensing element 2150 (g, q) Sensing element 2150 (1, h) Sensing element 2150 (p, h) detection element 2200 (i, j) pixel circuit 2200 (i, j + 1) pixel circuit 2501 insulating film 2502 insulating film 2503 insulating film 2504 insulating film 2505 insulating film 2506A first insulating film 2506B second insulating Film 2507 insulating film 2508 insulating film 2521 conductive film 2522A conductive film 2522B conductive film 2523 conductive film 2524A conductive film 2524B conductive film 2540A first intermediate film 2540B second intermediate film 2540C intermediate film 2560 semiconductor film 2581 functional layer 2582 functional layer 2601 Connection 2602A Opening 2602B Opening 2602C Opening 26 3A First opening 2603B Second opening 2603C Opening 2801 Substrate 2802 Substrate 2802P Functional film 2802D Functional film 2803 Substrate 2811 Bonding layer 2812 Bonding layer 2820 Sealing material 2900A Terminal 2900B Terminal 2901 Terminal 4000 Display module 4001 Upper cover 4002 Lower cover 4003 FPC
4004 Touch panel 4005 FPC
4006 Display panel 4009 Frame 4010 Printed circuit board 4011 Battery 4700 Electronic component 4701 Lead 4702 Printed circuit board 4703 Circuit part 4704 Circuit board 4800 Semiconductor wafer 4800a Chip 4801 Wafer 4801a Wafer 4802 Circuit part 4803 Spacing 4803a Spacing 4810 Semiconductor wafer 5200 Information terminal 5221 Housing Body 5222 Display unit 5223 Operation button 5224 Speaker

Claims (9)

A first operational amplifier, a second operational amplifier, and first to third circuits;
The first circuit includes first to nth switches (n is an integer of 2 or more) and first to (n + 1) th capacitive elements,
The second circuit includes first to nth selectors,
Each of the first to n-th selectors has a first input terminal, a second input terminal, and an output terminal,
The third circuit includes (n + 1) th to (2n + 1) th switches,
One terminal of the first switch is electrically connected to one of the pair of electrodes of the first capacitive element,
One terminal (j is an integer of 2 or more and n or less) of the j-th switch is electrically connected to one of the pair of electrodes of the j-th capacitance element,
One terminal of the j-th switch is electrically connected to the other terminal of the (j-1) switch,
The other terminal of the nth switch is electrically connected to one of a pair of electrodes of the (n + 1) th capacitive element,
A non-inverting input terminal of the first operational amplifier is electrically connected to the other terminal of the nth switch;
The inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier,
A non-inverting input terminal of the second operational amplifier is electrically connected to one terminal of the first switch;
The inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier,
The output terminal of the kth selector (k is an integer of 1 to n) is electrically connected to the other of the pair of electrodes of the (k + 1) th capacitive element,
One terminal of the h-th switch (h is an integer from (n + 2) to (2n + 1)) is electrically connected to the other terminal of the (h-1) switch,
The other terminal of the (n + k) switch is electrically connected to the second input terminal of the kth selector. In claim 1,
Each of the first to (2n + 1) switches includes a first transistor,
The channel formation region of the first transistor includes an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. In claim 1 or claim 2,
A (2n + 2) switch and a (2n + 3) switch,
One terminal of the (2n + 2) switch is electrically connected to the non-inverting input terminal of the first operational amplifier,
One terminal of the (2n + 3) switch is electrically connected to the non-inverting input terminal of the second operational amplifier. In claim 3,
Each of the (2n + 2) switch and the (2n + 3) switch includes a second transistor,
The channel formation region of the second transistor includes an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. In any one of Claims 1 thru | or 4,
A (2n + 4) switch and a (2n + 5) switch,
One terminal of the (2n + 4) switch is electrically connected to the output terminal of the first operational amplifier,
One terminal of the (2n + 5) switch is electrically connected to the output terminal of the second operational amplifier. In claim 5,
Each of the (2n + 4) switch and the (2n + 5) switch includes a third transistor,
The channel formation region of the third transistor includes an oxide containing at least one of indium, element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. A first operational amplifier, a second operational amplifier, first to third switches, a first capacitive element, a second capacitive element, and a selector;
The selector has a first input terminal, a second input terminal, and an output terminal;
One terminal of the first switch is electrically connected to one of the pair of electrodes of the first capacitive element,
The other terminal of the first switch is electrically connected to one of the pair of electrodes of the second capacitive element;
A non-inverting input terminal of the first operational amplifier is electrically connected to the other terminal of the first switch;
The inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier,
A non-inverting input terminal of the second operational amplifier is electrically connected to one terminal of the first switch;
The inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier,
The output terminal of the selector is electrically connected to the other of the pair of electrodes of the second capacitive element;
One terminal of the second switch is electrically connected to the other terminal of the three switches,
The other terminal of the third switch is electrically connected to the second input terminal of the selector. A system comprising the semiconductor device according to any one of claims 1 to 7, an illuminance meter, a fourth circuit, a fifth circuit, a first display panel, and a second display panel.
The illuminance meter is electrically connected to the fourth circuit,
The fourth circuit is electrically connected to the fifth circuit;
The fifth circuit is electrically connected to the semiconductor device;
The first display panel is electrically connected to the semiconductor device;
The system, wherein the second display panel is electrically connected to the semiconductor device. A method of operating the system according to claim 8,
Having first to tenth steps;
The first step includes the step of measuring the illuminance by the illuminometer.
The second step includes a step of transmitting the illuminance from the illuminance meter to the fourth circuit,
The third step includes a step of generating, by the fourth circuit, first data for determining a gray level of the first display panel and a gray level of the second display panel based on the illuminance.
The fourth step includes a step of transmitting the first data from the fourth circuit to the fifth circuit, and a step of transmitting second data from the outside to the fifth circuit,
The fifth step includes a step of initializing the semiconductor device,
The sixth step includes a step of generating third data to be transmitted to the first display panel according to the first data and the second data in the fifth circuit; and Transmitting the third data from a circuit to the semiconductor device; and in the semiconductor device, converting the third data into digital data by converting the third data into fourth data,
The seventh step includes a step of transmitting the fourth data from the semiconductor device to the first display panel and displaying an image on the first display panel;
The eighth step includes a step of initializing the semiconductor device,
The ninth step includes generating fifth data to be transmitted to the second display panel according to the first data and the second data in the fifth circuit; and Transmitting the third data from a circuit to the semiconductor device; and in the semiconductor device, converting the fifth data from digital to analog into sixth data,
The tenth step includes a step of transmitting the sixth data from the previous semiconductor device to the second display panel and displaying an image on the second display panel;
The operation method according to claim 1, wherein the second data is video data.