JPH0855224A - Image processor - Google Patents

Abstract

PURPOSE:To improve the efficiency of even a full-color printer etc., with high resolution by making the access time of an image memory not long. CONSTITUTION:A PDL process part 2 decodes inputted PDL(page description language) data. An image expansion part 3 generates command and data for image development by images, graphic data, and flonts based on the output of the PDL process part 2. An image memory 5 has structure capable of holding plural color component data of plural pixels at a position specified with one address. Then an image memory control part 4 expands data of plural pixels at the specified address position in the image memory 5 at the same time based on the commands and data from the image expansion part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image processing device, and more particularly to coded font information from a host device,
The present invention relates to an image processing apparatus which receives graphic information and image information and forms a high resolution full color image.

[0002]

2. Description of the Related Art When a color image is formed using page description language (PDL) data composed of coded font information including color information, graphic information and image information as input data, The PDL data is decoded, expanded in a full-page image memory, and an image is formed based on it. Conventionally, in such an image processing apparatus, a plurality of bits (for example, 8 bits) are provided for each pixel for each color component (cyan, magenta, yellow, black) corresponding to a color material for forming a color image.
Bits). As a technique for forming such a color image at high speed, a memory element is assigned to each color component to configure an image memory, and a plurality of color component data can be simultaneously written while inputting a common address to each memory element. Techniques have been proposed to make it possible.

FIG. 15 is a block diagram showing the structure of an image memory in a conventional image processing apparatus. In FIG. 15, _5c is a cyan memory element, _5M is a magenta memory element, _5Y is a yellow memory element, and _5K is a black memory element. Each memory element _5c , _5M , _5Y ,
The 5 _K, the image memory for one page is formed. Further, a common address Ad is given to each of the memory elements 5 _c , 5 _M , 5 _Y and 5 _K, and at each position designated by the same, 8-bit color component data PD _C corresponding to one pixel. , PD _M , PD _Y , PD _K are written or read. The signal WE is a write enable signal.

Here, the operation of the one shown in FIG. 15 will be described by taking the case of writing data in the image memory as an example. When the address Ad and the write enable signal WE are applied to each of the memory elements 5 _c , 5 _M , 5 _Y , and 5 _K while the color component data PD _C , PD _M , PD _Y , and PD _K are applied, The data for one pixel is written at the position designated by the address Ad. Next, the color component data PD
_{When C} , PD _M , PD _Y and PD _K and the address Ad are changed to those of the next pixel and the write enable signal WE is applied, the data of the next pixel is written at the address.
When such an operation is repeated by the required number of pixels, predetermined image data is developed in the image memory.

A conventional document relating to such an image processing apparatus is, for example, Japanese Patent Laid-Open No. 4-277881.
There is a gazette.

[0006]

However, in the above-mentioned conventional technique, only one pixel data can be read / written by one address output. Therefore, 400 dpi
For high resolution full color printers such as
There has been a problem that the ratio of the image memory access time in the DL processing time increases, the performance overhead becomes remarkable, and the efficiency deteriorates. An object of the present invention is to solve such a problem.

[0007]

In order to solve the above problems, in the image processing apparatus of the present invention, the page description language processing means for decoding the input page description language data and the output of the page description language processing means are provided. An image developing means for generating a command and data for image development based on the image, an image memory for holding a plurality of color component data per pixel for a plurality of pixels at a position designated by one address, and the command and the data. Based on the above, the image memory control means for simultaneously developing data for a plurality of pixels is provided at a position designated by one address of the image memory.

[0008]

[Operation] The page description language processing means decodes the input page description language data, and the image expansion means generates an image expansion command and data. Then, the image memory control means, based on the image expansion command and data, at a position specified by one address of the image memory,
Data for a plurality of pixels having a plurality of color component data per pixel is simultaneously developed.

As described above, when the image is developed in the image memory, data for a plurality of pixels having a plurality of color component data per pixel is developed at the same time. Therefore, even in a high resolution full color printer or the like, The ratio of the access time of the image memory to the PDL processing time does not increase, and the efficiency does not decrease.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus of the present invention. In FIG. 1, 1 is an external interface, 2 is a PDL processing unit, 3 is an image developing unit,
Reference numeral 4 is an image memory control unit, 5 is an image memory, 6 is an output control device, and 7 is an output device.

The external interface 1 is a SCSI (Sma
ll Computer System Interface), a communication LSI (Large Scale Integration), or various buses tightly coupled to the host computer. The PDL processing unit 2 converts the page description language data received by the external interface 1 into data for image development by classifying it by image, graphic, and font type. The image development unit 3 draws based on the image development data received from the PDL processing unit 2, and passes the result to the image memory control unit 4.

The image memory control section 4 writes each color component data of a plurality of pixels in the image memory 5 by one-time address output based on the data received from the image developing section 3. In this embodiment, the color component data for 32 pixels is written in the image memory 5 by one address output. The image memory 5 has a structure in which 32 pixels are designated by the same address. Which of the 32 pixels is overwritten is
It is determined by the write enable signal WE. That is, in the pixels to which the write enable signal WE is not applied, the data is output to the data bus, but the writing of the data does not occur in the image memory. The output control device 6 controls output when the data in the image memory 5 is output from the output device 7.

FIG. 2 is a block diagram showing the configuration of the image memory in the image processing apparatus of the present invention. In FIG. 2, 50 _{C to} 531 _C are memory elements that store cyan color components, 50 _{M to} 531 _M are memory elements that store magenta color components, and 50 _{Y to} 531 _Y are yellow color components. Memory elements for storing, 50 _{K to} 531 _K, are memory elements for storing the color component of black. Also, four memory elements 5
One pixel of data is stored using 0 _C , 50 _M , 50 _Y , and 50 _K. The address terminals of each memory element are connected by one address line, and one address Ad is applied at the same time. Further, the write enable signals WE0 to WE31 are collectively applied to each pixel. And also, the data terminals of the memory device is eight in correspondence with the color components data PD _C 0 ~PD _K 31 of 8 bits.

FIG. 3 is a conceptual diagram of data storage on an image memory in the image processing apparatus of the present invention. d0, d1, ...
.., dN respectively correspond to one pixel, and each pixel has four types of 8-bit color component data of cyan C, magenta M, yellow Y, and black K. Then, in the first pixel corresponding part d0, four kinds of color component data P
D _C 0, PD _M 0, PD _Y 0 and PD _K 0 are stored, and color component data PD _C 1 and PD _M are stored in the next pixel corresponding part d 1.
1, PD _Y 1, and PD _K 1 are stored, and similarly, four types of color component data are stored in all pixel corresponding portions. Then, the writing and reading are performed by designating 32 pixels, for example, the pixel corresponding parts d0 to d31 with one address.

The configuration of each part of the image processing apparatus of the present invention will be described in detail below. FIG. 4 is a block diagram showing a schematic configuration of the PDL processing unit. Reference numeral 1 corresponds to that of FIG. 1, 20 is a CPU (central processing unit), 21 is a PDL code ROM (Read Only Memory), and 22 is a work RAM (Ran).
dom access memory), 23a is an image command register, and 23b is an image data FIFO (First In Firs).
t Out), 23c is the image status register, 24a
Is a graphics command register, 24b is a graphics data FIFO, 24c is a graphics status register, 25a is a font command register,
25b is a font data FIFO, and 25c is a font status register.

The CPU 20 is a CPU for code processing, and the PDL code ROM 21 stores a processing program for the CPU 20. The work RAM 22 serves as a work area for the CPU 20. CPU20 is PDL code ROM
External interface 1 according to 21 processing programs
The PDL data received from the device is converted into image development data for images, graphics, and fonts, and the respective commands and data are delivered to the image development unit 3. Image command register 23a,
Image data FIFO 23b, graphic command register 24a, graphic data FIFO 24b
, Font command register 25a and font data FIFO 25b.

An example of these commands and data is as follows. For images, <100,100,200,400, cmyk, 0,255,122,4, ............> fi
llImage This means that the image data of width 200 and height 400 centered on the coordinate (100,100) is drawn in the color specified for each pixel. "0,255,122,4, ..." Indicating the components are put in the image data FIFO 23b as data.

In the case of graphics, <100,100,200,200, cmyk 0,255,122,4> fillBOX This means to fill the inside of a rectangle whose coordinates are (100,100) and (200,200) with color components cmyk0,255,122 and 4. However, in the above command,
"100,100,200,200" is put in the graphic data FIFO 24b as data.

For fonts, <100,100,10, GothicFont, abcd, cmyk 0,255,122,4> Prin
tfont This is the 10 Gothic string "ab at coordinates (100,100)
cd ”is drawn with the color components cmyk0, 255, 122, and 4, but in the above command, the character string“ abcd ”is the font data FIFO 25 as data.
put in b.

FIG. 5 is a flow chart showing the processing in the PDL processing section. Step 1 ... Receives PDL data from the external interface 1. Step 2 ... Analyze the received command. Step 3 ... Determine what command the received command is.

Step 4 ... If the received command is an image drawing command, the processing of the previously issued image drawing command is completed, the image data FIFO 23b is empty, and the next command can be issued. Check whether or not. Step 5 ... If all is ok, it is checked whether or not the area of the image memory 5 in which the image is drawn does not overlap the area of the graphic and font drawing commands already issued to the image developing section 3. Step 6 ... If they do not overlap, a command is issued to the image processing unit 31 (FIG. 1).

Step 7 ... If it is a graphic drawing command in step 3, is it okay to issue the next command after the processing of the previously issued graphic drawing command is completed and the graphic data FIFO 24b is empty? Check whether or not. Step 8: If all is ok, it is checked whether the area of the image memory 5 in which the graphic is drawn does not overlap the area of the image and font drawing command already issued to the image developing unit 3. Step 9 ... If the opponents that do not overlap or if they overlap, even if they overlap, the graphic processing unit 32
Issue a command to (Fig. 1). It should be noted that the reason why the areas may be overlapped if the overlapping opponents have the same color font is that whichever is drawn first has the same result.

Step 10 ... If it is the font drawing command in step 3, the processing of the previously issued font drawing command is completed, the font data FIFO 25b is empty,
Check whether it is okay to issue the following command. Step 11 ... If all is ok, it is checked whether or not the area of the image memory 5 in which the font is drawn does not overlap the area of the image and graphic drawing command already issued to the image developing unit 3. Step 12 ... If the opponents who do not overlap or if they overlap each other have the same color, the font processing unit 33
Issue a command to (Fig. 1).

Step 13 ... If it is an output command in step 3, all the image, graphic and font drawing commands have been processed and drawing on the image memory 5 has been completed, so it is okay to issue an output command. Determine whether. Step 14 ... If it is all right, an output command is issued to the image memory control unit 4.

Step 15 ... If it is another instruction in Step 3, that command is processed. Step 16 ... It is judged whether or not the processing of all the PDL data has been completed, and if not completed, the procedure returns to Step 1.

Next, the detailed structure of the image expansion unit 3 will be described. The image developing unit 3 is divided into an image processing unit 31, a graphic processing unit 32, and a font processing unit 33. Figure 6
FIG. 6 is a block diagram showing a schematic configuration of each part of the image developing unit. FIG. 6A shows a configuration of the image processing unit 31.
6B shows the configuration of the graphic processing unit 32, and FIG.
Shows the configuration of the font processing unit 33. In FIG. 6, 310, 320 and 330 are CPUs, 311 is an image developing ROM, 312, 322 and 332 are work RAMs, 313 is an image buffer, 314 is an image command FIFO,
315 is a color data FIFO, and 316 and 324 are start point FIFOs.
O, 317 and 325 are end point FIFOs, 321 is a ROM for graphic expansion, 323 is a graphic command FIFO,
331 is a font expansion ROM, 333 is a font data ROM, 334 is a font command FIFO, and 335 is a font data FIFO.

The CPU 310 of the image processing unit 31 is a CPU for image image development processing, and is an image development RO.
M311 stores an image development processing program for the CPU 310. The work RAM 312 serves as a work area for the CPU 310, and the image buffer 313 serves as a CP.
The image image developed by U310 is temporarily stored.

The CPU 310 receives the image command register 23a and the image data FIF from the PDL processor 2.
When the image drawing command and the image drawing data are received via O23b, the image image is expanded in the image buffer 313 according to the image expansion processing program. When an image transfer instruction to the image memory 5 is received from the PDL processing unit 2, the work RAM 312 and the image
Based on the data stored in the buffer 313, FIG.
The command shown in FIG. 1A, the pixel data shown in FIG. 11B, and the start point and end point position data shown in FIGS. 11C and 11D are issued to the image memory control unit 4. It is issued by an image command FIFO 314, a color data FIFO 315, a start point FIFO 316 and an end point F.
Via IFO317.

The graphic processing section 32 shown in FIG.
Also, similar processing is performed in the font processing unit 33 shown in FIG. 6C, and the graphic command FIFO 323
, Start point FIFO324, end point FIFO325, font
Command FIFO334, font data FIFO335
Commands and data are delivered to the image memory control unit 4 via the above. In the case of a graphic, those commands and data are as shown in FIGS. 12A, 12B, and 12C, and in the case of a font, for example, as shown in FIG.
3 (a) and (b).

Next, the detailed structure of the image memory control unit 4 will be described. FIG. 7 is a block diagram showing a schematic configuration of the image memory control unit. The reference numeral corresponds to that of FIG.
Is an image memory control unit, 41 is a graphic memory control unit, 42 is a font memory control unit, 43 is a data packing unit, 44 is a data selector, 45 is an address selector, 46 is a memory access controller, 47 is a write enable selector, 48 is a graphic color data register, and 49 is a font color data register.

The image memory control unit 40 generates an address AdI of the image memory 5 whose (x, y) coordinates are converted based on the data rasterized by the image processing unit 31 of the image developing unit 3, and a write enable signal. WEI and memory access request signal / memory access completion signal R
Generate an AI. Similarly, also in the graphic memory control unit 41 and the font memory control unit 42, based on the data rasterized by the graphic processing unit 32 and the font processing unit 33, addresses AdG, AdF,
Write enable signals WEG, WEF and memory access request signals / memory access completion signals RAG, RAF are generated.

The memory access completion signal is a signal for the memory access controller 46 to notify the request source that issued the memory access request signal that the request cycle has been completed.

The memory access controller 46 includes a memory access request signal from the image processing unit 31, the graphic processing unit 32, and the font processing unit 33 of the image developing unit 3 shown in FIG. And a predetermined DR
Ras ^* and Cas ^* for AM are generated. The address Ad selected by the address selector 45 is output, and the selection signals S ₀ , S ₁ , S ₂ , and S ₃ for the data selector 44 and the write enable selector 47 are output.

The address selector 45 follows the instruction from the memory access controller 46, and the address generation units 401, 411, 421 of the image memory control unit 40, the graphic memory control unit 41, and the font memory control unit 42.
One of the addresses AdI, AdG, AdF output from is selected and output. Further, the write enable selector 47, according to the instruction from the memory access controller 46, the write enable generation units 402, 412, 422 of the image memory control unit 40, the graphic memory control unit 41, and the font memory control unit 42. One of the write enable signals WEI, WEG, and WEF output from is selected and output.

The data packing unit 43 is the image expansion unit 3
Image data processing unit 31 (FIG. 1) color data FIFO 31
The color data from 5 (FIG. 6 (A)) is received pixel by pixel and the data is stored. When the data for 32 pixels is stored, they are collectively output. In this way, each pixel data is packed in the maximum access width of the image memory so that the color change in pixel units in image processing does not become a bottleneck in accessing the image memory. In the case of graphics and fonts, since one image has a single color, it is not necessary to pack such data, and color data can be directly stored in the graphic color data register 48 and font color data register 49. Given.

The data selector 44, in accordance with the instruction of the memory access controller 46, displays the color data PDI of the image image from the data packing unit 43, the color data PDG of the graphic image from the graphic color data register 48 and the font.・ Color data PDF of the font image from the color data register 49
One of the above is selected and output.

Next, in the image memory control unit 4, x,
The configuration of the portion that generates the address Ad and the write enable signal WE from the y coordinate will be described by taking the image memory control unit 40 as an example. FIG. 8 is a block diagram showing an example of an address generation unit and a write enable generation unit in the image memory control unit. Reference numerals 316 and 317 correspond to those in FIGS. 6 and 7, 403 is a start point register, 404 is an end point register,
Reference numerals 405 and 408 are comparators, 406 is a control unit, 407 and 4072 are adders, and 409 is a drawing mask generation unit.

The start point register 403 and the end point register 404 are
Each time the scan line changes, the start point FIFO 316, the end point FI
From FO317, the start point and end point on the scan line are read and set. Start address register 40
70 holds the y-coordinate y1 indicating the first scan line, the product y1 × X _W in the x direction of the word number X _W of the image memory 5. The value is set by the image processing controller 400 (FIG. 7) of the image memory controller 40.

In the x-direction width register 4071, the image memory 5
Holds the number of words X _{W in} the x direction of the adder 407
, The value of the start address register 4070 is first set, and then the number of words X _W of the x-direction width register 4071 is added every time the scanning line changes. That is, in the adder 407, the start position of each scanning line (position of x = 0)
Will be set.

On the other hand, the load counter 4032 is set with upper bits other than the lower 5 bits of the start point register 403 every time the scanning line changes, and is incremented by 1 every time one word of data is written in the scanning line. It And the value of load counter 4032 is the adder
The value of 407 is input to the adder 4072 and added together, and the output of the adder 4072 becomes the address AdI of the image memory 5.
Here, the correspondence between the x and y coordinates of the image and the image memory address is conceptually shown in FIG.

The value of the load counter 4032 is also input to the comparator 405 where it is compared with the upper bits of the end point register 404. Then, the comparator 405 notifies the control unit 406 when the value of the load counter 4032 exceeds the value of the upper bit of the end point register 404. When the memory access controller 46 (FIG. 7) sends the memory access completion signal RAI, the control unit 406 outputs the count-up clock CC to the drawing mask generation unit 409. After that, the output of the count-up clock CC is stopped.

The drawing mask generator 409 uses the start point register 40.
3, the lower 5 bits 4031 and 4041 of the end point register 404 and the count-up clock CC from the control unit 406
The write enable signal WEI is generated. That is, the lower 5 bits 403 of the start point register 403 and the end point register 404
1, 4041 designates a pixel to be written in the image memory 5 out of 32 pixels to be processed at one time, and a pixel between the pixel indicated by the start point register 403 and the pixel indicated by the end point register 404 on the scanning line. About write enable signal W
Output EI.

In the above process, the y coordinate of the first scanning line is set as an initial value, and then the current scanning line register 4080 is incremented by the image processing control unit 400 (FIG. 7) of the image memory control unit 40. Is the value of
This is repeated until the y coordinate of the final scan line reaches the value of the final line register 4081 that has been set. Similar processing is performed in the graphic memory control unit 41 and the font memory control unit 42.

Next, the structure of the data packing unit 43 will be described. FIG. 9 is a block diagram showing an example of the configuration of the data packing unit. The reference numerals correspond to those in FIGS. 7 and 8, 430 is a data latch unit, 431 to 433 are pixel data latches, and 434 is a latch address encoder. The pixel data latches 431 to 433 latch data of 8 bits for each of cyan, magenta, yellow, and black color components, for a total of 32 bits of data.
The latch address encoder 434 sequentially designates pixel data latches based on the lower 5 bits of the load counter 4032 of the image memory control unit 40, and the designated pixel data latches 431 to 433 are respectively designated at that time. Latches the data given by the color data FIFO 315.

Next, the structure of the data selector 44 will be described. FIG. 10 is a block diagram showing an example of the configuration of the data selector. In FIG. 10, 441 to 444 are 4-input 1-output selectors. 4-input 1-output selector 441-444
Is 32 for each of the color components of cyan, magenta, yellow, and black for each pixel, and there are 32 pixels in total, and a total of 1024 are arranged. Then, each of the 4-input 1-output selectors 441 to 444 has 4
One bit of each image data of image, graphic, and font is input to three of the three input terminals, and one of them is selected and output. The selection is performed by the select signals S ₀ and S ₁ provided from the memory access controller 46 (FIG. 7). For example, when the select signals S ₀ and S ₁ are both “0”, image data is output and the select signal S ₀ is “0”.
When the select signal S ₁ is “1”, graphic data is output, and when the select signal S ₀ is “1” and the select signal S ₁ is “0”, font data is output.

Write enable register 47 in FIG.
The address selector 45 can also be realized by a configuration similar to that of the data selector. However, the number of 4-input / 1-output selectors is the same as the number of pixels (32 in the write enable register 47 that corresponds to the number of pixels to be simultaneously written by one address output).
In the address selector 45, the number corresponds to the number of bits of the address.

The image memory control unit 4 as described above
For example, when the image drawing command, the data and the start point and the end point as shown in FIGS. 11A to 11D are input, as shown in FIG. 11E, on the scanning line from y1 to y1 +3. Between each start point X _s1 , X _s2 , ... And each end point X _e1 , X _e2 ,.
X _s1 , y ₁ ), pixel (X _s1 + 1, y ₁ ), ... Gives an image filled with pixels of the colors individually designated.

When a graphic drawing command and a start point and an end point as shown in FIGS. 12A to 12C are input, as in the case of FIG. 11E, on the scanning lines from y1 to y1 + 3. Each starting point X _s1 , X _s2 , ... And each end point X
An image in which the spaces between _e1 , X _e2 , ... Are filled is obtained. However, each pixel has the same color specified by "set cmyk 0,255,0,0", that is, the same color in magenta.

When a font drawing command and bitmap data as shown in FIGS. 13 (a) and 13 (b) are input, the width W and height H as shown in FIG. 13 (c).
As shown in FIG. 13D, the character having the size of is expanded from the coordinates (x ₀ , y ₀ ) of the image memory 5 as a starting point.
Then, the color becomes the color specified by "cmyk 0,255,122,4".

In the above embodiment, the color space is CMYK.
However, the present invention is not limited to this, and another color space, for example, an RGB, CIE-based color space may be used.

[0051]

As described above, in the image processing apparatus of the present invention, in developing an image in the image memory, data for a plurality of pixels having a plurality of color component data per pixel is simultaneously developed. . Therefore, even in a high-resolution full-color printer or the like, the ratio of the image memory access time to the PDL processing time does not increase, and the efficiency does not decrease.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration of an image memory in the image processing apparatus of the present invention.

FIG. 3 is a conceptual diagram of data storage on an image memory in the image processing apparatus of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of a PDL processing unit.

FIG. 5 is a flowchart showing processing in the PDL processing unit.

FIG. 6 is a block diagram showing a schematic configuration of each part of an image expansion unit.

FIG. 7 is a block diagram showing a schematic configuration of an image memory control unit.

FIG. 8 is a block diagram showing an example of an address generation unit and a write enable generation unit in the image memory control unit.

FIG. 9 is a block diagram showing an example of the configuration of a data packing unit.

FIG. 10 is a block diagram showing an example of the configuration of a data selector.

FIG. 11 is a diagram showing an example of data given to an image / data control unit and an image corresponding to the data.

FIG. 12 is a diagram showing an example of data given to a graphic data control unit.

FIG. 13 is a diagram showing an example of data given to a font / data control unit and an image corresponding to the data.

FIG. 14 is a conceptual diagram showing a correspondence relationship between x, y coordinates and an image memory address.

FIG. 15 is a block diagram showing a configuration of an image memory in a conventional image processing apparatus.

[Explanation of symbols]

1 ... External interface, 2 ... PDL processing unit, 20,
310, 320, 330 ... CPU, 21 ... PDL code ROM, 22 ... Work RAM, 3 ... Image development unit, 31
Image processing unit 311, Image development ROM, 3
12 ... Work RAM, 313 ... Image buffer,
32 ... Graphic processing unit, 321 ... Graphic expansion ROM, 322 ... Work RAM, 33 ... Font processing unit, 331 ... Font expansion ROM, 332 ... Work RAM, 333 ... Font data ROM, 4 ... Image memory control Section, 40 ... Image memory control section, 403
... Start point register, 404 ... End point register, 405,40
8 ... Comparator, 406 ... Control unit, 407, 4072 ... Adder, 4070 ... Start address register, 407
1 ... Word number register, 4080 ... Current scan line register, 4081 ... Last line register, 409 ... Drawing mask generation unit, 41 ... Graphic memory control unit, 4
2 ... Font memory control unit, 43 ... Data packing unit, 430 ... Pixel data latch unit, 434 ... Latch address encoder, 44 ... Data selector, 4
41-444 ... 4-input 1-output selector, 45 ... Address
Selector, 46 ... Memory access controller, 4
7 ... write enable selector, 48 ... graphics color data register, 49 ... font color data register, 5 ... image memory, 5c~5 _K, 50 _C
~ 531 _C , 50 _M ~ 531 _M , 50 _Y ~ 531 _Y , 5
0 _{K to} 531 _K ... Memory element, 6 ... Output control device, 7 ...
Output device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06T 1/00 G09G 5/02 C 9377-5H 5/36 530 H 9377-5H H04N 1/21 G06F 15/64 450 D 15/66 310

Claims (1)

[Claims] 1. A page description language processing means for decoding input page description language data, and an image expansion means for generating an image expansion command and data based on an output of the page description language processing means. An image memory for holding a plurality of pixels of a plurality of color component data per pixel at a position designated by an address, and a plurality of pixels for a position designated by one address of the image memory based on the command and data. And an image memory control means for simultaneously expanding the data of 1. in the image processing apparatus.