JPH0855480A - Electronic circuits for semiconductor memory or the like - Google Patents

Abstract

PURPOSE:To prevent noise from propagating through internal wirings, to obtain a storage device having a good characteristic and to make the deign of an internal power source step-down circuit itself easy by dividing the internal power source step-down circuit into plural circuits. CONSTITUTION:A first internal power source step-down circuit 1 is connected with a base voltage generating circuit 2 in which a voltage fluctuation is required to be avoided most, a third internal power source step-down circuit 9 is connected with a sense amplifier circuit 10 which is a large noise generating source and is susceptible to receive the influence of noise and a forth internal power source step-down circuit 11 is connected with a data buffer circuit 12 being a large noise generating source. Moreover, a clock generator circuit 4, a column address buffer circuit 5 and a row address buffer circuit 6 which do not generate noise relatively are connected with a second internal power source step-down circuit 3 as a group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit represented by a semiconductor memory such as a DRAM or SRAM having an internal power supply voltage down circuit.

[0002]

2. Description of the Related Art Generally, a volatile memory device is a DRAM.
(Dynamic Random Access Memory) and SRAM (Static Ra
ndom Access Memory). In these memory devices, in recent years, circuits have been further miniaturized with the increase in memory capacity. As described above, when the circuit is miniaturized, the internal electric field increases, and the reliability as a memory element may be impaired. Therefore, the internal power supply voltage down circuit is adopted.

For example, as shown in FIG. 8, an internal power supply voltage step-down circuit 51 disclosed in Japanese Patent Laid-Open No. 3-237685 (G11C11 / 41) has a pMOS transistor 52 having a source as an external power supply Vcc and a drain as an internal power supply. V
By connecting to INT and controlling the gate voltage by the reference voltage generating circuit RVG, the external power supply voltage Vcc is stepped down to a desired internal power supply voltage Vint and supplied to the entire circuit.

Such an internal power supply step-down circuit 51 has a DR
In AM, they are connected as shown in FIG. That is, the internal power supply voltage down circuit (VINT GEN) 51 includes a clock generator circuit (CG) 53, an address buffer circuit (AB) 54, a row decoder circuit (RD) 55, a column decoder circuit (CD) 56, and a sense amplifier circuit ( SA)
57, a data buffer circuit (DB) 58, and a base voltage generating circuit 59, which are commonly connected to the internal power supply voltage down circuit 5
The internal power supply voltage VINT from 1 is supplied to each circuit.
Reference numeral 60 is a memory cell (MC).

[0005]

In a semiconductor memory device such as a DRAM, each of the circuits 53 to 59 causes noise in the internal wiring or is affected by noise from the internal wiring. Further, the degree thereof also varies depending on each circuit. In the conventional example, since the internal power supply step-down circuit 51 is commonly connected to each of the circuits 53 to 59, noise from a certain circuit causes the voltage of the internal power supply step-down circuit 51 to fluctuate, which causes other circuits to change. May cause malfunctions, and also cause the base voltage to fluctuate,
There is a possibility that characteristics of other elements such as a transistor which receives the supply of the base voltage are deteriorated.

FIG. 7 is a time chart showing variations of the externally applied voltage VCC, the internal power supply voltage VINT, the ground voltage VSS and the base voltage VBB in the DRAM circuit of FIG. 6 during operation. Every time each circuit operates, the internal power supply voltage V
The INT voltage fluctuates, and the base voltage VBB fluctuates due to the fluctuation.

Since the fluctuation of the internal power supply voltage affects the base voltage in this way, when designing the internal power supply voltage down circuit 51, the relation between each circuit and noise, that is,
It is necessary to consider all of the current consumption of each circuit, the operation timing, and L, C, R parasitic on the internal wiring lined up in the chip, and it is difficult to design accurately. Further, since the relationship between each circuit and noise changes depending on the layout of the circuits, it is necessary to design the internal power supply step-down circuit after the system and pattern of the circuit are determined, which makes the circuit design more difficult. It was a factor.

The present invention relates to improvement of an electronic circuit such as a semiconductor memory, and solves such a problem.

[0009]

An electronic circuit such as a semiconductor memory according to claim 1 is composed of a base voltage generating circuit, a sense amplifier circuit, etc., and an internal power supply for stepping down a power supply voltage. A step-down circuit is provided for each circuit individually. An electronic circuit such as a semiconductor memory according to claim 2 is configured by collecting a base voltage generating circuit, a sense amplifier circuit, and the like, and each circuit is grouped and shared by each circuit in the group. The connected internal power supply voltage down circuit is provided corresponding to each group.

Further, in an electronic circuit such as a semiconductor memory according to a third aspect of the present invention, the groups are segmented according to noise characteristics. In an electronic circuit such as a semiconductor memory according to a fourth aspect of the present invention, circuits that do not generate noise relatively are grouped together. In an electronic circuit such as a semiconductor memory according to a fifth aspect of the present invention, circuits susceptible to noise are connected to different internal power supply voltage down circuits.

In an electronic circuit such as a semiconductor memory according to a sixth aspect of the present invention, circuits that are likely to generate noise are connected to different internal power supply voltage down circuits. In the electronic circuit such as the semiconductor memory according to the seventh aspect, a circuit which is not easily affected by noise is directly connected to the power supply voltage. In an electronic circuit such as a semiconductor memory according to an eighth aspect, a circuit that is not easily affected by noise is commonly connected to an internal power supply voltage down circuit that is connected to a circuit that is easily affected by noise.

According to a ninth aspect of the present invention, an electronic circuit such as a semiconductor memory has a first internal power supply voltage down circuit connected to a base voltage generation circuit and a third internal power supply voltage down circuit connected to a sense amplifier circuit. And a fourth internal power supply voltage down circuit connected to the data buffer circuit. An electronic circuit such as a semiconductor memory according to claim 10
A second internal power supply voltage down circuit to which a clock generator circuit and an address buffer circuit, which generate relatively little noise, are connected in common is provided.

According to the eleventh aspect of the present invention, an electronic circuit such as a semiconductor memory is provided with an internal power supply voltage down circuit connected to a row decoder circuit. In an electronic circuit such as a semiconductor memory according to a twelfth aspect, an internal power supply voltage down circuit connected to the sense amplifier circuit is provided independently of other internal power supply voltage down circuits.

An electronic circuit such as a semiconductor memory according to a thirteenth aspect is one in which at least one of the base voltage generating circuit and the data buffer circuit is directly connected to the power supply voltage.

[0015]

In other words, in a circuit composed of a base voltage generating circuit, a sense amplifier circuit, etc., an internal power supply step-down circuit for stepping down the power supply voltage is provided for each circuit, so that the internal wiring from a certain circuit can be reduced. Even if noise is generated, the internal power supply step-down circuit connected to the other circuit functions as a noise filter, and it is possible to prevent the noise from being transmitted to the other circuit.

For example, by connecting circuits susceptible to noise to separate internal power supply voltage down circuits, each internal power supply voltage down circuit prevents noise from entering from other circuits. Specifically, the first internal power supply voltage step-down circuit is connected to the board voltage generation circuit that is most required to avoid voltage fluctuations, and the sense amplifier circuit that is a large noise source and is susceptible to noise is The internal power supply voltage down circuit is connected, and the fourth internal power supply voltage down circuit is connected to the data buffer circuit which is a large noise source.

When the operation of the row decoder circuit cannot be ignored due to the higher integration of the memory, an internal power supply voltage down circuit is provided exclusively for the row decoder circuit. In addition, an internal power supply voltage down circuit connected to the sense amplifier circuit, which is a large noise generation source and is most susceptible to noise in the circuit, is provided independently of other internal power supply voltage down circuits.

Further, by connecting circuits that are likely to generate noise to different internal power supply voltage down circuits, it becomes difficult for noise generated by itself to be transmitted to other circuits. In addition, each circuit is divided according to the characteristics against noise so that the circuits that do not generate relatively noise are grouped in common, and the internal power supply step-down circuit commonly connected to each circuit in the group is The number of internal power supply step-down circuits can be reduced by providing them corresponding to each group.

Specifically, a clock generator circuit and an address buffer circuit which do not generate relatively noise are connected as a group to the second internal power supply voltage down circuit. As described above, the characteristics of the circuits in the group are similar to each other, so that the characteristics can be easily grasped in terms of design. Further, by directly connecting the circuit which is not easily affected by noise to the power supply voltage, the internal power supply voltage down circuit can be omitted accordingly.

Further, a circuit that is not easily affected by noise is
By commonly connecting to the internal power supply voltage down circuit which is connected to a circuit susceptible to noise, the number of internal power supply voltage down circuits is reduced. In addition, when the capacity of the power supply voltage is sufficient and is not affected by a little noise, at least one of the board voltage generation circuit and the data buffer circuit is directly connected to the power supply voltage to obtain a high output level and gain. .

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described with reference to the drawings. The number of internal power supply voltage down circuits and the connection form with each circuit should be determined according to the system mounted on the chip. FIG. 1 shows the DR in the first embodiment.
It is a block configuration diagram of an AM circuit.

The difference from the conventional example shown in FIG. 6 is the configuration in which four internal power supply voltage down circuits are independently provided and the connection form between each internal power supply voltage down circuit and the internal circuit. That is, in order to suppress the fluctuation of the board voltage as much as possible, the board voltage generating circuit (VINT1 GEN) 1 is connected to the board voltage generating circuit (V
Only BB GEN) 2 is connected.

Second internal power supply voltage down circuit (VINT2 GE
N) 3 includes a clock generator circuit (CG) 4, a column address buffer circuit (CAB) 5, and a row address buffer circuit (RAB) that generate relatively little power supply noise.
6, a row decoder circuit (RD) 7 and a column decoder circuit (CD) 8 are commonly connected. Only the sense amplifier circuit (SA) 10 that generates large power supply noise is connected to the third internal power supply voltage down circuit (VINT3 GEN) 9.

Fourth internal power supply step-down circuit (VINT4GE
N) 11 is connected only to the data buffer circuit (DB) 12 that generates a large power supply noise. FIG. 2 is a time chart for examining the voltage fluctuation condition of this DRAM circuit. By the operation of a certain circuit, VINT1 which is each internal power supply voltage of the first internal power supply voltage down circuit 1, the second internal power supply voltage down circuit 3, the third internal power supply voltage down circuit 9 and the fourth internal power supply voltage down circuit 11. Any of VINT4 fluctuates.

Due to this fluctuation, the externally applied voltage VCC also slightly changes. However, since another independent internal power supply voltage down circuit is interposed in other circuits, this internal power supply voltage down circuit serves as a noise filter, and the influence of power supply noise can be suppressed to a very small level. In addition, the fluctuation of the base voltage VBB can be suppressed to be small accordingly. FIG. 3 is a block diagram of a DRAM according to the second embodiment.

In this example, the fifth internal power supply step-down circuit (V
A clock generator circuit (CG) 4, a column address buffer circuit (CAB) 5, a row address buffer circuit (RAB) 6, a row decoder circuit (RD) 7, and a column decoder circuit which do not generate power supply noise in the INT 5 GEN) 13 relatively. (CD) 8 are commonly connected. The sense amplifier circuit 10 is the largest source of power supply noise and is most susceptible to the power supply noise.
6th internal power supply voltage down circuit (VINT6GEN) 1
Connected to 4.

Further, in order to obtain a higher output potential level and higher gain, the externally applied voltage Vcc is directly applied to the base voltage generating circuit 2 and the data buffer circuit 12. In this case, the externally applied voltage Vcc needs to have a sufficient capacity not to be affected by noise. FIG. 4 is a block diagram of a DRAM circuit according to the third embodiment.

As the memory is highly integrated and the number of bits is increased,
Since the number of memory cells (MC) 60 operating simultaneously increases rapidly, the numbers of sense amplifier circuits (SA) 10 and row decoders (RD) 7 also increase rapidly. As a result, the influence of the circuit operation of the row decoder (RD) 7 on the fluctuation of the internal power supply voltage becomes so large that it cannot be ignored. Therefore, an internal power supply voltage down circuit dedicated to the row decoder (RD) 7 is provided.

That is, in order to suppress the fluctuation of the board voltage as much as possible, only the board voltage generating circuit (VBB GEN) 2 is connected to the first internal power supply voltage down circuit (VINT1 GEN) 1. Seventh internal power supply voltage down circuit (VINT7 GEN)
15 is a row decoder (RD) for the above reason.
Only 7 are connected.

Eighth internal power supply voltage down circuit (VINT8 GE
N) 16 includes a clock generator circuit (CG) 4, a column address buffer circuit (CAB) 5, and a row address buffer circuit (RAB) that generate relatively little power supply noise.
6 and a column decoder circuit (CD) 8 are commonly connected. 9th internal power supply voltage down converter (VINT3 GEN) 1
Only a sense amplifier circuit (SA) 10 that generates a large power supply noise is connected to 7.

Fourth internal power supply step-down circuit (VINT4GE
N) 11 is connected only to the data buffer circuit (DB) 12 that generates a large power supply noise. FIG. 5 is a block diagram of the SRAM circuit according to the fourth embodiment. Although there is a difference between the DRAM and the SRAM, the number of internal power supply voltage down circuits and the connection form are the same as those in the first embodiment.

In addition to the above embodiments, the following modifications are possible. 1) If there is a circuit that is not easily affected by noise even if the capacity of the externally applied voltage Vcc is not sufficiently large, it may be directly connected to the externally applied voltage Vcc without going through the internal power supply voltage down circuit. 2) A circuit that is strong against noise and a circuit that is a source of noise are connected to one internal power supply voltage down circuit. For example, possible combinations of the circuits of this embodiment include a clock generator circuit (CG) 4 that is extremely hard to generate noise and is not easily affected by noise, and a sense amplifier circuit (SA that easily generates noise). ) 10 and 10 to the internal power supply step-down circuit of the supply. Sense amplifier circuit (SA) 10
Although it is itself very weak against noise, the clock generator circuit (CG) 4 hardly generates noise, so there is almost no problem.

[0033]

In the electronic circuit such as the semiconductor memory of the present invention, the internal power supply voltage step-down circuit functioning as a noise filter is provided for each individual circuit or for each circuit group, so that the noise generated through the internal wiring is reduced. Prevent the propagation of
It is possible to obtain a product with good characteristics.

Moreover, compared to designing an internal power supply voltage down circuit common to all circuits, the current consumption of each circuit, the operation timing, etc. can be grasped easily, the design is facilitated, and the design accuracy is improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a time chart in which the voltages at main points in FIG. 1 are measured.

FIG. 3 is a block configuration diagram of a DRAM according to a second embodiment of the present invention.

FIG. 4 is a block configuration diagram of a DRAM according to a third embodiment of the present invention.

FIG. 5 is a block configuration diagram of an SRAM according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a conventional DRAM.

FIG. 7 is a time chart in which the voltages at main points in FIG. 6 are measured.

FIG. 8 is a schematic diagram showing a general step-down circuit.

[Explanation of symbols]

 1 first internal power supply voltage down circuit 2 base voltage generation circuit 3 second internal power supply voltage down circuit 4 clock generator circuit (CG) 5 column address buffer circuit (CAB) 6 row address buffer circuit (RAB) 7 row decoder circuit (RD) ) 8 column decoder circuit (CD) 9 third internal power supply voltage down circuit 10 sense amplifier circuit (SA) 11 fourth internal power supply voltage down circuit 12 data buffer circuit (DB) 13 fifth internal power supply voltage down circuit 14 sixth Internal power supply voltage down circuit 15 Seventh internal power supply voltage down circuit 16 Eighth internal power supply voltage down circuit 17 Ninth internal power supply voltage down circuit 60 Memory cell

Claims (13)

[Claims] 1. A base voltage generating circuit, a sense amplifier circuit, and the like are assembled, and an internal power supply step-down circuit for stepping down a power supply voltage is provided for each circuit individually. Electronic circuits such as semiconductor memory. 2. A base voltage generating circuit, a sense amplifier circuit, etc. are assembled together, each circuit is grouped, and an internal power supply step-down circuit commonly connected to each circuit in the group is provided in each group. An electronic circuit such as a semiconductor memory, which is provided correspondingly to each. 3. An electronic circuit such as a semiconductor memory according to claim 2, wherein the group is divided according to a noise characteristic. 4. An electronic circuit such as a semiconductor memory according to claim 2, wherein circuits that do not generate relatively noise are grouped in common. 5. The circuit susceptible to noise is connected to separate internal power supply voltage down circuits.
5. An electronic circuit such as the semiconductor memory according to any one of 4 to 4. 6. An electronic circuit such as a semiconductor memory according to claim 1, wherein circuits that are likely to generate noise are connected to different internal power supply voltage down circuits. 7. An electronic circuit such as a semiconductor memory according to claim 1, wherein a circuit which is not easily affected by noise is directly connected to a power supply voltage. 8. The circuit according to claim 2, wherein a circuit which is not easily influenced by noise is commonly connected to an internal power supply voltage down circuit which is connected to a circuit which is easily influenced by noise. Electronic circuits such as semiconductor memory. 9. A first internal power supply voltage down circuit connected to the base voltage generation circuit, and a third internal power supply voltage down circuit connected to the sense amplifier circuit.
2. An electronic circuit such as a semiconductor memory, comprising: the internal power supply voltage down circuit of 4) and a fourth internal power supply voltage down circuit connected to the data buffer circuit. 10. An electronic device for a semiconductor memory or the like according to claim 9, further comprising a second internal power supply step-down circuit to which a clock generator circuit and an address buffer circuit which are relatively noise-free are connected in common. circuit. 11. An internal power supply voltage down circuit connected to a row decoder circuit is provided.
An electronic circuit such as the semiconductor memory described in 1. 12. An electronic circuit such as a semiconductor memory in which an internal power supply voltage down circuit connected to a sense amplifier circuit is provided independently of other internal power supply voltage down circuits. 13. An electronic circuit such as a semiconductor memory according to claim 12, wherein at least one of the base voltage generating circuit and the data buffer circuit is directly connected to the power supply voltage.