JPH08298492A - Multi-frame synchronization circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a multi-frame synchronization circuit capable of performing multi-frame synchronization protection for a plurality of time slots and having a short waiting time for re-synchronization when a reception target time slot is changed. [Structure] One synchronization circuit for detecting and outputting a reference multi-frame synchronization signal from a received multi-frame signal, and reference multi-frame synchronization provided for each reception processing target time slot and detected by each one synchronization circuit. A phase adjustment circuit configured to detect a phase difference between a signal phase and a received multi-frame synchronization signal, and selectively output a synchronization signal obtained by shifting the phase of the reference multi-frame synchronization signal according to the phase difference. It

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiframe synchronizing circuit. In particular, for a signal from a communication line operating in a so-called multi-frame manner, which has a plurality of time slots in one frame such as a digital primary group transmission line and in which information is periodically carried over a plurality of frames. The present invention relates to a circuit for processing multiframe synchronization.

[0002]

2. Description of the Related Art When performing reception processing for a plurality of time slots of a transmission line (communication line) as described above, it is necessary to carry out synchronization protection by using a multi-frame synchronization signal given to each time slot. There is.

However, in the public line, the multi-frame phase is often different due to passing through multiple stages of demultiplexers on the way and different routes between time slots. For this reason, in the past, when performing reception synchronization processing for a plurality of time slots, it is general to prepare multiple frame synchronization circuits for the number of time slots to be received and synchronize each time slot. .

Further, the above will be described with reference to the drawings.
FIG. 5 is a diagram showing a configuration example of a multi-frame for explaining the problem of the conventional example. In the figure, A, B, C ...
Is information on each line, for example, a multiframe information string for 24 lines.

Reference numeral 10 is a frame formed by multiplexing each multi-frame line. Here, each line signal is, for example, a signal of 64 Kbps, forms one frame every 20 ms, and a head identification bit MF is attached to the head of the frame.

The signal of each line is assigned to one time slot of frame 10 in units of 8 bits. The frame 10 constitutes one frame with 24 time slots.

In FIG. 5, the multiframes of the line A and the line C are synchronized, and the respective head identification bits MF are in the same frame in the frame 10 (MF-
A, MF-C). However, the line B shows a case where the multiframes are not synchronized with the lines A and C, and therefore the head identification bit MF is arranged at a different frame position in the frame 10 (MF-B). .

[0008]

As described above, the fact that the positions of the head identification bits MF, that is, the phases, shift due to the synchronism of a plurality of lines, as described above, is due to the multiple demultiplexing in the middle. This is because the route goes through the device and the route is different for each line. Therefore, in the reception process,
It was necessary to prepare a synchronization circuit for the line.

However, the multi-frame generally extends from several tens to several hundreds of frames, and from several tens of milliseconds to several seconds in terms of time, which constitutes a big problem in terms of the circuit scale in constructing multiple systems of the synchronizing circuit.

Also, backward protection for multi-frame synchronization,
Usually, synchronization protection such as forward protection is applied, but for example, when the reception target time slot is switched, it is necessary to resynchronize with a new time slot. For this reason, there is a problem that reception cannot be started until after a delay corresponding to the number of protection steps.

From this point of view, it is an object of the present invention to enable multiframe synchronization protection for a plurality of time slots with a relatively small circuit, and to shorten the resynchronization waiting time when the reception target time slot is changed. It is to provide a multi-frame synchronization circuit.

[0012]

In order to achieve the above-mentioned object of the present invention, a multi-frame synchronizing circuit according to claim 1 detects and outputs a reference multi-frame synchronizing signal from a received multi-frame signal. One synchronization circuit, which is provided for the number of timeslots to be subjected to reception processing, and detects the phase difference between the phase of the reference multi-frame synchronization signal and the received multi-frame synchronization signal, which are respectively detected by the one synchronization circuit, It is configured to have a phase adjustment circuit that selectively outputs a synchronization signal obtained by shifting the phase of the reference multi-frame synchronization signal according to the phase difference.

According to a second aspect of the present invention, there is provided the multi-frame synchronization circuit according to the first aspect, wherein at least the same number of sets of reception-target time slots as the multi-frame phase shift amount between the time slots of the received multi-frame signal. , And the one synchronization circuit obtains the OR logic of the outputs of the same stages of the shift registers of the set number, and obtains the AND logic of the OR logic of the obtained number of stages. A logic circuit and a counter for counting the output of the logic circuit by a number corresponding to the number of multiframes of the received multiframe signal, the counter having a value equal to the number of sets by the output of the logic circuit. Set,
When the count value becomes 0, the reference multi-frame synchronization signal is output.

Further, in the multi-frame synchronization circuit according to a third aspect of the present invention, in the first aspect, the number of timeslots to be subjected to reception processing is at least the same number of sets as the multi-frame phase shift amount between the time slots of the received multi-frame signal. , And each of the phase adjustment circuits compares with the state of the previous frame in which of the shift registers the multi-frame synchronization signal of one time slot has been latched. By doing so, the frame synchronization status is determined, and the corresponding phase-shifted reference multi-frame synchronization signal is output.

In the above-mentioned structure, the reference multi-frame synchronization signal is given by one synchronization circuit, the phase of the received multi-frame signal is further compared, and a plurality of phase-shifted reference multi-frame synchronization signals are used in correspondence with the phase difference. A reference multi-frame sync signal for As a result, it becomes possible to control the synchronization of multi-frame signals of a plurality of time slots with a single common synchronization circuit.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar parts will be described with the same reference numerals and symbols.

As an embodiment of the present invention, consider a transmission path model as shown in FIG. That is, here, the transmission rate is 1.
It is 544 Mbps, and shows an example when the primary group transmission line is operated in 160 multi-frames. In this case, the frame length is 125 μs, the frame is composed of 24 TSs, the number of bits per TS is 8, and the transmission rate is 1.
Since it is 544 Mbps, the line speed of 1TS is 64 kbps
Becomes

It is assumed that the first, second and eighteenth TSs are received from this transmission line, and the multiframe is 160
It is assumed that the frame is operated at 20 ms cycle.

In such a case, the MF phase of each TS is shifted because the transmission path is managed in units of handling groups, as already described, and the paths that pass when the groups are different. Is changed and the delay is changed. Therefore, here, it is considered that the shift amount is at most 1 to 2 frames and the maximum shift amount n is 3 frames.

FIG. 1 is basically the same as the multi-frame structure described in the conventional example of FIG. 5, but in this model, as described above, the first, second, and eighteenth time slots (TS1, TS2). , TS18) are assumed to be received.

Further, as shown in FIG. 1, it is assumed that TS1 and TS2 are in phase and TS18 is delayed by one multiframe. That is, regarding the multi-frame shown in the lower part of FIG. 1, the MF of TS18, in which the leading bit of the multi-frame is shown in the square mark, is shown at a time point delayed by one multi-frame from that of TS1 and TS2.

FIG. 2 is a block diagram of an embodiment of a multi-frame synchronization circuit according to the present invention. In the figure, reference numeral 11 is a shift register for extracting the first bit MF of a reception target time slot (hereinafter referred to as TS) and latching n sets (n = 3 in the embodiment) in the order of TS1 → TS2 → TS18.

Reference numeral 20 is a reference multi-frame signal generation circuit, and all TSs to be received in the shift register 11 are received.
It has a circuit 12 for detecting the arrival of the MF bit of and a multi-frame counter 13 which uses the output of this circuit as a re-initialization signal. This reference multi-frame signal generation circuit generates a reference multi-frame (MF) signal.

Further, in FIG. 2, reference numeral 21 is a multi-frame (MF) phase adjustment circuit. This circuit is prepared for each TS to be received. In the MF phase adjustment circuit 21, 14 is a phase comparison circuit that compares the present arrival amount (new) and the previous arrival amount (old) for the MF bit phase of a certain reception target TS.

Reference numeral 15 is a circuit for performing phase adjustment on the reference multiframe from the MF counter 13 according to the phase comparison result of the phase comparison circuit 14 to generate a multiframe for its own TS.

Reference numeral 16 is a synchronization protection circuit which controls the front protection and the rear protection by the output signal of the phase comparison circuit 14. As shown in FIG. 2, in the configuration of the embodiment of the present invention, the counter operating in the multi-frame cycle is 1
There are only one MF counter 13, and the phase comparison circuit 14,
The TS MF phase adjustment circuit 21 including the own TS multi-frame generation circuit 15 and the synchronization protection circuit 16
By preparing the number of TSs to be received, necessary MF signals for each TS are generated.

Details of the operation of the embodiment of FIG. 2 will be described below with reference to the reference multi-frame signal generation circuit 20 and the multi-frame (M
F) A description will be given according to the configuration example of the phase adjustment circuit 21.

FIG. 3 shows a reference M in the configuration of the embodiment shown in FIG.
3 is a block diagram of a detailed configuration example of an F signal generation circuit 20. FIG. In this figure, the number of reception target TSs is m = 3, and the maximum amount of MF phase shift for each TS is n = 3.

In the figure, the blocks arranged vertically on the left side correspond only to the first bit of the receiving target TS (TS1, TS2, TS18) corresponding to the maximum amount n = 3 of the MF phase shift for each TS.
A shift register 11 for latching three frames. Furthermore, in the figure, the shaded portion of the shift register 11 indicates that it is an MF bit.

With the above configuration, in FIG. 3, in the shift register 11 for three frames, the first frame (1fr).
Is empty, MF of TS1 and TS2 in the second frame (2fr)
Indicates that the MF of the TS18 is included in the third frame (3fr).

In FIG. 3, reference numeral 12 denotes an all-MF arrival detection circuit, in which the parallel output of the shift register 11 is TS.
Each is summarized by OR-AND logic. And M for all TS
A signal indicating whether or not F is complete is generated.

That is, the OR circuits 121, 122, 123.
Outputs a logical "1" when the leading bits MF of TS1, TS2 and TS18 respectively appear in any of the three frames. The state shown in FIG. 3 is for all TSs to be received, that is, TS1, TS2 and TS.
18 is in the received state.

Therefore, the OR circuits 121, 122, 1
The AND circuit 124 to which the output of 23 is input detects that all the leading bits MF of TS1, TS2 and TS18 are present in three frames, and outputs a logic "1" to the multi-frame counter 13.

The multi-frame counter 13 has a structure of free-running from 0 to 159 corresponding to 160 multi-frames, and sets a value "3" when the logical "1" is output from the AND circuit 124. Further, when the counter value indicates 0, a pulse is output. Therefore, the MF is added to the shift register of the first frame (1fr).
It is possible to obtain a reference MF that is the same as the phase when is latched.

In the present invention, as shown in FIG. 3 above, first, it waits for all the MF bits of the TS to be received to be taken into the shift register 11 which is updated at the frame cycle. When the MF having the latest phase arrives at the shift register section, the MF counter is initialized.

At this time, the counter 13 is set to n (“3” in the above example), where n is the expected maximum deviation amount of each MF bit for each TS.
If initialized to, the reference MF that matches the fastest phase can be obtained.

By passing this reference MF through a 2-bit shift register 21-0 that shifts in frame units in FIG. 4 to be described below, MFs having the same phase as the second frame and the third frame can be prepared.

FIG. 4 is a diagram showing a detailed configuration example of the MF phase adjustment circuit 21 in the configuration of the embodiment shown in FIG. In the figure, the number of TSs to be received is equal to the number of TSs (TS1, TS
2 and three TS8) MF phase adjustment circuits 21-1 to 21-1
Shown as 21-3.

Further, these MF phase adjusting circuits 21-1 to 21-1
21-3 have the same configuration, and a shift circuit 21-0 is provided in common with them. Therefore, the detailed configuration will be described below by taking one MF phase adjusting circuit 21-3 among the MF phase adjusting circuits 21-1 to 21-3 as an example.

The shift register 11 of FIG. 4 and the shift register 11 of FIG. 3 are the same and correspond to the MF bit latch shift register 11 of FIG.

The phase comparison circuit 14 constituting the MF phase adjustment circuit 21-3 has a 3-bit latch circuit 141 for holding the old MF phase and a 3-bit comparator 142 for comparing the new / old phase. The synchronization protection circuit 16 determines backward protection and forward protection based on the comparison result of the 3-bit comparator 142.

The sync protection circuit 16 has a general structure regardless of the present invention. When the sync protection state is declared as a result of the sync protection determination, the latch circuit 141 is provided.
To the new state. As a result, the new / old state is updated.

The output signal of the latch circuit 141 is input to the self-ST MF generating circuit 15. The self-ST MF generation circuit 15 has three AND circuits 151 to 15 to which the 3-bit output of the latch circuit 141 is input.
OR which outputs the OR logic of 3 and the output of those AND circuits
It has a circuit 154.

The other input terminals of the AND circuits 151 to 153 are supplied with the timing signals phase-shifted from each other from the 2-bit shift register 21-0 which shifts in frame units as already described with reference to FIG. . As a result, the shift amount of the reference MF is sequentially selected, and the self-ST MF is selected.
The generating circuit 15 outputs the self-ST MF.

Specifically, the MF of TS18 in FIG.
Is held in the shift register of the third frame (3fr). Since the synchronization has not been established yet, the latch is operating in the updated state, and the state of the shift register 11 is transferred to the latch circuit 141 at the timing of the next reference MF.

If the MF arrives at the same phase the next time, it is similarly held in the shift register of the third frame (3fr). Then, the states will be the same before and after the latch. This is transmitted to the synchronization protection circuit 16, and the backward protection monitoring is started.

In the output of the latch circuit 141, the bit in the third frame has MF, that is, it is in the enabled state, and the other bits are in the disabled state. Therefore, a signal delayed by two frames from the reference MF is the shift register 2
It is selected by 1-0 and output as an MF for 18TS through the AND circuit 153 and the OR circuit 154.

This state is repeated for the number of backward protection stages of the synchronization protection, and when the synchronization is established, the update signal for the latch is stopped, and the MF is continuously output in the same phase as when the synchronization was established. Then, if the phase of the MF of 18TS changes only once in the second frame, the outputs of the comparison circuit 16 do not match.

Although this result is sent to the synchronization protection circuit 16, the latch circuit 141 is not updated because the synchronization establishment state continues due to the forward protection, and the phase of MF is held as it is.

As described above, in the present invention, the criterion M
A signal obtained by delaying F in frame units is used as the shift register 21.
By preparing n (3 in the embodiment) groups by using −0 and using each bit of the latch output from the previous latch circuit 141 as n groups of MF phase selection signals,
The output becomes the synchronization protected MF signal of its own TS.

If the circuits 21 each including a set of this latch, comparison, synchronization protection, and phase selection are provided for the number of TSs to be received, an MF synchronization protection circuit for a plurality of TSs can be realized.

Although the transmission line of 1.544 Mbps is used in the above-mentioned embodiment, the present invention is not limited to this and can be naturally applied to other transmission lines. Further, the cycle of MF is not limited. Although the embodiment shows the case where three TSs are received, it is possible to process a larger number of TSs by increasing the number of stages of the shift register and the number of phase difference measuring circuits. At the same time, even if the MF phase shift amount between TSs is larger, it can be dealt with by expanding the number of stages of shift registers, latches, comparators, and the like.

[0053]

As described above according to the embodiments,
According to the present invention, it is sufficient to prepare only one MF counter having a large circuit scale. In addition, an MF synchronization circuit can be realized with a few sets of flip-flops in units of 2 to 3 bits and a few logic gates. Therefore, the present invention is particularly advantageous when considering an LSI or the like.

Further, since the circuit operates when the MFs of a plurality of TSs are aligned in a close phase, it is possible to prevent the pseudo sync from being entered in an incorrect phase due to sudden noise. Therefore, in the situation where the reception TS is switched from time to time, the time until the establishment of synchronization can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a multi-frame configuration used in an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a multi-frame synchronization circuit of the present invention.

FIG. 3 is a diagram showing a configuration example of a reference MF signal generation circuit.

FIG. 4 is a diagram showing a configuration example of a multi-frame extraction circuit for each slot.

FIG. 5 is a diagram showing a configuration example of a multiframe for explaining the problem of the conventional example.

[Explanation of symbols]

 11 shift register 20 reference MF signal generation circuit 12 all MF arrival detection circuit 13 MF counter 21 MF phase adjustment circuit 14 new / old MF phase comparison circuit 15 own MF generation circuit 16 synchronization protection circuit

Claims (3)

[Claims] 1. A synchronization circuit for detecting and outputting a reference multi-frame synchronization signal from a received multi-frame signal, and a reference multi-circuit provided for the number of timeslots to be subjected to reception processing, each of which is detected by the synchronization circuit. A phase adjustment circuit for detecting a phase difference between the phase of the frame synchronization signal and the received multi-frame synchronization signal, and selectively outputting a synchronization signal obtained by shifting the phase of the reference multi-frame synchronization signal according to the phase difference. A multi-frame synchronization circuit characterized by being constructed. 2. The shift register according to claim 1, comprising at least the same number of sets of shift registers as the number of multiframe phase shifts between the time slots of the received multiframe signal, and the number of stages equal to the number of timeslots to be subjected to reception processing. One synchronization circuit obtains an OR logic of outputs of the same stages of the number of sets of shift registers, obtains an AND logic of the obtained OR logic of the stages, and an output of the logic circuit. A counter for counting a number corresponding to the number of multi-frames of the multi-frame signal, the counter is set to a value equal to the number of sets by the output of the logic circuit, and when the count value becomes 0, A multi-frame synchronization circuit configured to output the reference multi-frame synchronization signal. 3. The shift register according to claim 1, comprising at least the same number of sets of shift registers as the number of multiframe phase shifts between the time slots of the received multiframe signal and the number of stages equal to the number of reception processing target time slots. Each of the phase adjustment circuits determines the state of frame synchronization by comparing in which shift register of the number of sets the multi-frame synchronization signal of one time slot is latched, and determines the frame synchronization status. A multi-frame synchronization circuit configured to output the phase-shifted reference multi-frame synchronization signal.