JPH08274261A - Electrostatic breakdown protective circuit - Google Patents

Abstract

PURPOSE: To improve an integrated circuit in dielectric strength to external static electricity of high-voltage restraining it from increasing in area. CONSTITUTION: An output cell C4 is an ESD protecting object to be enhanced in dielectric strength to an external static electricity of high-voltage. The output cell C4 is connected to a lead frame L4 , and an unused cell C5 is connected to the lead frame L4 with a bonding wire W5 bigger than a bonding wire W4 . A current induced by a high voltage applied to the lead frame L4 from outside is made to concentrate on the bigger bonding wire W5 , and most of the current is made to flow in an ESD protecting circuit of the unused cell C5 . By this setup, the output cell C4 is enhanced in dielectric strength.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame provided in a package provided for an input cell, an output cell or a bidirectional input / output cell of a semi-custom type integrated circuit chip, and a lead frame connected to the lead frame. It relates to the electrostatic breakdown protection circuit that protects the internal circuit from the electrostatic high voltage applied via the bonding wire. Especially, it should try to protect and protect the electrostatic breakdown more effectively while suppressing the increase of the integrated circuit area. The present invention relates to an electrostatic breakdown protection circuit capable of improving the withstand voltage of an input cell, an output cell, or a bidirectional input / output cell.

[0002]

2. Description of the Related Art Static electricity generated by friction of a human body or clothes may be very high voltage. When such a high voltage due to static electricity is applied to the input or output of the integrated circuit or the bidirectional input / output, the internal circuit may be destroyed. In particular, MOSFET (metal ox
In a MOS semiconductor integrated circuit mainly composed of an ide semiconductor field effect transistor), an input impedance and an output impedance tend to be high in both a digital integrated circuit and an analog integrated circuit. At least, a high voltage may be applied.

For this reason, in the integrated circuit, the internal circuit is protected from electrostatic high voltage applied from the outside to the input and output or the bidirectional input / output (hereinafter, ESD (electrostatic).
It is generally called discharge protection).

For example, the conventional ESD protection is to provide a protection diode to the input and output of the integrated circuit to be protected and the bidirectional input and output.
For example, between the integrated circuit input and the power supply VDD or the ground G
It is provided between the integrated circuit output and the power supply VDD or the ground GND. Further, in a MOS semiconductor integrated circuit, a MOS diode is generally used as a protection diode. The MOS diode has a P / N
Diffusion resistance generated at the junction, power supply VDD and ground GN
By using a stray capacitance (electrostatic capacitance) or the like for D, a high voltage pulse applied from the outside is absorbed.

FIG. 4 is a circuit diagram of an example of an ESD protection circuit provided for an input cell of a conventional integrated circuit chip.

In FIG. 4, an input buffer BI for inputting a signal from a bonding pad PI connected to the outside of the integrated circuit chip is built in an input cell together with the bonding pad PI. Via the input buffer BI,
The input signal is output to the internal circuit as the signal SI. For such an input buffer BI, an ESD protection circuit G1 is provided in the input cell. The ES
The D protection circuit G1 includes two protection diodes D1 and D2.
And a protection resistor R1. ESD like this
In the protection circuit G1, the bonding pad PI
When a high voltage pulse is applied to the protection diode D
1 and D2 are turned on, and the voltage applied to the input buffer BI via the protection resistor R1 is reduced.

FIG. 5 is a circuit diagram of an example of an output cell provided with a conventional ESD protection circuit.

In FIG. 5, the ESD built in the output cell together with the bonding pad PO and the output buffer BO.
The protection circuit G3 is shown. The ESD protection circuit G3
Is composed of protection diodes D5 and D6 and a protection resistor R2. Also in the ESD protection circuit G3, when a high voltage pulse is applied to the bonding pad PO, the protection diodes D5 and D
6 is turned on, and the voltage applied to the output buffer BO via the protection resistor R2 is reduced.

FIG. 6 is a circuit diagram of an example of an input cell of a NAND logic gate which is conventionally ESD protected.

In FIG. 6, an ESD protection circuit G4 built into an input cell is formed together with a NAND logic gate composed of P channel MOS transistors TP1 and TP2 and N channel MOS transistors TN1 and TN2, and a bonding pad PI2. Is shown. The E
The SD protection circuit G4 includes protection diodes D7 and D8,
It is constituted by a protection resistor R3. E like this
Also for the SD protection circuit G4, the bonding pad PI
Even if a high voltage pulse is externally applied to 2, the protection diodes D7 and D8 are turned on to reduce the voltage applied to the input of the NAND logic gate through the protection resistor R3. It

The signal SS from the internal circuit is input to the other input of the NAND logic gate. The N
The input cell of the AND logic gate is used, for example, in a part of the oscillation circuit. For example, the bonding pad PI
2 and the signal SS related to the oscillation signal
According to a signal input through the bonding pad PI2, oscillation or its stop can be switched by a logical product of the above and.

FIG. 7 is a circuit diagram of an example of an output cell of a NAND logic gate which has been conventionally ESD-protected.

In FIG. 7, an ESD protection circuit G5 built into an output cell is formed together with a NAND logic gate composed of P channel MOS transistors TP3 and TP4 and N channel MOS transistors TN3 and TN4, and a bonding pad PO2. Is shown. The E
The SD protection circuit G5 includes protection diodes D9 and D10.
And a protection resistor R6. Even in such an ESD protection circuit G5, even if a high voltage pulse is externally applied to the bonding pad PO2, the protection diodes D9 and D10 are turned on, and the NAND is connected via the protection resistor R6. The voltage applied to the input of the logic gate is reduced.

The two inputs of the NAND logic gate respectively have the signal SCK or SEN from the internal circuit.
Has been entered. The output cell of the NAND logic gate is used, for example, as a part of an oscillation circuit. For example, the signal SCK, which is a clock signal generated internally,
According to the signal SEN, the signal SCK is obtained by a logical product of the signal SEN which is an enable signal obtained internally.
It is possible to switch the supply or stop of the clock signal to the external circuit.

[0015]

However, as described above, although the integrated circuit has been conventionally provided with the ESD protection and the corresponding effect is obtained, the withstand voltage against a high voltage applied from the outside is further enhanced. It is preferable.

In particular, since it has been conventionally difficult to improve the withstand voltage, it is necessary to further increase the withstand voltage. For example, in the output cell of the NAND logic gate shown in FIG. 7, compared with the input cell of the simple input buffer BI shown in FIG. 4 and the output cell of the simple output buffer BO shown in FIG. It is difficult to improve the breakdown voltage against the high voltage that is generated.

This is because the output cells of the NAND logic gate use more elements than the input buffer BI, the output buffer BO, etc.
This is because the transistor size becomes smaller, for example. For example, the N-channel MOS transistor TN
If the junction area of 1 to 4 is reduced, the breakdown voltage of the parasitic diode generated for these transistors TP1 to TN4 and TN1 to 4 will decrease.

In the output cell of such a NAND logic gate, the N-channel MOS transistor TN is
3 is equivalently connected with the parasitic diode directly to the bonding pad PO2 side, but the N-channel MO
The parasitic diode of the S transistor TN4 is equivalently connected to the bonding pad PO2 via the N channel MOS transistor TN3. Therefore, the junction area of the parasitic diode formed by the N-channel MOS transistor TN4 is reduced. If the junction area is reduced in this way, the breakdown voltage against a high voltage applied from the outside will be reduced.

In order to improve the breakdown voltage against a high voltage applied from the outside, for example, the P channel M is used.
It is also conceivable to increase the transistor sizes of the OS transistor TP1 and the N-channel MOS transistor TN1. However, it goes without saying that, if the transistor size is increased in this way, inconvenience may normally occur in the integrated circuit layout.

The present invention has been made to solve the above-mentioned conventional problems, and suppresses an increase in integrated circuit area,
An object of the present invention is to provide an ESD protection circuit (electrostatic breakdown protection circuit) capable of more effectively performing ESD protection and improving the withstand voltage of an input cell, an output cell or a bidirectional input / output cell to be protected. To do.

[0021]

SUMMARY OF THE INVENTION The present invention provides a lead frame provided for a package, which is provided for an input cell, an output cell or a bidirectional input / output cell of a semi-custom type integrated circuit chip, and the lead frame. An unused cell that is adjacent to the cell subject to electrostatic breakdown protection and is not used for signal input / output in the electrostatic breakdown protection circuit that protects the internal circuit from the electrostatic high voltage applied via the bonding wire connected to An electrostatic breakdown protection circuit inside, and a low-impedance bonding wire thicker than the bonding wire for connecting the electrostatic breakdown protection circuit to the lead frame to which the electrostatic breakdown protection target cell is connected by a bonding wire. The provision has achieved the above-mentioned problems.

In the electrostatic breakdown protection circuit, the low-impedance bonding wire is equivalently thicker than the bonding wire because a plurality of low-impedance bonding wires having the same thickness as the bonding wire are used in parallel. In addition to achieving the above problems, the thickness of the low-impedance bonding wire is made the same as other bonding wires to simplify the manufacturing process, reduce the manufacturing cost, and so on. By reducing the impedance to the high voltage pulse containing many high frequency components due to the applied pulse property, the current of the high voltage pulse flowing to the electrostatic breakdown protection circuit side in the unused cell is increased, resulting in The breakdown voltage of the cell to be protected against electric breakdown is further improved. here,
Even if the cross-sectional area is the same, the conductor surface area is increased and the so-called skin effect against high frequencies is reduced when using a plurality of thin bonding wires, as compared to a single thick bonding wire. Can be suppressed.

[0023]

In the present invention, the TAT (turn
It has been widely used in recent years due to its short around time,
Attention is paid to a semi-custom type integrated circuit prepared in advance by standardizing at least a part of the design process or the manufacturing process. The semi-custom type integrated circuit includes a standard cell type integrated circuit and a gate array type integrated circuit. The standard cell type integrated circuit is
According to a design method in which registered cells are arranged according to a circuit to be incorporated in an integrated circuit and interconnected. On the other hand, in the gate array type integrated circuit, a group of cells arranged in a matrix that is processed before the wiring process is shared, and the subsequent wiring process is designed or built according to the circuit incorporated in the integrated circuit. It is a thing.

According to a research conducted by the inventor, such a semi-custom type integrated circuit has an input cell or an output cell arranged on the outer periphery of the integrated circuit chip, or a bidirectional input / output cell. It can be seen that there are many unused ones. For example, in one series of semi-custom type integrated circuit chips, about 20 to 40% of such cells are unused per integrated circuit chip.

The ratio of such unused cells varies on a case-by-case basis. For example, as a general trend, as the die size (chip size) increases, the number of input cells, output cells, or bidirectional input / output cells that can be arranged increases, so the number of unused cells also increases. is there.

In the present invention, attention is paid to such an unused cell, and the electrostatic breakdown protection circuit in the unused cell is utilized for ESD protection of another adjacent cell that is actually used. ing. As described above, in the present invention, since the ESD protection is performed by using the cell which has not been used conventionally, the ESD protection can be more effectively performed while suppressing the increase of the integrated circuit area.

Further, according to the present invention, the ESD
The inventors have also found a configuration in which an ESD protection circuit in an unused cell adjacent to a cell to be protected is used to more effectively improve the breakdown voltage of an actually used cell against a high voltage applied from the outside.

In the present invention, compared with the thickness of the bonding wire used for connecting the cell which is the object of ESD protection and the lead frame used for inputting and outputting the signal which may intrude a high voltage, the lead frame and The thickness of the bonding wire connecting the used cell is made thicker.
Therefore, the impedance from the lead frame to the unused cell is lower than the impedance from the lead frame to the ESD protection target cell. Therefore, a large amount of current due to a high voltage applied to the lead frame from the outside flows into the unused cell side, so that the withstand voltage of the ESD protection target cell can be further increased.

Here, the inductance L of the bonding wire can be obtained by the following equation.

L = (μ / (2 × π)) × ln (4 × h / d) (1)

Here, μ is the magnetic permeability, h is the distance from the constant potential object such as the ground of the bonding wire or the power source, d is the radius of the bonding wire, and ln is the natural logarithmic function. A high voltage applied from the outside such as static electricity is generally a pulsed current for an extremely short time. Such an abrupt rising current has a problem in the impedance component particularly in the impedance, and the smaller the inductance, the easier the current flows. Therefore, by making the inductance of the bonding wire on the unused cell side smaller than that on the side of the ESD protection target cell, the current flowing into the ESD protection target cell side is suppressed and the breakdown voltage is effectively improved. can do.

[0032]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a partial plan view of a first embodiment of an integrated circuit to which the present invention is applied.

In FIG. 1, an output cell C4 which is an ESD protection target, an unused output cell C5, and an integrated circuit package to which these are connected, which is a part to which the present invention is particularly applied in this embodiment. Lead frame L provided on
4 and a plan view of the periphery thereof are shown. The bonding pads P1 to C1 of the input cells C1 to C3, C6 and C7
P3, P6 and P7 are respectively connected by bonding wires W1 to W3, W6 and W7 to lead frames L1 to L3, L6 and L7 provided in the integrated circuit package for inputting signals from outside the integrated circuit. Has been done.

For the output cell C4, the lead wire L4 is formed by the bonding wire W4 having the same thickness as the other bonding wires W1 to W3, W6 and W7.
It is connected to the. Also, the bonding pad P5 of the unused output cell C5 is connected to the lead frame L4 to which the bonding pad P4 is also connected by the bonding wire W5 thicker than the other bonding wires W1 to W4 and W6 to W7. Connected to.

FIG. 2 is an equivalent circuit diagram of a portion to which the present invention of the first embodiment is applied.

In FIG. 2, an equivalent circuit diagram relating to the output cells C4 and C5 to which the present invention is applied is shown.

First, the output cell C4 related to the bonding pad P4 has been described with reference to FIG. 7, and the ESD protection circuit G5 and the P channel MO are provided.
S transistors TP3 and TP4 and the N channel MO
NAND composed of S transistors TN3 and TN4
It is composed of a logic gate G1. The bonding pad P4 is connected to the lead frame L4 by the bonding wire W4 having an impedance R4. The output cell C4 outputs the NAND logical operation result from the lead frame L4.

On the other hand, the output cell C5 related to the bonding pad P5 is the output cell described above with reference to FIG. 5, and includes the ESD protection circuit G3 and the output buffer BO. The bonding pad P5 of the output cell C5 is connected to the lead frame L4 by the bonding wire W5 having an impedance R5. The output cell C5 is the output cell C.
4 is an unused cell that is used for the ESD protection of No. 4 and is not used for outputting the signal of the internal circuit.

Here, the output cell C4 of the NAND logic gate has the same size as the output cell C5 of the output buffer. However, the output cell C4 has a lower withstand voltage against a high voltage applied from the outside than a general output cell using another output buffer, for example, the output cell C5. For this reason,
In this embodiment, the output cell C5 is connected to the lead frame L4 for ESD protection in parallel with the output cell C4 having such a low breakdown voltage.

Further, here, the thickness of the bonding wire W4 of the output cell C4 which is the object of ESD protection is the same as the bonding wires W1 to W1 as shown in FIG.
The same as W3, W6, W7, etc. On the other hand, ES
The output cell C5 used for D protection is shown in FIG.
Also, as shown in the figure, the thickness of the bonding wire W5 is made thicker than the others, so that the impedance R
5 is made small, and in particular, the inductance component of the impedance R5 is made small. Therefore, when a high voltage pulse is applied to the lead frame L4 from the outside, the resulting current mainly flows to the output cell C5 side for ESD protection. As a result, the breakdown voltage of the output cell C4 that is the object of ESD protection is further improved.

As described above, according to the first embodiment, the breakdown voltage tends to be lower than that of an output cell using a general output buffer, and the current flows into the output cell C4 of the NAND logic gate. The current generated when a high voltage pulse is applied from the outside can be suppressed. This makes it possible to improve the breakdown voltage of the output cell C4 to the same level as or higher than that of the output cell using the output buffer shown in FIG. Further, when the withstand voltage of the output cell C4 is thus improved, the output cell C5 used is originally an unused cell, so that problems such as a reduction in the integrated circuit area and a reduction in the degree of integration are not caused. Absent.

FIG. 3 is a plan view of a main portion of a second embodiment of the electrostatic breakdown protection circuit to which the present invention is applied.

In the second embodiment shown in FIG. 3, as apparent from the comparison with FIG. 1, the bonding wires W5 of the first embodiment are two bonding wires W5a and two bonding wires W5a in total. It is replaced by W5b. These bonding wires W5a and W5b are
The bonding wires W1 to W4, W6, and W7 have the same thickness. The total cross-sectional area of the bonding wires W5a and W5b is the same as the cross-sectional area of the bonding wire W5.

In the second embodiment as described above, the combined inductance of the bonding wires W5a and W5b is equal to or less than that of the bonding wire W5. In particular, when a large amount of high-frequency component current flows, such as when a high-voltage pulse with a sudden current change is applied from the outside, the current concentrates on the conductor surface due to the so-called skin effect, so these bonding wires W5a and W5
The composite impedance of b is the bonding wire W
It is smaller than 5.

Therefore, according to the second embodiment, more current due to a high voltage applied from the outside to the lead frame L4 is made to flow into the output cell C5 side used for ESD protection. Therefore, the output cell C4 can be effectively protected. Further, in the second embodiment, since the bonding wires W5a and W5b having the same thickness as the other bonding wires W1 to W4 are used, the bonding process can be simplified.

From the viewpoint of flowing more current due to the high voltage externally applied to the lead frame L4 to the output cell C5 side used for ESD protection, the thickness of the bonding wire of the output cell C5 is larger. Is relatively thicker than that of the output cell C4. Therefore, it is conceivable that the bonding wire used for connecting the output cell C5 has a normal thickness and the bonding wire on the output cell C4 side to be protected is thinner than usual. However, since the bonding wire of the output cell C4 is also a signal line, if it is made thin, performance deterioration such as a decrease in signal transmission speed will occur.

In the first and second embodiments described above, one unused cell is used for ESD protection for one output cell that is the object of ESD protection. However, the present invention is not limited to this, and for example, when there are a plurality of unused cells and there is a bonding space in the lead frame to which the cells to be protected are connected, one ESD is used. A plurality of cells for protection may be connected to the cell to be protected.
In addition, both the first and second embodiments described above are ES
Although the D protection target cell is an output cell, the present invention is not limited to this, and for example, an input cell or a bidirectional input / output cell can be similarly subject to ESD protection.

In both the first embodiment and the second embodiment, the bonding of the plurality of bonding wires to the lead frame L4 is made at different positions in plan view. However, if technically possible, as a double bonding, a plurality of bonding wires may be stacked and bonded so as to be sequentially stacked.

In the first and second embodiments, the present invention is applied to the output cell of the NAND logic gate shown in FIG. 7, as described above with reference to FIG. . However, the present invention is not limited to this. For example, the first embodiment and the second embodiment can be applied to the input cell of FIG. 4, the output cell of FIG. 5, and the input cell of the NAND logic gate of FIG.

[0051]

As described above, according to the present invention,
An excellent effect that electrostatic discharge protection can be more effectively performed while suppressing an increase in integrated circuit area and the withstand voltage of an input cell, an output cell or a bidirectional input / output cell to be protected can be improved. be able to.

[Brief description of drawings]

FIG. 1 is a partial plan view of a first embodiment of an integrated circuit to which the present invention is applied.

FIG. 2 is an equivalent circuit diagram of the portion of the first embodiment to which the present invention is applied.

FIG. 3 is a partial plan view of a second embodiment of an integrated circuit to which the present invention is applied.

FIG. 4 is a circuit diagram of an input cell including a conventional electrostatic breakdown protection circuit.

FIG. 5 is a circuit diagram of an output cell equipped with a conventional electrostatic breakdown protection circuit.

FIG. 6 is a circuit diagram of an input cell of a NAND logic gate having a conventional electrostatic breakdown protection circuit.

FIG. 7 is a circuit diagram of an output cell of a NAND logic gate having a conventional electrostatic breakdown protection circuit.

[Explanation of symbols]

C1-C7 ... Cell P1-P7, PI, PI2, PO ... Bonding pad W1-W7, W5a, W5b ... Bonding wire L1-L7 ... Lead frame G1, G3-G5 ... ESD protection circuit D1, D2, D5-D10 ... Protection diodes R1 to R6 ... Protection resistance BI ... Input buffer BO ... Output buffer TP1 to TP4 ... P channel MOS transistors TN1 to TN4 ... N channel MOS transistors S4, SI, SI2, SO, SS, SCK, SEN ... Signal VDD ... Power supply G ... Grand

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 23/60

Claims (2)

[Claims] 1. A lead frame provided for an input cell, an output cell, or a bidirectional input / output cell of a semi-custom type integrated circuit chip, which is provided in a package, and a bonding wire which is connected to the lead frame. In the electrostatic breakdown protection circuit that protects the internal circuit from the high electrostatic voltage that is generated, the electrostatic breakdown protection circuit in an unused cell that is not used for signal input / output adjacent to the cell subject to electrostatic breakdown protection A static low impedance bonding wire that is thicker than the bonding wire and that connects the electrostatic breakdown protection circuit to the lead frame to which the electrostatic breakdown protection target cell is connected by a bonding wire. Electric breakdown protection circuit. 2. The low-impedance bonding wire according to claim 1, which is equivalently thicker than the bonding wire because a plurality of wires having the same thickness as the bonding wire are used in parallel. An electrostatic breakdown protection circuit characterized by the following.