JPH08265798A - Time base corrector circuit - Google Patents

Abstract

PURPOSE: To provide a time base corrector circuit capable of simplifying a circuit and eliminating SN ratio degradation due to A/D and D/A conversion. CONSTITUTION: In a horizontal synchronizing lock clock generation circuit 13 using the digital technique of a numerically controlled oscillator(NCO), first clocks synchronized with the horizontal synchronizing signals of input video signals for quickly following up even the jitters or the like of VTR reproducing signals for instance are generated. After the A/D conversion is performed by using the first clocks, A/D converted digital video signals are inputted to a Y/C separation/color demodulation circuit 16, a color demodulation process is performed on the basis of the first clocks in the circuit 16 and thereafter, write in a memory 21 is performed by using the first clocks. Then, when the readout is performed by using the highly stable second clocks of a fixed frequency out of a fixed frequency oscillator 22 and the D/A conversion is performed, by the technique of the NCO, clocks for color demodulation are easily generated on the first clocks for the sampling of the input video signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time base collector circuit, and more particularly to a numerically controlled oscillator (hereinafter referred to as NCO).
The present invention relates to a time base collector circuit using digital technology of NCO (Numerical Control Oscillator).

[0002]

2. Description of the Related Art Conventionally, a time base collector circuit has been developed to suppress a time base error (hereinafter referred to as jitter) of a video tape recorder (hereinafter referred to as VTR). In a VTR, a magnetic tape is sent by rotation of a capstan shaft, a recording / reproducing head is mounted on a rotating drum, and a motor is included when recording a video signal on the tape or reproducing a signal on the tape. I need a mechanical system.

Therefore, an error occurs between the tape speed during recording, the rotational speed of the recording head, and the speed during reproduction. These mechanical errors appear as jitter in the reproduced signal, and the time axis of the video signal changes long or short. The time base collector circuit corrects such jitter and returns it to the standard phase state, for example, V
When the TR reproduction signal and the video camera signal are switched and used, the two signals can be phase-synchronized.

FIG. 3 is a block diagram of a conventional time base collector circuit and video processing circuit.

In FIG. 3, a video signal having horizontal jitter from a VTR or the like is input to an input terminal 31,
This video signal is supplied to the A / D converter 32 and the horizontal sync lock clock generation circuit 33. The horizontal synchronization lock clock generation circuit 33 includes a PLL (Phase Locked Loop) circuit composed of a phase comparator, a low-pass filter, and a voltage-controlled oscillator, and the frequency of the voltage-controlled oscillator accurately reflects the frequency of the input video signal. By synchronizing with the average frequency of the horizontal synchronizing signal (when locked), a clock synchronized with the horizontal synchronizing signal of the input video signal is generated. The A / D converter 32 samples the input video signal with this generated clock and outputs it as a digital signal to the memory 34. In the memory 34, A / D
The digital signal is stored at the same clock timing as that of the converter 32, and the stored value is sequentially read out by using a clock having a fixed cycle from a fixed frequency oscillator 35 which is different from the digital signal and supplied to the D / A converter 36. To do. D / A converter 3
In 6, the read digital signal is converted into an analog signal using the same clock from the fixed frequency oscillator 35. In this way, by writing to the memory 34 with a clock synchronized with the horizontal synchronizing signal and reading with a clock of a constant frequency, a jitter-corrected video signal is obtained,
It is supplied to the video processing circuit 40 in the next stage.

In the video processing circuit 40, the jitter-corrected video signal from the time base collector circuit 30 is supplied to the A / D converter 41 in order to perform digital processing for color demodulation, and a burst lock clock is generated. Circuit 42
After the A / D conversion is performed with the clock from, the signal is input to the Y / C separation / color demodulation circuit 43. The burst lock clock generation circuit 42 includes a PLL circuit including a phase comparator, a low-pass filter and a voltage controlled oscillator, and the average frequency of the burst signal of the video signal whose jitter is corrected by the frequency of the voltage controlled oscillator (when locked). ) To generate a clock synchronized with the burst signal. A
The / D converter 41 converts the video signal into a digital signal based on the generated clock and outputs the digital signal. The digital video signal is Y / C separated by using a clock synchronized with the burst signal from the burst clock generation circuit 42.
After Y / C separation and color demodulation processing by the color demodulation circuit 43,
The D / A converter 44 uses the same clock as the A / D converter 41 to perform conversion into an analog signal. An analog luminance signal Y and a color difference signal RY from the D / A converter 44,
BY is output from the output terminals 45, 46, 47 and supplied to a display device (not shown).

By the way, in the above-mentioned conventional circuit, in order to perform both the time axis correction operation and the color demodulation operation, there are two clocks, a clock synchronized with the horizontal synchronizing signal and a clock synchronized with the burst signal. Was required, and the circuit was complicated. Even if an attempt is made to perform the above two operations using only the clock synchronized with the horizontal synchronization signal in order to solve this, the color demodulation processing cannot be performed because the correspondence between the horizontal synchronization clock and the color demodulation clock cannot be accurately grasped. Was impossible. Therefore, in the conventional circuit, three clock generating means and two sets of A / D and D / A converters are required, which complicates the circuit configuration, while repeating A / D and D / A conversions. As a result, quantization noise is generated due to sampling, resulting in a decrease in SN ratio.

[0008]

As described above, different processing clocks are required in the conventional processing circuit that performs both the time base correction operation and the color demodulation operation, which complicates the circuit and causes A / D and D / The SN ratio was deteriorated due to repeated A conversion.

In view of the above problems, it is an object of the present invention to provide a time base collector circuit which simplifies the circuit and eliminates the SN ratio deterioration due to A / D and D / A conversion. is there.

[0010]

A time base collector circuit according to the present invention includes an A / D converter for converting an input video signal into a digital signal, and a PLL circuit using NCO digital technology. The A / D-converted video signal from the A / D converter is input, and the first clock and the horizontal / vertical reference signal for A / D conversion synchronized with the horizontal synchronizing signal of the input video signal are generated. A first clock generation circuit and a first clock generation circuit from the first clock generation circuit.
A Y / C separation / color demodulation circuit for digitally Y / C separating and color demodulating the video signal from the A / D converter by using the clock, and outputting a digital luminance signal and color difference signal; A second clock generation circuit for generating a second clock having a high frequency stability different from the first clock with reference to horizontal / vertical reference signals;
The luminance signal and the color difference signal from the color demodulation circuit are input, writing is performed using the first clock and the horizontal / vertical reference signal synchronized with the horizontal synchronization signal from the first clock generation circuit, and the second signal is written. A memory for outputting a time-corrected digital luminance signal and color difference signal by performing reading using the second clock having high frequency stability from the clock generation circuit, and a luminance signal and color difference read from this memory. And a D / A converter for converting the signal into an analog signal by using the second clock.

According to a second aspect of the invention, in the time base collector circuit according to the first aspect of the invention, the second base is provided.
The clock generation circuit of 1 is composed of a fixed frequency oscillator for generating a clock having high frequency stability different from the first clock with reference to the horizontal / vertical reference signals from the first clock generation circuit. Is characterized by.

According to a third aspect of the present invention, in the time base collector circuit according to the first aspect of the invention, the second base is provided.
Of the burst signal, which has sufficiently high frequency stability with respect to horizontal synchronization, based on a burst signal obtained from an input video signal with reference to the horizontal / vertical reference signals from the first clock generation circuit. It is characterized in that it is composed of a clock generation circuit for generating a clock synchronized with.

According to a fourth aspect of the present invention, in the time base collector circuit according to the first aspect of the present invention, the second base is provided.
Of the vertical clock signal having a sufficiently high frequency stability with respect to horizontal synchronization, based on a vertical synchronizing signal obtained from an input video signal with reference to the horizontal / vertical reference signals from the first clock generating circuit. It is characterized by being configured by a clock generation circuit for generating a clock synchronized with a synchronization signal.

[0014]

According to the present invention, in the first clock generation circuit using the NCO digital technology, the first clock generation circuit which synchronizes with the horizontal synchronizing signal of the input video signal and quickly follows the jitter of the VTR reproduction signal, for example. A clock is generated, A / D conversion is performed using the first clock, and the A / D converted digital video signal is input to the Y / C separation / color demodulation circuit, where the first clock is used. After performing the color demodulation processing based on the above, the first clock is used to write into the memory, the second clock generating circuit reads out using the second clock of a constant frequency with high stability, and D / A conversion is performed. I decided to do it. Since the first clock generation circuit has the circuit configuration using the NCO, it is possible to easily generate the color demodulation clock based on the sampling clock of the input video signal, and to eliminate one clock generation circuit. In addition, one set of A / D and D / A converters can be deleted, the circuit configuration can be simplified, and A / D and D / A
It is possible to reduce the SN ratio deterioration due to A conversion.

[0015]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a time base collector circuit according to an embodiment of the present invention.

The time base collector circuit of the embodiment shown in FIG. 1 converts an input video signal containing jitter into a digital signal, and based on the clock, the digital video signal is synchronized with a horizontal synchronizing signal of the input video signal. A video processing unit 10 that digitally performs Y / C separation and color demodulation, and a digital luminance signal Y and digital color difference signals RY and BY from the video processing unit 10 are used as horizontal synchronizing signals of the input video signal. Write to memory using synchronized clocks,
A time base collector operation unit 20 is used to read out using a clock having a high degree of stability other than the clock and take out a stable synchronized video signal as an output.

The video processing unit 10 includes an A / D converter 12 for converting an input video signal containing jitter from the input terminal 11 into a digital signal, and a PLL circuit using an NCO digital technique, which will be described later. Input the A / D converted video signal from the A / D converter 1 and generate a clock (a fixed number of clocks within one horizontal period) and a horizontal / vertical reference signal synchronized with the horizontal synchronizing signal of the input video signal. Using the horizontal synchronization lock clock generating circuit 13 and the horizontal synchronization clock, the video signal from the A / D converter 12 is digitally Y / C separated and color demodulated to obtain a digital luminance signal Y and a color difference. It is composed of a Y / C separation / color demodulation circuit 16 which outputs signals RY and BY.

The time base collector operating unit 20 is composed of, for example, a crystal oscillator, and refers to the horizontal / vertical reference signals from the video processing unit 10 and has a frequency stability different from that of the clock from the video processing unit 10. A fixed frequency oscillator 22 for generating a high clock, a luminance signal Y and color difference signals RY and BY from the video processing unit 10 are input, and a clock synchronized with a horizontal synchronizing signal from the video processing unit 10 and Writing is performed by using horizontal / vertical reference signals, and reading is performed by using a clock having a high stability and a constant frequency from the fixed frequency oscillator 22, and time-axis corrected digital luminance signal Y and color difference signal RY , BY for outputting the luminance signal Y and the color difference signals RY, BY read from the memory 21 into analog signals, and output terminals D output from 24, 25 and 26
And / A converter 23.

In the circuit configured as described above, a video signal having jitter is input from the input terminal 11,
This video signal is converted into a digital video signal by the A / D converter 12, and the horizontal sync lock clock generation circuit 1
3 and the Y / C separation / color demodulation circuit 16. The horizontal sync lock clock generation circuit 13 is composed of a phase comparator, a low pass filter and a voltage controlled oscillator.
The LL (Phase Locked Loop) circuit is provided, and the frequency of the voltage-controlled oscillator is made to exactly match the average frequency (when locked) of the horizontal synchronizing signal of the input video signal, so that the horizontal synchronizing signal of the input video signal is And a horizontal / vertical reference signal 15 are generated. Here, the horizontal synchronization lock clock generation circuit 13
853 of Toshiba Review 1993 Vol.48 No.11 (November issue)
As shown in the page, it utilizes the NCO digital technology, and has a feature that the oscillation frequency can be uniquely known from the oscillation control signal. That is, the NCO
It is possible to stably digitally control the oscillation frequency by using a cumulative adder and an overflow processing circuit. As a result, even a clock synchronized with a horizontal synchronizing signal having jitter can be accurately represented by a digital value, so that the sampling frequency of the input video signal can be accurately grasped as an absolute value (digitally). .

The digital video signal from the A / D converter 12 is subjected to color demodulation by the Y / C separation / color demodulation circuit 16 using a clock having a cycle obtained based on the clock from the horizontal sync lock clock generation circuit 13. , Luminance signal Y and color difference signals RY and BY. The luminance signal Y and the color difference signals R-Y and B-Y after Y / C separation and color demodulation by the Y / C separation / color demodulation circuit 16 using digital technology are the horizontal signals from the horizontal synchronization lock clock generation circuit. It is written in the memory 21 of the time base collector operation unit 20 with a sampling number of clocks obtained by dividing the synchronization period by a constant value.
It should be noted that the sampling number of a video signal having jitter such as VTR is a constant sampling number in one field cycle, for example. Therefore, a fixed frequency oscillator 22 having a frequency obtained by multiplying the field frequency by the sampling number of one field period is provided, the memory 21 is read by the oscillation clock, and the D / A converter 23 converts the analog signal into an analog signal using the same clock. The converted luminance signal Y from the output terminals 24, 25 and 26 is subjected to the jitter correction,
The color difference signals RY and BY are output and supplied to a display device (not shown).

Writing to the memory 21 is performed with a clock synchronized with the horizontal synchronizing signal of the horizontal synchronizing lock clock generating circuit 13, and reading from the memory 21 is performed using a clock with a high frequency stability from the fixed frequency oscillator 22. Thus, the time axis correction operation is performed and the jitter correction is performed.

The fixed frequency oscillator 22 may be, for example, a crystal oscillator, but the clock generated due to element variations, temperature drift, etc. may have frequency variations, but the horizontal synchronizing signal supplied to the display device is a D / A converter. 23, the luminance signal Y and the color difference signal R- which have been D / A converted
If it is processed in synchronization with each of the Y and BY signals, there is practically no problem.

Regarding the timing of reading from the writing in the memory 21, the memory 21
Then, by managing the time delay amount of the video signal including the jitter from the input terminal 11 to be the minimum value by the horizontal / vertical reference signal, the read timing from the memory 21 is the maximum of the VTR skew. The delay amount corresponding to the value may be used. However, this is the case of adapting to a wide range of VTRs, and it is also possible to determine the applicable range, that is, the upper limit of the allowable VTR skew, and reduce the delay amount of the memory 21.

FIG. 2 is a block diagram showing a time base collector circuit according to another embodiment of the present invention. The same components as those in FIG. 1 will be described with the same reference numerals.

In FIG. 1, the difference from FIG. 2 lies in the generation means of the clock used for reading the memory 21 and sampling the D / A converter 23.

The time base collector circuit of the embodiment shown in FIG. 2 converts an input video signal containing jitter into a digital signal, and based on the clock, the digital video signal is synchronized with the horizontal synchronizing signal of the input video signal. Digital Y / C separation and color demodulation are performed to output digital luminance signal Y and color difference signals R-Y and B-Y, while horizontal / vertical reference signals obtained from the input video signal and extracted at the time of the color demodulation. Image processing unit 10A capable of generating a clock with high frequency stability synchronized with the burst signal
Then, the digital luminance signal Y and the color difference signals RY and BY from the video processing unit 10A are written in the memory 21 using a clock synchronized with the horizontal synchronizing signal of the input video signal, and the horizontal synchronizing clock Is a time for reading out by using a clock synchronized with a burst signal having a sufficiently high frequency stability with respect to another horizontal synchronization and taking out an analog luminance signal Y and digital color difference signals RY and BY having a stable cycle as outputs. It is composed of a base collector operating unit 20A.

The video processing section 10A includes an A / D converter 12 for converting an input video signal containing jitter from the input terminal 11 into a digital signal, and a PLL circuit using an NCO digital technique described later, Input the A / D converted video signal from the A / D converter 12, and generate a clock (a fixed number of clocks in one horizontal period) and a horizontal / vertical reference signal synchronized with the horizontal synchronizing signal of the input video signal. Using the horizontal synchronization lock clock generating circuit 13 and the horizontal synchronization clock, the video signal from the A / D converter 12 is digitally Y / C separated and color demodulated to obtain a digital luminance signal Y and a color difference. Y / C separation / color demodulation circuit 16 for outputting signals RY and BY, and a burst signal reproduced at the time of color demodulation with reference to the horizontal / vertical reference signal 15. , And a burst lock clock generator circuit 18 which generates a clock synchronized with the high burst signal sufficiently frequency stability with respect to the horizontal sync.

The time base collector operating section 20A receives the luminance signal Y and the color difference signals RY and BY from the Y / C separation / color demodulation circuit 16 and inputs them from the horizontal sync lock clock generation circuit 13. Writing is performed using a clock synchronized with the horizontal synchronizing signal, and reading is performed using a clock having a high frequency stability from the burst lock clock generating circuit 18, and a jitter-corrected digital luminance signal Y and color difference signal R- A memory 21 that outputs Y and BY, and a luminance signal Y read from this memory 21.
And color difference signals RY and BY are converted into analog signals,
The D / A converter 23 outputs from the output terminals 24, 25 and 26.

In the above-described embodiment of FIG. 1, the reading of the memory 21 and the D / A conversion of the D / A converter 23 are performed by using the clock from the fixed frequency oscillator 22 which is independent of the input video signal. On the other hand, in the embodiment shown in FIG. 2, the memory 21 is read and the D / A is read using the clock synchronized with the burst signal having a frequency stability sufficiently high with respect to horizontal synchronization.
The converter 23 performs D / A conversion. If NCO digital technology is used for the burst lock clock generation circuit 18, digital data synchronized with the burst signal (that is, color subcarrier) can be accurately expressed, and the color demodulation in the Y / C separation / color demodulation circuit 16 can be performed. By the way, since the color subcarrier locked to the burst signal is reproduced, the target clock can be generated only by converting the color subcarrier to the required frequency using the input, and then D / A converting and binarizing it. In other words, it can be realized simply by adding a simple digital circuit and analog circuit.

In this way, like the embodiment of FIG.
Writing to the memory 21 is performed using a clock that is synchronized with the horizontal synchronization signal from the horizontal synchronization lock clock generation circuit 13, and is read from the memory 21 using a clock that is synchronized with the burst signal from the burst lock clock generation circuit 18. By doing so, the time axis correction operation is performed,
Jitter correction is performed.

In the embodiments described above, the fixed oscillator 22 for generating a clock of a constant frequency or the burst lock clock generator 18 for generating a clock synchronized with a burst signal is used as a means for generating a read clock of the memory 21. However, in the present invention, instead of this, a configuration may be used in which a clock generation circuit that generates a clock synchronized with the vertical synchronization signal is used, and this also achieves a performance substantially equivalent to that in FIG. This is because the vertical synchronizing signal has a sufficiently low frequency with respect to horizontal synchronizing and is relatively stable in frequency even if horizontal jitter occurs.

[0032]

As described above, according to the present invention, the NC
Since the color demodulation is performed based on the sampling clock of the input video signal using the O digital technology, one clock generation circuit can be deleted, while one set of A /
The D and D / A converters can be deleted, and the circuit configuration can be simplified. Further, since the A / D and D / A converters are reduced, it is possible to reduce the SN ratio deterioration due to the A / D and D / A conversions.

[Brief description of drawings]

FIG. 1 is a block diagram showing a time base collector circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a time base collector circuit according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional time base collector circuit.

[Explanation of symbols]

 10, 10A ... Video processing unit 12 ... A / D converter 13 ... Horizontal synchronization lock clock generation circuit 16 ... Y / C separation / color demodulation circuit 18 ... Burst clock generation circuit 20, 20A ... Time base collector circuit 21 ... Memory 22 … Fixed frequency oscillator 23… D / A converter

Claims (4)

[Claims] 1. An A / D converter for converting an input video signal into a digital signal, and a PLL circuit using an NCO digital technique, wherein the A / D converted video signal from the A / D converter is converted into a digital signal. The A / D input and synchronized with the horizontal synchronizing signal of the input video signal
A first clock generating circuit for generating a first clock for conversion and a horizontal / vertical reference signal, and an image from the A / D converter using the first clock from the first clock generating circuit. A Y / C separation / color demodulation circuit for digitally Y / C separating and color demodulating a signal and outputting a digital luminance signal and a color difference signal; and the first clock with reference to the horizontal / vertical reference signals. A second clock generating circuit for generating a second clock having another high frequency stability; and a luminance signal and a color difference signal from the Y / C separating / color demodulating circuit, and the first clock generating circuit. Writing is performed using the first clock and horizontal / vertical reference signals synchronized with the horizontal synchronizing signal from, and reading is performed using the second clock having high frequency stability from the second clock generation circuit, A memory for outputting the digital luminance signal and the color difference signals between axis correction, D / A converting the luminance signal and color difference signals read out from the memory into an analog signal using the second clock
A time base collector circuit comprising a converter. 2. The second clock generation circuit is the first clock generation circuit.
2. A fixed frequency oscillator for generating a clock having a high frequency stability different from the first clock by referring to horizontal / vertical reference signals from the clock generating circuit in FIG. Time base collector circuit. 3. The second clock generation circuit comprises:
Clock generation for generating a clock synchronized with the burst signal, which has sufficiently high frequency stability for horizontal synchronization, based on the burst signal obtained from the input video signal by referring to the horizontal / vertical reference signals from the clock generation circuit The time base collector circuit according to claim 1, wherein the time base collector circuit is formed of a circuit. 4. The second clock generation circuit comprises the first clock generation circuit.
Based on the vertical synchronizing signal obtained from the input video signal by referring to the horizontal / vertical reference signals from the clock generating circuit, the clock which is sufficiently high in frequency stability with respect to the horizontal synchronizing and is synchronized with the vertical synchronizing signal The time base collector circuit according to claim 1, wherein the time base collector circuit comprises a clock generation circuit.