JPH08153826A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To provide a high connection reliable LSI package in the case of packaging on a printed-wiring board at low heat resistance fit for multiple pins, high density packaging at low cost. CONSTITUTION: Within the semiconductor integrated circuit device as an LSI package, a TAB tape 6 formed of outer electrode pads 9 comprising a wiring pattern and a part of lead wiring 8 is arranged so that the outer electrodes parts 9 may be positioned on the rear surface side of a substrate 1 while the periphery of the TAB tape 6 may be bent on the main surface side of the substrate 1 so as to electrically connect a semiconductor chip 2 mounted on the main surface of the substrate 1 to one end of the lead wiring 8 provided on the main surface side of the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having an LSI package having a BGA (Ball Grid Array) structure.

[0002]

2. Description of the Related Art An LSI package having a BGA (ball grid array) structure has been attracting attention as a mounting technique for a semiconductor chip having many input / output terminals such as a gate array and a microcomputer. In this LSI package, solder bumps are connected to electrodes of a package substrate on which a semiconductor chip is mounted, and the package substrate is mounted on a printed wiring board via the solder bumps.

The BGA structure LSI package is described in detail, for example, in "Nikkei Electronics, February 28, 1994 (no. 602)" issued by Nikkei BP.

On page 115 (FIG. 3) of this document, a plastic BGA using a resin substrate with double-sided wiring is described. In this plastic BGA, a semiconductor chip mounted on the main surface of a double-sided wiring board and wires on the surface of the board are electrically connected by a wire bonding method, and the wires on the surface of the board are provided on the periphery of the board. It is connected to the wiring on the back surface through the provided through hole. Further, the semiconductor chip is sealed with a mold resin.

The plastic BGA is mounted on the printed wiring board through solder bumps connected to the wiring on the back surface of the board. In addition, this plastic BGA is provided with a through hole for heat dissipation on the wiring substrate immediately below the semiconductor chip,
By connecting a dummy solder bump to the lower end of this through hole, heat dissipation is improved.

On page 117 (FIG. 7) of the above-mentioned document, a BGA using the TAB technique is described. In the case of this BGA, the semiconductor chip is a TA with wiring on both sides.
Face down bonding is performed on the main surface of the B tape via solder bumps. Also, this TAB tape
It is mounted on the printed wiring board via the second solder bumps connected to the back surface thereof. Further, a fixing plate is adhered to the peripheral portion of the TAB tape to prevent the TAB tape from warping. Regarding heat dissipation, a heat dissipation plate that doubles as a cap is attached to the back surface of the semiconductor chip.

[0007]

However, a BGA having a substrate made of resin, such as the plastic BGA described in the above-mentioned document, has a large warp due to the large thermal expansion coefficient of the substrate and is mounted on a printed wiring board. There is a problem that a solder bump connection defect is likely to occur during the soldering. Further, since the resin substrate also has a large thermal resistance, there is a limit to the improvement of the heat radiation property even if a through hole for heat radiation is provided on the substrate or a dummy bump is connected, and it cannot be applied to mounting a semiconductor chip with high heat generation. .

On the other hand, in the case of the BGA package using the TAB tape, since the fixing plate for preventing the warp of the tape is formed by hollowing out the semiconductor chip portion to form the cavity, the size of the semiconductor chip is increased and the package is increased. When approaching the size, there arises a problem that the rigidity of the fixing plate decreases and the warp increases.

Further, since solder bumps for connecting a printed wiring board cannot be attached to the TAB tape directly below the semiconductor chip which is not supported by the fixing plate, when the size of the semiconductor chip increases, the same number of solder bumps are connected. In order to do so, a larger size package is required, which makes it difficult to achieve high-density mounting, which is an inherent advantage of BGA packages.

An object of the present invention is to provide an LSI package having low thermal resistance.

Another object of the present invention is to provide an LSI package having high connection reliability when mounted on a printed wiring board.

Another object of the present invention is to provide an LSI package suitable for multi-pin / high-density mounting.

Another object of the present invention is to provide an LSI package which realizes the above object at a low cost.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

The typical ones of the inventions disclosed in the present application will be outlined below.

A semiconductor integrated circuit device according to the present invention comprises a substrate on which a semiconductor chip is mounted and an insulating tape having a wiring pattern and external electrode pads forming a part of the wiring pattern formed thereon. While arranging so that the electrode pad is located on the back side of the substrate,
A package in which the peripheral portion of the insulating tape is bent to the main surface side of the substrate, and the semiconductor chip mounted on the main surface of the substrate and one end of the wiring pattern located on the main surface side of the substrate are electrically connected. It has a structure.

The semiconductor integrated circuit device of the present invention has a package structure in which bump electrodes are connected in multiple stages to the external electrode pads.

In the semiconductor integrated circuit device of the present invention, the substrate is made of metal.

The semiconductor integrated circuit device of the present invention has a package structure in which the semiconductor chip is sealed with a mold resin or a resin cap.

In the semiconductor integrated circuit device of the present invention, the substrate is made of a conductive material and is electrically connected to the constant potential pad of the semiconductor chip and the constant potential external electrode pad of the insulating film, whereby the substrate is formed. The package structure has a constant potential.

In the semiconductor integrated circuit device of the present invention, a through hole reaching from the main surface to the back surface is provided in the substrate, and the external electrode pad at the bottom of the through hole is electrically connected to the semiconductor chip by a wire. It has a package structure.

In the semiconductor integrated circuit device of the present invention, guide holes are provided in the margins at the four corners of the insulating tape.

[0023]

According to the above means, since the substrate is made of metal having a high thermal conductivity and the semiconductor chip is mounted on the main surface of the substrate, the heat of the semiconductor chip is quickly dissipated to the outside through the substrate. It is possible to realize an LSI package with low thermal resistance.

According to the above-mentioned means, since the substrate is made of a metal having high rigidity, the warp of the substrate can be suppressed, so that the connection reliability of the bump electrodes when mounting the substrate on the printed wiring board is improved. Can be improved.

According to the above means, since the substrate is made of metal and the insulating film is bonded to the surface of the substrate, the external electrode pads can be arranged on the entire surface of the substrate. A suitable LSI package can be realized.

According to the above-mentioned means, the material of the substrate (metal) and the material of the cap (or mold resin) can be obtained at low cost, so that a low-cost LSI package can be realized.

According to the above-mentioned means, since the bump electrodes are connected to the external electrode pads in multiple stages, the diameter of the bump electrodes in the direction perpendicular to the main surface of the printed wiring board is substantially increased, so that the LSI package and the printed circuit board are printed. The stress applied to the bump electrode due to the difference in the thermal characteristics of the wiring board is easily absorbed and alleviated by the deformation of the bump electrode, and the deterioration of the bump electrode over time can be effectively suppressed.

According to the above means, the GND potential can be stabilized by fixing the substrate having a larger area than the semiconductor chip to a constant potential, for example, GND. Therefore, the operation of the LSI formed on the semiconductor chip The reliability can be improved.

According to the above means, the substrate is provided with a through hole reaching from the main surface to the back surface, and the external electrode pad at the bottom of the through hole is electrically connected to the semiconductor chip by a wire, whereby Since the semiconductor chip mounted on the main surface and the external electrode pad arranged on the back surface side of the substrate can be connected at the shortest distance, it is possible to reduce the wiring resistance and the inductance of the LSI package. It is possible to realize an LSI package suitable for mounting an LSI that operates in.

According to the above-mentioned means, by providing the guide holes in the margins at the four corners of the insulating film, when the bump electrodes of the LSI package and the lands of the printed wiring board are superposed, the guide holes are used as alignment guides. Therefore, the bump electrode and the land can be accurately overlapped.

[0031]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a plan view of an LSI package (semiconductor integrated circuit device) according to an embodiment of the present invention.
2 is a plan view showing a state where the cap of the LSI package is removed, and FIG. 3 is a sectional view of the LSI package (a sectional view taken along the line III-III in FIG. 1).

The LSI package of this embodiment shown in FIGS. 1 to 3 has a structure in which a semiconductor chip 2 is mounted on the central portion of the main surface of a rectangular substrate 1 and the semiconductor chip 2 is sealed with a cap 3. Has been done.

The substrate 1 is composed of an Al (aluminum) plate whose main surface and back surface are processed flat, and a thin film of aluminum oxide is formed on the surface by electrolytic treatment or the like. That is, the inside of the substrate 1 is made of a good conductor of heat and electricity, and the surface is made of an insulating material.

A semiconductor chip 2 is bonded (die-bonded) to the main surface of the substrate 1 with a silicone rubber adhesive 4, for example. The semiconductor chip 2 is made of single crystal silicon, and a logic LSI such as a gate array or a microcomputer is formed on the element formation surface thereof.

A TAB tape 6 is bonded to the surface of the substrate 1 with an epoxy resin adhesive 5, for example. The TAB tape 6 is composed of a single tape having an area larger than that of the substrate 1. The central portion of the TAB tape 6 is bonded to the back surface of the substrate 1, and the peripheral portion is bent to the main surface side of the substrate 1 and its peripheral portion. Is joined to.

The TAB tape 6 is composed of two layers of insulating tapes 7a and 7b made of polyimide resin, for example.
An external electrode pad 9 formed integrally with the lead wiring 8 is formed in a portion located on the back surface side of the substrate 1 and has a three-layer structure in which lead wirings 8 formed by etching a copper (Cu) foil are bonded together. Are provided in an array. It is also possible to manufacture the same structure as the TAB tape 6 by using a flexible printed wiring board.

At the peripheral portion of the TAB tape 6, that is, at the tip of the portion bent to the main surface side of the substrate 1, the end portion (inner lead portion) of the lead wiring 8 plated with Au is exposed. The inner lead portion and the bonding pad (not shown) of the semiconductor chip 2 are made of Au.
Are electrically connected by a wire 10.

A cap 3 for sealing the semiconductor chip 2
Are bonded to the peripheral portion of the main surface of the substrate 1 with a silicone rubber adhesive 11, for example. This cap 3
Is made of synthetic resin such as epoxy resin.

Next, an example of a method of assembling the LSI package will be described.

4 and 5 are plan views of the TAB tape 6 used for assembling this LSI package. FIG. 4 is a plan view of the insulating tape 7a of the two-layer insulating tapes 7a and 7b in the state in which the insulating tape 7a is shown in the front side, and the lead wiring 8 is shown by a broken line. FIG. 5 is a plan view showing a state in which the insulating tape 7b (shown by a gray shading pattern) is shown, and one end of the lead wiring 8 is exposed at the peripheral portion of the TAB tape 6 to form an inner lead portion. And the other end is T
They are arranged in an array at the center of the AB tape 6 and form the external electrode pads 9.

At the four corners of the TAB tape 6, there are left margins 6A in which the lead wires 8 are not formed, and in the center of each margin 6A, the LS which has been assembled is completed.
A guide hole 12 is provided as a positioning guide when the I package is mounted on the printed wiring board. The blank portion 6A may be cut and removed as needed after the LSI package is mounted on the printed wiring board.

Next, as shown in FIG. 6, the insulating tape 7a
The substrate 1 is placed in the central portion of the TAB tape 6 facing the front side, and the back surface of the substrate 1 and the insulating tape 7a are bonded with the adhesive 5. At this time, the guide hole 12 provided in the blank portion 6A of the TAB tape 6 can also be used as a positioning guide for the substrate 1 and the insulating tape 7a.

Next, as shown in FIG. 7, the peripheral portion of the TAB tape 6 protruding to the outside of the substrate 1 is bent upward,
After bonding the back surface (insulating tape 7a) to the main surface of the substrate 1 with the adhesive 5, the semiconductor chip 2 is attached to the central portion of the main surface of the substrate 1 with the adhesive 4 as shown in FIG. Join (die bonding).

Thereafter, the inner lead portion of the lead wiring 8 and the bonding pad of the semiconductor chip 2 are connected by the wire 10 (see FIG. 2), and then the semiconductor chip 2 is sealed with the cap 3 (FIG. 1, FIG. 1). (See FIG. 3)
Assembly of SI package is completed.

To mount the LSI package of this embodiment on a printed wiring board, as shown in FIG. 9 as an example,
Solder bumps 13, which are a type of bump electrode, are bonded to the external electrode pads 9 on the back surface of the substrate 1 to form an LSI package having a BGA structure. Then, as shown in FIG. Reflow by superimposing it on the land 15.

To bond the solder bumps 13 to the external electrode pads 9 of the TAB tape 6, for example, the external electrode pads 9 are used.
After the flux is applied to the solder, solder balls (Sn10% -Pb90%) that have been processed into a spherical shape are temporarily attached to the external electrode pad 9, and the solder balls are melted in a heating furnace, a screen printing method. After applying the cream solder to the external electrode pad 9 by, for example, a method of melting this cream solder in a heating furnace, forming a solder ball on the external electrode pad 9 by a ball bonding method,
There is a method of melting this solder ball in a heating furnace.

In order to mount the BGA structure LSI package formed by such a method on the printed wiring board 14, cream solder (Sn 63% Sn 63%) is applied to the land 15 of the printed wiring board 14 by, for example, a screen printing method.
(-Pb 37%), the solder bumps 13 of the LSI package may be superposed on the lands 15 and the cream solder may be melted in the heating furnace.

When the solder bumps 13 of the LSI package and the lands 15 of the printed wiring board 14 are overlapped with each other, the guide hole 1 formed in the blank portion 6A of the TAB tape 6 described above.
By using 2, solder bumps 13 and lands 15
Can be accurately overlapped. The guide hole 12 can be used, for example, by irradiating light from above the LSI package and detecting the light passing through the guide hole 12 from the back side of the blank portion 6A, or inserting a pin into the guide hole 12 to form the LSI package. May be temporarily fixed on the printed wiring board 14.

The second method of mounting the LSI package of this embodiment on the printed wiring board 14 is to connect the solder bumps 13 on the lands 15 of the printed wiring board 14 and then to connect the external electrode pads 9 of the LSI package thereto. This is a method of reflowing the solder bumps 13 by superimposing them. in this case,
Since bump electrodes are not joined to the external electrode pad 9 side,
The LSI package has a so-called Land Grid Array (LGA) structure. To connect the solder bumps 13 on the lands 15 of the printed wiring board 14, various methods of joining the solder bumps 13 to the external electrode pads 9 described above can be used. As described above, the LSI package of this embodiment can be used not only as a BGA package but also as an LGA package.

The LSI of this embodiment configured as described above
According to the package, the following effects can be obtained.

The substrate 1 is made of an Al material having a high thermal conductivity, and the semiconductor chip 2 is mounted on the main surface thereof,
Since the heat of the semiconductor chip 2 is quickly dissipated to the outside through the substrate 1, it is possible to realize an LSI package having a small thermal resistance.

Since the board 1 is made of a highly rigid Al material, the warp of the board 1 can be suppressed, so that the connection reliability of the solder bumps 13 when the board 1 is mounted on the printed wiring board 14 is improved. Can be made.

Since the substrate 1 is made of a hard material and the TAB tape 6 is bonded to the front surface of the substrate 1, the external electrode pads 9 can be arranged on the entire back surface of the substrate 1, so that multi-pin / high-density mounting can be achieved. A suitable LSI package can be realized.

Since the material for the substrate 1 (Al) and the material for the cap 3 (synthetic resin) can be obtained at low cost, a low-cost LSI package can be realized.

(Embodiment 2) FIG. 11 shows an LSI of this embodiment.
It is sectional drawing of a package. The difference from the LSI package of the first embodiment is that the semiconductor chip 2 is molded with a molding resin 16
And the bump electrodes connected to the external electrode pads 9 are made of Au balls 17.

Mold resin 1 for sealing the semiconductor chip 2
6 is composed of, for example, an epoxy resin. For sealing the semiconductor chip 2, an epoxy-based potting resin used in the TAB manufacturing process may be used. Also, Cu balls can be used for the bump electrodes connected to the external electrode pads 9. To bond the Au ball 17 (or Cu ball) to the external electrode pad 9, a well-known ball bonding method using heating, ultrasonic waves or energy of both may be used.

FIG. 11 shows an example in which Au balls 17 are connected in a single stage to the external electrode pads 9, but as shown in FIG.
The Au balls 17 may be connected in two stages, or three or more stages may be connected as required.

For example, in order to mount the LSI package having the BGA structure shown in FIG. 12 on the printed wiring board 14, first, as shown in FIG. 13, the tips of the Au balls 17 are flattened, and all the parts connected to the back surface of the board 1 are flattened. The heights of the Au balls 17 are made uniform. To flatten the tips of the Au balls 17, a flat tool (not shown) is pressed against all the Au balls 17 at once.

Next, cream solder (Sn6) is applied to the land 15 of the printed wiring board 14 by screen printing or the like.
3% -Pb37%) 27, and then, as shown in FIG.
Then, the cream solder 27 may be melted in a heating furnace.

As described above, according to the present embodiment, all the Au balls 17 on the back surface of the substrate 1 are simultaneously flattened at the same time, so that the Au balls 17 caused by the warp or undulation of the back surface of the substrate 1 are removed. Absorbs variations in height and all A
Since the heights of the u balls 17 can be aligned with high accuracy, all the Au balls 17 and the lands 15 can be surely brought into contact with each other when the board 1 is mounted on the printed wiring board 14.

Further, Au balls 17 are formed on the external electrode pads 9.
When two or more stages are connected, the Au ball 1 in the direction perpendicular to the printed wiring board 14 (and the board 1) is connected.
The diameter of 7 is substantially increased. As a result, due to the difference in thermal characteristics between the LSI package and the printed wiring board 14,
Since the stress applied to the u ball 17 is easily absorbed and alleviated by the deformation of the Au ball 17, it is possible to effectively suppress the deterioration of the Au ball 17 with time.

That is, according to this embodiment, the connection reliability between the LSI package and the printed wiring board 14 can be further improved.

(Embodiment 3) FIG. 15 shows an LSI of this embodiment.
It is sectional drawing of a package.

A characteristic of the LSI package of this embodiment is that the substrate 1 is fixed at a constant potential (for example, GND). To fix the substrate 1 to a constant potential, for example, GND, the insulating film 7 on the back surface of the external electrode pad 9 (GND) for GND is used.
A TAB tape 6 having a through hole 18 formed in a is prepared, and the TAB tape 6 is bonded to the back surface of the substrate 1 by using a conductive adhesive 19 such as Ag paste. The substrate 1 and the external electrode pad 9 (GND) are electrically connected through the agent 19, and the GND pad of the semiconductor chip 2 and the main surface of the substrate 1 are electrically connected by the wire 10. in this case,
Since the surface of the substrate 1 must also be conductive, the substrate 1
For example, a Cu plate whose surface is plated with Au is used as the material.

According to the LSI package of the present embodiment, the GND pad can be stabilized by connecting the GND pad of the semiconductor chip 2 to the large-area GND-fixed substrate 1 without redundancy. The operational reliability of the LSI formed in 2 can be improved.

(Embodiment 4) FIG. 16 shows an LSI of this embodiment.
It is sectional drawing of a package.

The LSI package of this embodiment is characterized in that a through hole 20 reaching from the main surface to the back surface is provided in a part of the substrate 1, and the external electrode pad 9 exposed at the bottom of the through hole 20.
(Or the through hole 18 formed in the insulating film 7a on the back surface of the external electrode pad 9) and the semiconductor chip 2 are electrically connected by the wire 10.

According to the LSI package of this embodiment, the semiconductor chip 2 mounted on the main surface of the substrate 1 and the external electrode pad 9 arranged on the back surface side of the substrate 1 can be connected at the shortest distance. As a result, wiring resistance and inductance of the LSI package can be reduced, so that an LSI package suitable for mounting an LSI that operates at high speed can be realized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

FIG. 17 shows an embodiment in which a cap-like cover 21 is provided at the end of the cap 3 of the LSI package shown in the first embodiment, and the TAB tape 6 bent on the side surface of the substrate 1 is covered with the cover 21. Is. According to this embodiment, the soft TA protruding laterally from the side surface of the substrate 1
It is possible to reliably prevent the B tape 6 from being damaged.

FIG. 18 shows part of the TAB tape 6 on the substrate 1.
By electrically connecting the semiconductor chip 2 and the lead wire 8 joined to the main surface of the main surface of the semiconductor chip 2 to the lead wire 8 by the wire 10, the TAB tape 6 immediately below the semiconductor chip 2 is connected to a capacitor (for example, a power supply bypass capacitor). ) Is an example used as.

FIG. 19 shows an A on the pad of the semiconductor chip 2.
The u bump electrode 22 is formed, and the second TAB tape 23 is formed.
In this embodiment, the bump electrode 22 and the lead wiring 8 of the TAB tape 6 are connected using the lead wiring 24 of FIG. In this embodiment, the TAB tape 23 having the area TAB structure is used, and the bump electrodes 2 are formed on the entire element formation surface of the semiconductor chip 2.
By arranging 2 pins, the number of pins is increased. Further, when mounting the semiconductor chip 2 in which the bump electrodes 22 are arranged on the peripheral portion of the element formation surface, as shown in FIG.
It is also possible to collectively bond the lead wiring 8 of the TAB tape 6 on the bump electrode 22.

FIG. 21 shows a package structure suitable for mounting the semiconductor chip 2 which generates a particularly large amount of heat. In this embodiment, the semiconductor chip 2 is connected to the substrate 1 via the solder bumps 25.
Face-down bonding on the main surface of the semiconductor chip 2 and the back surface (upper surface) of the semiconductor chip 2 is bonded to the lower surface of the Al cap 3. A radiating fin may be joined to the cap 3 as required, or the cap 3 itself may have a radiating fin shape. Also, the substrate 1
Of the semiconductor chip 2 and a part (for example, GND) through the internal wiring layer 26 of the substrate 1.
External electrode pads 9 (for use in) are connected at the shortest distance.

In the first embodiment, the TAB tape 6 is bonded to the substrate 1 and then the semiconductor chip 2 is bonded (die bonded). However, the step of bonding the TAB tape 6 to the substrate 1 and the semiconductor chip 2 are bonded. Any of the steps may be performed first. For example, as shown in FIG. 22, the substrate 1 and the semiconductor chip 2 are bonded to the TAB tape 6 in advance, then the TAB tape 6 is bent to bond the semiconductor chip 2 to the main surface of the substrate 1, and the TAB is further bonded. Tape 6
The lead wiring 8 at one end (A) and the lead wiring 8 at the other end (B) may be connected by a collective bonding method.

In the above-described embodiment, the case where the present invention is applied to the LSI package in which the logic LSI is mounted has been described, but it can also be applied to the LSI package in which the memory LSI is mounted. In this case, for example, a lead wire including a bus bar line is formed on a TAB tape, a plurality of semiconductor chips having memory LSIs are mounted on the TAB tape, and then the TAB tape is formed on the substrate by the method described in the above embodiment. A large-capacity LSI package having a multi-chip module structure can be realized by bonding them together.

[0077]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the present invention, the heat of the semiconductor chip is quickly dissipated to the outside through the substrate, so that an LSI package having a small thermal resistance can be realized.

According to the present invention, since the warp of the substrate can be suppressed, it is possible to improve the connection reliability of the bump electrode when the substrate is mounted on the printed wiring board.

According to the present invention, since the external electrode pads can be arranged on the entire surface of the substrate, an LSI package suitable for multi-pin high-density mounting can be realized.

According to the present invention, since the material of the substrate and the material of the cap can be obtained at low cost, a low cost LSI package can be realized.

According to the present invention, the stress applied to the bump electrodes due to the difference in thermal characteristics between the LSI package and the printed wiring board can be absorbed and alleviated by the deformation of the bump electrodes, so that the bump electrodes are deteriorated with time. Can be effectively suppressed.

According to the present invention, the GND potential can be stabilized, so that the operational reliability of the LSI formed on the semiconductor chip can be improved.

According to the present invention, the wiring resistance and the inductance of the LSI package can be reduced, and thus an LSI package suitable for mounting an LSI that operates at high speed can be realized.

According to the present invention, the guide holes provided in the margins at the four corners of the insulating film can be used as a positioning guide when the bump electrodes of the LSI package and the lands of the printed wiring board are superposed. The bump electrode and the land can be accurately overlapped.

[Brief description of drawings]

FIG. 1 is a plan view of an LSI package that is an embodiment of the present invention.

FIG. 2 is a plan view showing a state in which a cap of the LSI package shown in FIG. 1 is removed.

FIG. 3 is a cross-sectional view of the LSI package taken along the line III-III shown in FIG.

FIG. 4 is a plan view of a TAB tape used for assembling the LSI package shown in FIG.

5 is a plan view of a TAB tape used for assembling the LSI package shown in FIG.

6 is a perspective view illustrating a method of assembling the LSI package shown in FIG.

FIG. 7 is a cross-sectional view illustrating a method of assembling the LSI package shown in FIG.

8A and 8B are cross-sectional views illustrating a method of assembling the LSI package shown in FIG.

FIG. 9 is a sectional view of an LSI package having a BGA structure which is an embodiment of the present invention.

10 is a cross-sectional view showing a method of mounting the LSI package shown in FIG.

FIG. 11 is an LS having a BGA structure according to another embodiment of the present invention.
It is sectional drawing of I package.

FIG. 12 is an LS having a BGA structure according to another embodiment of the present invention.
It is sectional drawing of I package.

13 is a cross-sectional view showing the method of manufacturing the LSI package shown in FIG.

14 is a cross-sectional view showing the method of manufacturing the LSI package shown in FIG.

FIG. 15 is a cross-sectional view of an LSI package that is another embodiment of the present invention.

FIG. 16 is a cross-sectional view of an LSI package that is another embodiment of the present invention.

FIG. 17 is a cross-sectional view of an LSI package that is another embodiment of the present invention.

FIG. 18 is a cross-sectional view of an LSI package that is another embodiment of the present invention.

FIG. 19 is a cross-sectional view of an LSI package that is another embodiment of the present invention.

FIG. 20 is a cross-sectional view of an LSI package that is another embodiment of the present invention.

FIG. 21 is a cross-sectional view of an LSI package that is another embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the method of assembling the LSI package which is another embodiment of the present invention.

[Explanation of symbols]

 1 Substrate 2 Semiconductor Chip 3 Cap 4 Adhesive 5 Adhesive 6 TAB Tape 7a Insulating Tape 7b Insulating Tape 8 Lead Wiring 9 External Electrode Pad 10 Wire 11 Adhesive 12 Guide Hole 13 Solder Bump 14 Printed Wiring Board 15 Land 16 Mold Resin 17 Au ball 18 Through hole 19 Conductive adhesive 20 Through hole 21 Cover 22 Bump electrode 23 TAB tape 24 Lead wiring 25 Solder bump 26 Internal wiring layer 27 Cream solder

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 23/50 R H01L 23/12 Q (72) Inventor Sei Horiuchi 5 Kamimizumotocho, Kodaira-shi, Tokyo Chome No. 20-1 Hitate Super L.S.I. Engineering Co., Ltd. (72) Inventor Makoto Omata 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitate C.L.S.I. Engineering Co., Ltd. Within

Claims (9)

[Claims] 1. A substrate on which a semiconductor chip is mounted, and an insulating tape having a wiring pattern and external electrode pads forming part of the wiring pattern formed thereon, wherein the insulating tape is provided on the back surface of the substrate. The semiconductor chip mounted on the main surface of the substrate and the wiring pattern positioned on the main surface side of the substrate while bending the peripheral portion of the insulating tape to the main surface side of the substrate while arranging so as to be located on the main surface side. A semiconductor integrated circuit device characterized by being electrically connected to one end of. 2. The semiconductor integrated circuit device according to claim 1, wherein a bump electrode is connected to the external electrode pad, and the substrate can be mounted on a printed wiring board through the bump electrode. 3. The semiconductor integrated circuit device according to claim 2, wherein the bump electrodes are connected in multiple stages to the external electrode pads. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the substrate is made of metal. 5. The semiconductor chip is sealed with a mold resin or a resin cap.
5. The semiconductor integrated circuit device according to any one of items 4 to 4. 6. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor chip and one end of the wiring pattern are electrically connected by a bonding wire or a TAB lead. 7. The substrate is made of a constant potential by electrically connecting the substrate with a constant potential pad of the semiconductor chip and a constant potential external electrode pad of the insulating tape. 7. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device. 8. The substrate is provided with a through hole reaching from the main surface to the back surface, and the external electrode pad at the bottom of the through hole is electrically connected to the semiconductor chip by a wire. The semiconductor integrated circuit device according to any one of 1 to 7. 9. A guide hole is provided in a blank space at each of four corners of the insulating tape.
A semiconductor integrated circuit device according to item.