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JPH0810192Y2 - Semiconductor mounting structure - Google Patents

Semiconductor mounting structure

Info

Publication number
JPH0810192Y2
JPH0810192Y2 JP1991085683U JP8568391U JPH0810192Y2 JP H0810192 Y2 JPH0810192 Y2 JP H0810192Y2 JP 1991085683 U JP1991085683 U JP 1991085683U JP 8568391 U JP8568391 U JP 8568391U JP H0810192 Y2 JPH0810192 Y2 JP H0810192Y2
Authority
JP
Japan
Prior art keywords
semiconductor
mounting structure
wiring board
film carrier
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1991085683U
Other languages
Japanese (ja)
Other versions
JPH0538880U (en
Inventor
健一 森永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Funai Electric Co Ltd
Original Assignee
Funai Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Funai Electric Co Ltd filed Critical Funai Electric Co Ltd
Priority to JP1991085683U priority Critical patent/JPH0810192Y2/en
Publication of JPH0538880U publication Critical patent/JPH0538880U/en
Application granted granted Critical
Publication of JPH0810192Y2 publication Critical patent/JPH0810192Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】本考案は、フィルムキャリヤ(T
AB:Tape Automated Bondin
g)を利用して、例えば半導体チップ等の電子部品を配
線基板上に実装する半導体の実装構造に関するものであ
る。
[Industrial application] This invention is a film carrier (T
AB: Tape Automated Bondin
The present invention relates to a semiconductor mounting structure for mounting an electronic component such as a semiconductor chip on a wiring board using g).

【0002】[0002]

【従来の技術】従来より、ICやLSI等の半導体チッ
プの高性能化にともない、著しく高密度の実装技術が要
求されるようになって来た。そこで近年、ICチップ等
の高密度多端子を有する半導体チップ等の電子部品を高
い信頼性で配線基板上に接続する技術として、フィルム
キャリヤ(TAB)を利用して電子部品を印刷配線基板
上に高密度表面実装する実装技術が開発され実用される
ようになってきている。
2. Description of the Related Art Conventionally, as the performance of semiconductor chips such as ICs and LSIs has been improved, remarkably high-density mounting technology has been required. Therefore, in recent years, as a technique for connecting electronic components such as semiconductor chips having high-density multi-terminals such as IC chips onto a wiring board with high reliability, a film carrier (TAB) is used to mount electronic components on a printed wiring board. Mounting technology for high-density surface mounting has been developed and put into practical use.

【0003】[0003]

【考案が解決しようとする課題】しかしながら、上述し
た従来の実装技術において、複数個の半導体チップを基
板上に表面実装させた際には、当然ながらその複数個分
の面積を必要とすることになる。特に、例えば液晶パネ
ル・ICカード・電卓等の比較的制限された一定の実装
面積内に半導体チップを実装した場合には、その実装で
きる半導体チップの個数が制限される(個数が少なくな
る)という問題があった。
However, in the conventional mounting technique described above, when a plurality of semiconductor chips are surface-mounted on the substrate, the area for the plurality is naturally required. Become. In particular, when semiconductor chips are mounted within a relatively limited fixed mounting area such as a liquid crystal panel, an IC card, a calculator, etc., the number of semiconductor chips that can be mounted is limited (the number decreases). There was a problem.

【0004】従って、本考案は上記した事情を考慮して
なされたもので、複数個の電子部品を配線基板上に表面
実装させた際の実装面積を小さくすることができ、言い
換えれば多数の電子部品を実装でき著しく高密度の表面
実装が可能となる半導体の実装構造を提供することを目
的とするものである。
Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to reduce the mounting area when a plurality of electronic components are surface-mounted on a wiring board. An object of the present invention is to provide a semiconductor mounting structure capable of mounting components and capable of extremely high-density surface mounting.

【0005】[0005]

【課題を解決するための手段】本考案は上記した目的を
達成するために、半導体チップを搭載しフィルムキャリ
ヤにより形成されたTABパッケージを配線基板上に立
設するよう実装した半導体の実装構造において、両端の
接続部から屈曲して垂直に立上がる2つの折曲部を形成
して、側面視が略M字状を呈するように成した実装構造
であって、上記2つの折曲部の間の互いに背向いになる
位置に半導体チップをその厚み方向において重ならない
よう、上下に位置ずれを持たせて固定した構造である。
In order to achieve the above-mentioned object, the present invention provides a semiconductor mounting structure in which a semiconductor chip is mounted and a TAB package formed by a film carrier is mounted so as to stand on a wiring board. , A mounting structure in which two bent portions that bend from the connection portions at both ends and rise vertically are formed to have a substantially M-shape in a side view, and between the two bent portions. In this structure, the semiconductor chips are fixed to each other so that they do not overlap each other in the thickness direction, with a vertical displacement.

【0006】[0006]

【実施例】以下、本考案に係る半導体の実装構造の好適
一実施例を図面に基づいて説明する。図1は本実施例に
おける半導体の実装構造の縦置状態を示す図であり、同
図(a)はその全体斜視図、同図(b)はその側面図で
ある。図2は本実施例における半導体の実装構造の横置
状態を示す図であり、同図(a)はその全体斜視図、同
図(b)はその側面図である。図3は半導体チップを複
数搭載したフィルムキャリア(TAB)型半導体の構造
を示す平面図である。図4は半導体チップを単数搭載し
たフィルムキャリヤ(TAB)型半導体の構造を示す平
面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a semiconductor mounting structure according to the present invention will be described below with reference to the drawings. 1A and 1B are views showing a vertically mounted state of a semiconductor mounting structure in this embodiment. FIG. 1A is an overall perspective view thereof, and FIG. 1B is a side view thereof. 2A and 2B are views showing a laterally mounted state of a semiconductor mounting structure in this embodiment, FIG. 2A is an overall perspective view thereof, and FIG. 2B is a side view thereof. FIG. 3 is a plan view showing the structure of a film carrier (TAB) type semiconductor having a plurality of semiconductor chips mounted thereon. FIG. 4 is a plan view showing the structure of a film carrier (TAB) type semiconductor in which a single semiconductor chip is mounted.

【0007】まず、フィルムキャリヤ(TAB)型半導
体の構造は図3に示す如く、搬送及び位置決め用スプロ
ケットホール(11)と、半導体チップ(1)が入る開
孔部であるデバイスホール(19)及びOLB用ホール
(20)を有するポリイミド等の絶縁フィルム上に、銅
等の金属箔を接着し、金属箔をエッチング等により所望
の形状のリード(インナーリード(15),アウターリ
ード(16))と電気選別のためのパッド(14)とを
形成してフィルムキャリヤテープ(10)を製造する。
また、半導体チップ(1)の電極端子上に金属突起物で
あるバンプを形成する。
First, as shown in FIG. 3, the structure of a film carrier (TAB) type semiconductor is a sprocket hole (11) for carrying and positioning, a device hole (19) which is an opening portion into which a semiconductor chip (1) is inserted, and A metal foil such as copper is adhered onto an insulating film such as a polyimide having an OLB hole (20), and the metal foil is etched to form leads (inner leads (15) and outer leads (16)) having a desired shape. A film carrier tape (10) is manufactured by forming a pad (14) for electrical screening.
Further, bumps which are metal protrusions are formed on the electrode terminals of the semiconductor chip (1).

【0008】次に、フィルムキャリヤテープ(10)の
インナーリード(15)と半導体チップ(1)のバンプ
とを熱圧着法又は共晶法等によりインナーリードボンデ
ィング(ILB)し、フィルムキャリヤテープに装着さ
れた状態で電気選別用パッド(14)上に接触子を接触
させて半導体チップ(1)の電気選別及びバイアス試験
を実施する。これにより、フィルムキャリヤ型半導体装
置が完成する。なお、信頼性向上及び機械的保護のた
め、樹脂をポッテングして樹脂封止を行っても良い。
Next, the inner leads (15) of the film carrier tape (10) and the bumps of the semiconductor chip (1) are inner lead bonded (ILB) by a thermocompression bonding method or a eutectic method, and attached to the film carrier tape. In this state, a contactor is brought into contact with the electric selection pad (14) to perform electric selection and bias test of the semiconductor chip (1). As a result, the film carrier type semiconductor device is completed. In addition, in order to improve reliability and mechanical protection, the resin may be potted for resin sealing.

【0009】そして、上記したフィルムキャリヤ型半導
体装置を配線基板(2)に実装するために、アウターリ
ード(16)を所定の長さ(所定形状)に切断し、TA
Bパッケージ(5)を形成する。
Then, in order to mount the above film carrier type semiconductor device on the wiring board (2), the outer lead (16) is cut into a predetermined length (predetermined shape), and TA
Form B package (5).

【0010】なお、本実施例では、上記TABパッケー
ジ(5)の両端に配線基板(2)との接続部(4)
(4)が設けられており、更に、上記TABパッケージ
(5)を折り曲げ可能とするために屈曲部(例えばスリ
ット)(3a)・(3b)(3c)が複数形成されてい
るものである。
In this embodiment, the connection parts (4) to the wiring board (2) are provided at both ends of the TAB package (5).
(4) is provided, and a plurality of bent portions (for example, slits) (3a), (3b) and (3c) are further formed so that the TAB package (5) can be bent.

【0011】そして、本実施例では図1及び図2に示す
ように、上記の如く形成されたTABパッケージ(5)
を配線基板(2)上に立設する状態で実装するものであ
り、まず、TABパッケージ(5)の中央の屈曲部(3
a)部分で半導体チップ(1)(1)が互いに背向いに
なるよう2つ折りにし、そして両端の屈曲部(3c)
(3c)部分で接続部(4)(4)が互いに離反する方
向へ略90°屈曲したものである。例えば、接続部
(4)(4)の面積が少なく高さ方向(基板(2)に対
し垂直方向)に余裕のある場合には縦置状態(図1の
(a)及び(b))とし、あるいは、高さに余裕のない
場合には途中の屈曲部(3b)(3b)の部分で更に横
方向(基板(2)に対し水平方向)に折り曲げて、他の
半導体チップ部品(8)の上方に重ねて高さを低くした
横置状態(図2の(a)及び(b))に構成するもので
ある。
In this embodiment, as shown in FIGS. 1 and 2, the TAB package (5) formed as described above.
Is mounted on the wiring board (2) in an upright state. First, the bent portion (3) at the center of the TAB package (5) is mounted.
At the portion a), the semiconductor chips (1) and (1) are folded in two so that they face each other, and the bent portions (3c) at both ends.
In the portion (3c), the connecting portions (4) and (4) are bent by about 90 ° in the directions away from each other. For example, when the connecting portions (4) and (4) have a small area and there is a margin in the height direction (vertical direction to the substrate (2)), the state of vertical installation ((a) and (b) in FIG. 1) is set. Or, if there is no room in height, it is further bent in the lateral direction (horizontal direction with respect to the substrate (2)) at the bent portions (3b) (3b) in the middle, and other semiconductor chip parts (8) It is configured in a laterally placed state ((a) and (b) of FIG. 2) in which the height is reduced by stacking on the upper side of the.

【0012】なお、アウターリード(16)を配線基板
(2)の導電パターンにアウターリードボンディング
(OLB)する工程はILB工程と同様に加圧ツールに
より、リードを加圧加熱して実施するもので、接合は熱
圧着法又は共晶法又は半田を使用したろう付け等により
実施される。
The step of outer lead bonding (OLB) the outer lead (16) to the conductive pattern of the wiring board (2) is performed by pressurizing and heating the lead with a pressure tool as in the ILB step. The joining is performed by a thermocompression bonding method, a eutectic method, or brazing using solder.

【0013】以上、本考案の好適一実施例について詳細
に説明したが、本考案はこれに限定されるものではな
く、本考案の範囲を逸脱することなく種々の修正が可能
であることは明白である。
The preferred embodiment of the present invention has been described above in detail, but the present invention is not limited to this, and it is apparent that various modifications can be made without departing from the scope of the present invention. Is.

【0014】例えば、屈曲部(3a)・(3b)・(3
c)は本実施例のようなスリット形状に限らず、凹み,
ミシン目,薄み等、TABパッケージ(5)の屈曲を可
能にする種々の構造に置き換えることができる。また、
例えば図5に示す如く、TABパッケージ(5b)に搭
載する半導体チップ(1)(1)を、中心位置よりずら
して互いに異なる配置に形成し、アコーディオン式に折
り曲げて実装することにより、厚さ寸法(H)がより一
層薄くできる利点がある。また、上述した実施例では、
TABパッケージ(5)に半導体チップ(1)を2個搭
載した例で説明したが、これに限らず、2個以上(複
数)搭載できることは勿論のこと、例えば図4に示すT
ABパッケージ(5a)の如く、1個(単数)搭載して
も良いことは言うまでもない。この場合には、特にピン
数の多い半導体チップ(1)において、左右にパターン
を振り分けることにより接続部のピッチを広げることが
できる。なお、これら図4及び図5のTABパッケージ
(5a)及び(5b)において、符号は前述した実施例
と同一のため、ここでの説明は省略した。
For example, the bent portions (3a), (3b), (3
c) is not limited to the slit shape as in this embodiment, but may be
It can be replaced by various structures such as perforations, thinnesses, etc. that allow the TAB package (5) to bend. Also,
For example, as shown in FIG. 5, the semiconductor chips (1) and (1) to be mounted on the TAB package (5b) are formed in different arrangements by being displaced from the center position, and are bent and mounted in an accordion type to achieve a thickness dimension. There is an advantage that (H) can be made even thinner. Further, in the above-mentioned embodiment,
The example in which two semiconductor chips (1) are mounted on the TAB package (5) has been described, but the present invention is not limited to this, and of course, two or more (plural) semiconductor chips can be mounted.
It goes without saying that one piece (single piece) may be mounted like the AB package (5a). In this case, particularly in the semiconductor chip (1) having a large number of pins, it is possible to widen the pitch of the connection portion by allocating the patterns to the left and right. The reference numerals of the TAB packages (5a) and (5b) of FIGS. 4 and 5 are the same as those of the above-described embodiment, and thus the description thereof is omitted here.

【0015】以上の如く本実施例によれば、半導体チッ
プ(1)を搭載しフィルムキャリヤにより形成されたT
ABパッケージ(5)を配線基板(2)上に立設するよ
う実装したことにより、複数個の半導体チップ(1)を
配線基板(2)上に表面実装させた際の実装面積を小さ
くすることができ、言い換えれば多数の半導体チップ
(1)を実装することができ、著しく高密度の表面実装
が可能となる。更に、上記TABパッケージ(5)の両
端に配線基板(2)との接続部(4)(4)が設けられ
ていることにより、接続部の面積を少く構成することが
できると共に、立設したTABパッケージ(5)を安定
して支持することができる利点がある。更に、上記TA
Bパッケージ(5)に屈曲部(3b)等を設け屈曲可能
に構成したことにより、基板(2)に対し縦置状態(図
1参照)に限らず横置状態(図2参照)にもすることが
可能となり、高さを低く構成することができる利点があ
る。
As described above, according to the present embodiment, the T formed by the film carrier on which the semiconductor chip (1) is mounted.
By mounting the AB package (5) so as to stand on the wiring board (2), it is possible to reduce the mounting area when a plurality of semiconductor chips (1) are surface-mounted on the wiring board (2). In other words, a large number of semiconductor chips (1) can be mounted, and extremely high-density surface mounting becomes possible. Further, since the connecting portions (4) and (4) for connecting to the wiring board (2) are provided at both ends of the TAB package (5), the area of the connecting portion can be made small and the TAB package (5) is erected. There is an advantage that the TAB package (5) can be stably supported. Furthermore, the TA
Since the B package (5) is provided with the bending portion (3b) and the like so as to be bendable, the substrate (2) is not limited to the vertically placed state (see FIG. 1) but can be placed horizontally (see FIG. 2). Therefore, there is an advantage that the height can be reduced.

【0016】以上詳細に説明したように本考案によれ
ば、配線基板上に多数の電子部品を実装することがで
き、著しく高密度の表面実装が可能になり、略M字状の
2つの折曲部の間に半導体チップを固定しても、該チッ
プの厚み方向においては重ならないので、チップの発熱
が高温度となってしまうことが避けられる。
As described in detail above, according to the present invention, a large number of electronic components can be mounted on a wiring board, and extremely high density surface mounting is possible. Even if the semiconductor chips are fixed between the curved portions, they do not overlap in the thickness direction of the chips, so that the heat generation of the chips can be prevented from becoming high temperature.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本考案に係る半導体の実装構造の縦置状態を
示す図。
FIG. 1 is a view showing a vertically mounted state of a semiconductor mounting structure according to the present invention.

【図2】 本考案に係る半導体の実装構造の横置状態を
示す図。
FIG. 2 is a view showing a laterally mounted state of a semiconductor mounting structure according to the present invention.

【図3】 半導体チップを複数搭載したフィルムキャリ
ヤ(TAB)型半導体の構造を示す平面図。
FIG. 3 is a plan view showing the structure of a film carrier (TAB) type semiconductor on which a plurality of semiconductor chips are mounted.

【図4】 半導体チップを単数搭載したフィルムキャリ
ア(TAB)型半導体の構造を示す平面図。
FIG. 4 is a plan view showing the structure of a film carrier (TAB) type semiconductor in which a single semiconductor chip is mounted.

【図5】 本考案に係る半導体の実装構造の他の一例を
示す図。
FIG. 5 is a view showing another example of a semiconductor mounting structure according to the present invention.

【符号の説明】[Explanation of symbols]

(1) 半導体チップ (2) 配線基板 (3a)(3b)(3c) 屈曲部 (4) 接続部 (5)(5a)(5b) TABパッケージ (1) Semiconductor chip (2) Wiring board (3a) (3b) (3c) Bent part (4) Connection part (5) (5a) (5b) TAB package

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】半導体チップを搭載しフィルムキャリヤに
より形成されたTABパッケージを配線基板上に立設す
るよう実装した半導体の実装構造において、両端の接続
部から屈曲して垂直に立上がる2つの折曲部を形成し
て、側面視が略M字状を呈するように成した実装構造で
あって、上記2つの折曲部の間の互いに背向かいになる
位置に、半導体チップをその厚み方向において重ならな
いよう、上下に位置ずれを持たせて固定したことを特徴
とする半導体の実装構造。
1. A semiconductor mounting structure in which a semiconductor chip is mounted and a TAB package formed of a film carrier is mounted on a wiring board so as to stand upright.
Form two bends that bend from the
The mounting structure is such that the side view is substantially M-shaped.
There are two folds that are opposite to each other
Position, the semiconductor chips must not overlap in the thickness direction.
The semiconductor mounting structure is characterized in that it is fixed with a vertical displacement .
JP1991085683U 1991-10-22 1991-10-22 Semiconductor mounting structure Expired - Lifetime JPH0810192Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991085683U JPH0810192Y2 (en) 1991-10-22 1991-10-22 Semiconductor mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991085683U JPH0810192Y2 (en) 1991-10-22 1991-10-22 Semiconductor mounting structure

Publications (2)

Publication Number Publication Date
JPH0538880U JPH0538880U (en) 1993-05-25
JPH0810192Y2 true JPH0810192Y2 (en) 1996-03-27

Family

ID=13865649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991085683U Expired - Lifetime JPH0810192Y2 (en) 1991-10-22 1991-10-22 Semiconductor mounting structure

Country Status (1)

Country Link
JP (1) JPH0810192Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879032B2 (en) * 2003-07-18 2005-04-12 Agilent Technologies, Inc. Folded flex circuit interconnect having a grid array interface

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61121449A (en) * 1984-11-19 1986-06-09 Nippon Telegr & Teleph Corp <Ntt> Mounting structure and process of lsi chip
JPS6211295A (en) * 1985-05-11 1987-01-20 沖電気工業株式会社 Mounting of electronic component
JPS62195156A (en) * 1986-02-21 1987-08-27 Fuji Electric Co Ltd Mounting of semiconductor chip

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