JPH0775291B2 - Class D amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a class D amplifier for the purpose of highly efficient power amplification of acoustic signals.

[0002]

2. Description of the Related Art In recent years, a class D amplifier has been used as a high-efficiency power amplifier for acoustic signals, and has an advantage that it can process power at a particularly high level with high efficiency.

A conventional class D amplifier for the purpose of high efficiency power amplification is disclosed in, for example, Japanese Patent Laid-Open No. 2-177606.

The signal processing method of the conventional class D power amplifier will be described below. FIG. 4 is a block diagram of this conventional class D amplifier. In FIG. 4, 10 is an analog signal input terminal, 11 is a comparator, 12 is a drive amplifier, 13 is a pulse amplifier, 14 and 15 are coils and capacitors forming a low-pass filter, 16 is an output terminal, 17 is a load, and 18 is a triangular wave. A signal generator, 19 is an FM modulator, 20 is a basic signal oscillator, and 21 is a random signal oscillator.

The operation of the class D amplifier configured as described above will be described below.

First, the acoustic signal input to the analog signal input terminal 10 is input to the (-) input terminal of the comparator 11, and the triangular wave signal is input from the triangular wave signal oscillator 18 to the (+) input terminal of the comparator 11. It This 2
The amplitude of the seed signal is compared by the comparator 11,
Converted to bit digital signal. That is, the output C _out of the comparator 11, C _out = 0 when the acoustic signal> triangular wave signal, and C _out = 1 when the acoustic signal <triangular wave signal. A waveform diagram of this conversion is shown in FIG. From this, C
_It can be seen that out was converted into a pulse width modulation signal with the frequency of the triangular wave signal as the carrier. The output C _{out of the} comparator 11 is amplified by the drive amplifier 12, and further power-amplified by the pulse amplifier 13. The power-amplified pulse width modulation signal is used for the coil 14 and the capacitor 15.
Unnecessary component is removed by a low pass filter consisting of
An acoustic signal is output from the output terminal 7. Further, in order to improve the characteristics as an amplifier, feedback is applied from the output of the pulse amplifier 13 to the (−) input terminal of the comparator 11 via a resistor.

[0007]

However, in the above conventional configuration, a triangular wave generator is required to obtain a pulse width modulated signal, and a triangular wave with good linearity is required to obtain an amplifier with a low distortion rate. However, there is a problem in that it has to be generated and the structure must be complicated.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to provide a highly efficient power amplifier capable of selecting a signal processing system of a class D amplifier with a simple structure.

[0009]

In order to achieve this object, a class D amplifier of the present invention comprises a difference integrator which outputs a difference integration signal obtained by integrating a difference between an input signal and a pulse output signal which is a feedback signal. , The polarity of the difference integration signal is judged to be 1
A 1-bit quantizer that outputs a digital signal of bits,
A delay device for delaying the digital output signal of the 1-bit quantizer with a clock having an arbitrary frequency; and a digital signal selection switch for selecting the output signal of the delay device or the digital output signal of the 1-bit quantizer. A pulse amplifier for power-amplifying the digital signal selected by the digital signal selection switch, a feedback circuit for sending the pulse output signal amplified by the pulse amplifier to the difference integrator as a feedback signal, and an output of the pulse amplifier And a low-pass filter that passes only a signal in a necessary frequency band.

[0010]

The present invention has the above-mentioned configuration and has a differential integrator,
The bit quantizer, delay device, digital signal selection switch, pulse amplifier and feedback circuit form a closed loop circuit.
When the output signal of the delay device is selected by the digital signal selection switch and amplified by the pulse amplifier, this closed loop circuit becomes a negative feedback state in the low frequency region mainly due to the phase delay of the differential integrator and delay device, and in the high frequency region. Since it becomes a positive feedback state, it oscillates in a high frequency range. The oscillation frequency is not a constant frequency because the closed loop circuit and the feedback circuit are configured to correct the 1-bit quantization error in the low frequency range. As a result, the oscillation frequency of the feedback circuit, that is, the frequency of the carrier signal constantly changes, and the energy of the carrier signal is diffused without being concentrated at a single frequency and its harmonics.

On the other hand, when the output signal of the 1-bit quantizer is selected by the digital signal selection switch and is amplified by the pulse amplifier, the closed loop circuit is in a negative feedback state, and the differential integrator inputs the feedback signal from the pulse amplifier. A difference signal from the signal is detected, and the difference signal is integrated. The output signal of the differential integrator is converted into a digital signal by the 1-bit quantizer and power-amplified by the pulse amplifier. By repeating these operations by the closed loop circuit, the circuit oscillates at a constant frequency.

As described above, the signal processing method of the amplifier can be set to the pulse density modulation or the pulse width modulation with the digital signal selection switch.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a class D amplifier according to an embodiment of the present invention. In FIG. 1, 1 is an input terminal, 2 is an input signal input to the input terminal 1 and an output signal which is a feedback signal, and a difference integrator which outputs a difference integration signal obtained by integrating a difference value between these two signals. Reference numeral 3 is a 1-bit quantizer for converting the differential integrated signal into a digital signal, and 4 is a digital signal selection switch. A delay device 5 delays the digital output signal of the 1-bit quantizer with a clock having an arbitrary frequency, and is composed of a D-type flip-flop or the like. 6 is a clock oscillator that generates a clock pulse of an arbitrary frequency, 7 is a pulse amplifier that power-amplifies the digital output signal of the delay device 5, 8 is a low-pass filter that removes unnecessary signal components from the output signal of the pulse amplifier 7, 9 Is an output terminal, and 30 is a feedback circuit.

The operation of the class D amplifier of the present embodiment constructed as above will be described below. The output signal of the pulse amplifier 7 via the feedback circuit 30 is input as a feedback signal to the difference integrator 2 together with the input signal from the input terminal 1, the difference value between the two signals is integrated, and the difference integrator 2 outputs the difference integration signal. Is output. The difference integration signal is input to the 1-bit quantizer 3 and converted into a 1-bit digital signal by the 1-bit quantizer 3. The 1-bit digital signal is input to the delay unit 5 and delayed by a time period corresponding to the repetition cycle of the clock supplied from the clock oscillator 6 to the delay unit 5. The delay-processed digital signal and the output digital signal of the 1-bit quantizer 3 are selected by the digital signal selection switch 4, and one of the signals is power-amplified by the pulse amplifier 7. The output signal of the pulse amplifier 7 is input to the difference integrator 2 via the feedback circuit 30. Further, the output signal of the pulse amplifier 7 is input to the filter 8 including a coil and a capacitor, unnecessary signal components are removed, and the output signal is output from the output terminal 9.

When the output of the delay device 5 is selected by the digital signal selection switch 4, delta-sigma modulation is performed in the closed circuit loop, and the output of the 1-bit quantizer 3 becomes a pulse density modulation signal. Differential integrator 2, 1-bit quantizer 3, digital signal selection switch 4, delay device 5, pulse amplifier 7
The closed circuit loop including the feedback circuit is configured to be negative feedback in the low frequency range, but is positive feedback in the high frequency range due to the phase delay caused by the differential integrator 2 and the delay device 5. Therefore, the closed circuit loop is oscillated in a high frequency range (carrier oscillation), but its oscillation frequency is lower than the clock frequency of the clock oscillator 6.

Here, a description of the delta-sigma modulator will be given with reference to FIG.
Do with FIG. 2 is a block diagram of a second-order delta-sigma modulator, in which T is a delay device for delaying the input signal by one sample clock period. When the delta-sigma modulator of FIG. 2 is expressed by the Z conversion formula, the following formula (1) is obtained.

Vo (z) = − αVin (z) [2-Z ⁻¹ ] + [2Z ⁻¹ −Z ⁻² ] [Vo (z) −αYo (z)] (1) In FIG. The block diagram of the delta-sigma modulation amplifier shown has a modified configuration based on the above equation (1).

Next, it will be shown that the delta-sigma modulation amplifier shown in FIG. 1 is equivalent to the delta-sigma modulator shown in FIG. The input / output characteristic of the differential integrator 2 needs to be the characteristic represented by the following equation (2). Sampling period = T, difference integrator input signal = Vs, difference integrator output signal = Vo,

[0020]

[Equation 1]

If this is expressed by the Z conversion formula, the following formula (3) is obtained.
It Vo (z) =-α [2Vs (z) -Z^-1Vs (z) ＋ 2Z^-1Vo (z) -Z^-2Vo (z)] (3) If the output of the 1-bit quantizer 3 is Yo, pulse amplification
Since the output of the device 7 has a time delay of T in the delay device 5, Z
^-1It becomes Yo (z). Output signal Z of pulse amplifier 7 ^-1Yo (z)
And the signal Vin applied to the two-state modulation input terminal 1 is Vs (z)
Is expressed by the following equation (4).

Vs (z) = Vin (z) + Z ⁻¹ Yo (z) (4) If formula (4) is used to represent formula (3), the following formula (5) is obtained.

Vo (z) = − αVin (z) [2-Z ⁻¹ ] + [2Z ⁻¹ −Z ⁻² ] [Vo (z) −αYo (z)] (5) Formula (5) ) Is the same as the equation (1), and it can be seen that the delta-sigma modulation amplifier shown in FIG. 1 and the delta-sigma modulator shown in FIG. 2 operate similarly.

FIG. 3 shows the signal and quantization noise spectrum of the delta-sigma modulator. Quantization noise due to the 1-bit quantizer is considered to be white noise, but due to the noise shaping characteristic of delta-sigma modulation, a peak of the quantization noise appears near 1/2 of the sampling frequency (clock frequency of the delay device).

Similarly, in the class D amplifier of the present invention, the noise shaping characteristic is also exhibited in the case of a closed circuit loop in which the output signal of the delay device 5 is selected by the digital signal selection switch 4 and the power is amplified by the pulse amplifier 7. Also, the sampling frequency is the frequency of the clock supplied to the delay device 5, as in the delta-sigma modulator. The frequency at which the closed circuit loop oscillates in a high frequency range (carrier oscillation) works so as to reduce the quantization error and is not constant.

Next, a description will be given of the case where the digital output signal of the 1-bit quantizer 3 is selected by the digital signal selection switch 4 and amplified by the pulse amplifier 7. Difference integrator 2, 1
Pulse width modulation is performed in a closed circuit loop including the bit quantizer 3, the digital signal selection switch 4, the pulse amplifier 7 and the feedback circuit 30. The output signal of the pulse amplifier 7 passes through the feedback circuit 30 and is then integrated by the differential integrator 2, and the integrated output is added to the 1-bit quantizer 3. If the integrated output is equal to or higher than the quantization level of the 1-bit quantizer 3 (assuming 0 volt), the output of the 1-bit quantizer 3 is "
1 ", and the output of the 1-bit quantizer 3 becomes" 0 "if it is below the quantization level. Since the closed circuit loop constitutes a negative feedback circuit, the differential integrator which constitutes the closed circuit loop. 2, 1-bit quantizer 3, digital signal selection switch 4, pulse amplifier 7 oscillates according to the time constant, and 1-bit quantizer 3 and pulse amplifier 7 output a pulse with a duty cycle of 50%. When an input signal is applied to the input terminal 1 while the circuit loop is oscillating, the integrated output of the differential integrator 2 is biased in accordance with the input signal, and the biased integrated output is a 1-bit quantizer. Since it is quantized by 3, the 1-bit quantizer 3 outputs a pulse having a biased amount, that is, a duty cycle corresponding to the input signal, and a PWM modulation signal is obtained.

[0027]

As described above, according to the present invention, the difference integrator (2) that outputs the difference integration signal obtained by integrating the difference between the input signal and the pulse output signal that is the feedback signal, and the polarity of the difference integration signal are determined. 1-bit quantizer (3) for outputting a 1-bit digital signal, a delay device (5) for delaying the digital output signal of the 1-bit quantizer (3) with a clock of an arbitrary frequency, and a delay device (5) Alternatively, a digital signal selection switch (4) for selecting the digital signal output from the 1-bit quantizer (3), and a pulse amplifier (amplifying the power of the digital signal selected by the digital signal selection switch (4) ( 7) and a feedback circuit (30) for sending the pulse output signal of the pulse amplifier (7) as a feedback signal to the difference integrator (2), thereby making the signal processing method of the class D amplifier a digital signal. It can be easily switched by-option switch.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a class D amplifier according to an embodiment of the present invention.

FIG. 2 is a block diagram of a delta-sigma modulator according to the same embodiment.

FIG. 3 is a characteristic diagram showing a signal and a quantization noise spectrum of the delta-sigma modulator in the example.

FIG. 4 is a block diagram showing a configuration of a conventional pulse width modulation amplifier.

[Explanation of symbols]

 1 Input Terminal 2 Differential Integrator 3 1-bit Quantizer 4 Digital Signal Selection Switch 5 Delay Device 6 Clock Oscillator 7 Pulse Amplifier 8 Low Pass Filter 9 Output Terminal 30 Feedback Circuit

Claims (1)

[Claims] 1. A difference integrator that outputs a difference integration signal obtained by integrating a difference between an input signal and a pulse output signal that is a feedback signal, and a polarity of the difference integration signal is determined and converted into a 1-bit digital signal. 1-bit quantizer, delay device for delaying the digital output signal of the 1-bit quantizer with a clock of an arbitrary frequency, output signal of the delay device, and digital output signal of the 1-bit quantizer A digital signal selection switch, a pulse amplifier that power-amplifies the digital signal selected by the digital signal selection switch, and a feedback circuit that sends the pulse output signal amplified by the pulse amplifier to the difference integrator as a feedback signal. A low-pass filter that is connected to the output of the pulse amplifier and passes only a signal in a necessary frequency band, .