JPH0746499B2 - Sense amplifier circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sense amplifier circuit suitable for a memory circuit including a MOSFET.

[Description of Prior Art]

2. Description of the Related Art In recent years, in dynamic memory circuits using MOSFETs, memory cells that can be realized in a small area have been actively developed due to the increase in capacity. Some of such memory cells distinguish between two states corresponding to two logic levels by the difference in the current flowing through the memory cell during a read.

However, in the conventional MOSFET integrated circuit, a circuit capable of effectively detecting a difference in current has not been known. Therefore, conventionally, a resistance is used to convert a current into a voltage, and a sense amplifier for detecting a difference in potential is used to detect which one of the two states. In this case, assuming that the current difference between the two states is ΔI and the resistance that allows the current to flow is R, the following relationship holds between the obtained potential difference ΔV and ΔI, R according to Ohm's law.

ΔV = R × ΔI Therefore, in order to obtain a large potential difference, the resistance value R must be increased.

However, it is difficult to accurately create a resistance in a MOS integrated circuit, and it is particularly difficult for a resistance value to be large. Therefore, when the detection circuit is composed of a MOS integrated circuit, there is a possibility that it may not operate properly due to variations in resistance value.

[Explanation of Object of Invention]

In view of this point, the present invention has an object to provide a sense amplifier circuit particularly suitable for detecting a difference in current.

[Description of Configuration of Invention]

The present invention relates to a first load element having one end connected to a first power supply and the other end connected to a first output terminal, and a drain electrode connected to the first output terminal and a source electrode connected to a second power supply. A connected first MISFET, a second load element having one end connected to the first power supply and the other end connected to a second output terminal, and a drain electrode connected to the second output terminal and a source electrode A second MISFET connected to the second power source, a source electrode connected to the gate electrode of the first MISFET, a gate electrode connected to the second output terminal, and a drain electrode connected to the first input terminal. The connected third MISFET and the source electrode are connected to the second MI.
A fourth MISFET connected to the gate electrode of the SFET, a gate electrode connected to the first output terminal and a drain electrode connected to the second input terminal, and a drain electrode connected to the gate electrode of the first MISFET. A fifth MISFET having a gate electrode connected to the clock input terminal and a source electrode connected to the second power supply.
And a sixth MISFET having a drain electrode connected to the gate electrode of the second MISFET, a gate electrode connected to the clock input terminal, and a source electrode connected to the second power supply. It is a sense amplifier circuit.

[Explanation of Examples]

 An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, depletion type MOSFETs 1 and 3 operate as load elements, and constitute an inverter together with MOSFET 2 and MOSFET 4, respectively. The electrical characteristics of the MOSFETs 1 and 3 and the MOSFETs 2 and 4 are matched. During standby, a potential for conducting the MOSFETs 7 and 8 is applied to the clock input terminal 13, and as a result, the potentials of the connection points 18 and 19 to which the gate electrodes of the MOSFETs 2 and 4 are connected are the power source.
It is approximately equal to the potential V _SS of 15. Therefore, the MOSFETs 2 and 4 are both cut off, and the two output terminals 9 and 10 are both connected to the power supply 14
The potential V _{DD of} is shown.

During operation, the potential of clock input terminal 13 is
Change to a potential that blocks 7 and 8. A current to be compared is applied to the input terminals 11 and 12. This current is MOSF
It flows through the ET5 and the MOSFET 6 to charge the stray capacitance 16 at the connection point 18 and the stray capacitance 17 at the connection point 19, respectively. As a result, the potential between the connection point 18 and the connection point 19 _changes from the potential V _SS to the potential V _SS.
Change towards _DD . Here, it is assumed that the capacitance 16 and the capacitance 17 have the same value. Generally, in a MOSFET integrated circuit, the capacitance value is almost determined by the geometrical shape, so that it is much easier to control than the resistance value. Therefore, this condition can be easily satisfied.

Now, it is assumed that the current applied to the input terminal 11 is larger than the current applied to the input terminal 12. In this case, the potential of the connection point 18 changes faster than the potential of the connection point 19. As a result, the MOSFET 2 eventually becomes conductive and the potential of the output terminal 9 drops. As a result, the MOSFET 6 is cut off, the charging of the capacitor 17 is stopped, and the potential increase at the connection point 19 is also stopped. In this way, the potential of the output terminal 10 remains V _DD , the potential of the output terminal 9 becomes a value close to V _SS , and it can be detected that the current applied to the input terminal 11 is larger. On the contrary, if the current applied to the input terminal 12 is larger than the current applied to the input terminal 11, the potential of the output terminal 9 is V _DD and the potential of the output terminal 10 is V _DD in the same manner.
_It is close to _SS .

In the embodiment shown in FIG. 1, even when the potential of the output terminal 9 is close to V _SS and the MOSFET 6 is in the cutoff state, the MOSFET 6
When the leakage current of is large, the capacitor 17 is gradually charged, and eventually MOSFET 4 becomes conductive, and the potential of the output terminal 10, which should have been V _DD , changes to a potential close to V _SS and the output terminal 9
It is considered that the potential difference between 10 and 10 becomes small and becomes zero after a long time.

FIG. 2 shows another embodiment of the present invention which operates even when such a leak current is large.

The circuit of FIG. 2 is similar to the circuit of FIG. 1 with MOSFETs 21 and 26,
And an inverter consisting of MOSFETs 23 and 24 and MOSFETs 25 and 26.
Inverter consisting of and is added.

The operation of the circuit shown in FIG. 2 will be described below. As an example, consider the case where the current applied to input terminal 11 is greater than the current applied to input terminal 12. In this case, as described above, the potential of the output terminal 9 becomes a value close to V _SS , and the MOSFET 6 is shut off. At this time, the MOSFET 26 is also cut off at the same time, the potential of the connection point 28 becomes V _DD , and the MOSFET 22 which has been in the cut-off state is made conductive. The MOSFET 22 maintains the potential of the connection point 19 at a value close to V _SS regardless of the presence or absence of the leakage current of the MOSFET 6, and therefore the MOSFE
T4 never conducts.

Yet another embodiment of the present invention is shown in FIG.

The circuit shown in FIG. 3 has MOSFETs 31, 32, 33, 3 added to the circuit shown in FIG.
4 has been added.

Hereinafter, as an example, consider a case where the current applied to the input terminal 11 is larger than the current applied to the input terminal 12.
In this case, when the potential of the output terminal 9 changes, the MOSFET 31 is cut off so that the potential of the connection point 18 does not rise further. This is done by changing the potential of the clock input terminal 13 to bring the MOSFETs 7 and 8 into a conductive state and discharging the capacitor 16 in order to return to the standby state after the operation is completed and return to the standby state. This is to speed up. At this time, the potential of the output terminal 9 changes only to the potential required to shut off the MOSFET 31. Therefore, the MOSFET 34 is required to shut off the MOSFET 6. MOSFET 34 is connection point 37
And 38, a potential difference corresponding to the threshold voltage is generated, and the connection point 37
In accordance with the potential of the connection point 19, the potential of the connection point 19 is sufficiently close to V _SS as compared with the potential of the connection point 18, and the MOSFET 6 is turned off.
This prevents the potential of the MOSFET from rising and turning on the MOSFET 4.

In each of the embodiments described above, the stray capacitances are considered as the capacitors 16 and 17, but it is also possible to add a capacitance element separately as needed. A simple inverter circuit consisting of MOSFETs 1 and 2 or MOSFETs 3 and 4 is used as the circuit that actually generates the output potential, but it is better to use a cascode amplifier circuit or Schmitt trigger circuit with a higher gain. In some cases, good characteristics can be obtained. In the above embodiment, MOSF
Although the case of using the ET has been described, generally, the same can be applied to any MISFET.

[Explanation of Effect of Invention]

As described above, according to the present invention, it is possible to obtain a current value detection type sense amplifier circuit that can detect and amplify a current difference without converting it into a potential difference through a resistor and is not affected by variations in resistance value. Therefore, it has a great effect in the MIS dynamic RAM using the current detection type memory cell.

[Brief description of drawings]

1, 2 and 3 are circuit diagrams showing an embodiment of the present invention. 1,2,3,4,5,6,7,8,21,22,23,24,25,26,31,32,33,34 …… M
OSFET, 9,10 …… Output terminal, 11,12 …… Input terminal, 13 ……
Clock input terminal, 14,15 ... power supply, 16, 17 ... capacity.

Claims (1)

[Claims] 1. A first load element having one end connected to a first power supply and the other end connected to a first output terminal; and a drain electrode connected to the first output terminal and a source electrode connected to a second output terminal. A first MISFET connected to a power supply, a second load element having one end connected to the first power supply and the other end connected to a second output terminal, and a drain electrode connected to the second output terminal. A second MISFET having a source electrode connected to the second power supply, a source electrode connected to the gate electrode of the first MISFET, a gate electrode connected to the second output terminal, and a drain electrode connected to the first input. The third MISFET connected to the terminal and the source electrode are connected to the second
A MISFET, a gate electrode connected to the first output terminal and a drain electrode connected to the second input terminal, and a drain electrode connected to the first MISFET.
A fifth MI connected to the gate electrode of the second power source, the gate electrode to the clock input terminal, and the source electrode to the second power source.
And a sixth MISFET having a drain electrode connected to the gate electrode of the second MISFET, a gate electrode connected to the clock input terminal, and a source electrode connected to the second power supply. Sense amplifier circuit to do.