JPH022238B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input circuit for a monolithic integrated semiconductor memory device using field effect transistors, which includes a dynamic charge up circuit in a circuit for enhancing the known bootstrap effect.

Due to their small size and low power consumption compared to bipolar transistor monolithic integrated storage circuits, field effect transistors are widely used as the main memory in modern program-controlled data processing systems.

Field effect transistor (hereinafter referred to as FET)
As an input circuit for a monolithic integrated semiconductor memory device designed in
As known from No. 671, circuits utilizing the so-called bootstrap effect are often used. Such a circuit, the circuit diagram of which is shown in FIG. 1A, acting as an inverter, provides an output level that rises rapidly to the value of the operating voltage VH when reducing the input level.

FET storage devices are often controlled by digital circuits designed with bipolar transistors because bipolar transistors have faster switching speeds than field effect transistors. The so-called TTL level system is a typical voltage level system for digital circuits using bipolar transistors. Therefore, one binary state, e.g. logical "0"
Suppose that is represented by a voltage in the range 0 to 0.8 volts, and another binary state, e.g., a logic "1", is represented by a voltage in the range from 2.0 volts to a maximum operating voltage of, e.g., 5.5 volts. however,
Typical upper control levels and operating voltages for FET circuits are relatively high, for example VH = 8.5 volts. That is, a MOS field effect transistor with a typical threshold voltage of 1.5 volts and controlled with an upper input level of 2 volts in the worst case,
It will conduct only in a relatively low range. A FET controlled in this way still has a relatively high impedance even in its conducting state. Therefore, it is quite slow in performing the required charging or discharging of other circuit nodes, capacitances, etc. Therefore, separate level converters are often used to interface between the bipolar and FET components.

The circuit according to FIG. 1A is preferably controlled at the FET level, and also by the TTL level if FETs 2 and 3 are of correspondingly large dimension. The bootstrap inverter is formed by FETs 2-7 and bootstrap capacitor 6. The gate electrodes of FETs 4 and 5 which are interconnected are
FET wired to form a bipolar circuit electronic
Through 7, operating voltage VH minus FET threshold voltage
Charged up by VT. two inputs
When FETs 2 and 3 are made non-conductive, the input capacitance 9 of the circuit connected to the output 8 of the inverter is not parallel to the capacitor 6, so
The potential at both electrodes of the capacitor 6 rapidly rises (bootstraps) via the FET 5.

In order to make the present invention easier to understand, the following section 1B
The structure and operation will be briefly explained based on the diagram. This circuit is described in German published patent specification 22 43671
As is known from the above publication, it consists of the bootstrap inverter shown in FIG. 1A and a dynamic charge-up circuit for rapidly charging the load capacitance 9 added thereto. The bootstrap inverter consists of FETs 2 to 7 and the bootstrap inverter.
Although formed by capacitor 6, the dynamic charge up circuit is composed of FETs 10 and 11 and capacitor 12.

Dynamic charge up circuit is FET10 and 11
and a capacitor 12, the gate electrodes of the interconnected FETs 4 and 5 are connected to the operating voltage VH minus through the FET 7.
In addition to being charged up to the FET threshold voltage VT, when the leading edge of the input signal arrives, the operating voltage
Charged up to full VH value. The leading edge of the input signal arrives, via capacitor 12,
When transferred to the gate charged up to the voltage VH-VT of FET 10, its gate potential rises to a value of approximately 2VH-VT, resulting in its source potential 23 and the gate electrodes of interconnected FETs 4, 5. The potential comes to take the value of VH. In this way, by charging up the gate electrode to the full operating voltage VH, the two loads are
When the input signal falls, the gate potential of FETs 4 and 5 increases to such an extent that they are switched
FETs 2 and 3 become non-conducting and the potential of bootstrap capacitor 6 rises through FET 5, so that the load capacitance 9 rises to the full operating voltage VH faster than without the dynamic charge-up circuit. do.

However, an advantageous circuit based on FIG.
It has the disadvantage of requiring FET level.
When control is implemented at low TTL levels, the TTL potential swing is as small as 2 - 0.8 = 1.2 volts, causing node 23 to be overloaded by the charge-up circuit.
It is not charged up to VH and therefore has no value. Therefore, as in the circuit of FIG. 1A, only charge-up transistor T7 is connected to node 2.
3 to the maximum value of VH-VT.

Since the circuit according to FIG. 1B cannot be used as an input circuit for FET storage devices to be controlled at TTL level, the present invention provides a remedy. The invention characterized in the claims provides that, despite the control by the TTL level,
Through the charge up of the gates of the FETs 4 and 5, the output node 8 can be rapidly charged to the operating voltage VH. It fulfills the purpose of providing an input circuit for a FET storage device.

The main advantage of the present invention is that a bipolar level converter is no longer needed to convert the VH level to the level required to control the FET storage device.

Next, the present invention will be explained in detail with reference to the drawings.

The circuit diagrams of FIGS. 1A, 1B, 2, and 4 assume a conventional N-channel MOS-FET with a typical operating voltage of about 8.5 volts. However, the invention can equally be implemented with FETs of other conductivity types and operating voltages modified accordingly.

FIG. 2 shows a circuit diagram of a first embodiment of the present invention. This TTL level controllable storage input circuit is a variation of the circuit based on FIG. 1B. Components of the circuit of FIG. 2 that correspond to components of the circuit of FIG. 1B are given the same reference numerals. Consisting of FETs 10 and 11 and capacitor 12, interconnected FETs
Since the dynamic charge up circuit with gate electrodes 4 and 5 requires FET level operational control, capacitor 12 in the circuit of FIG.
The first electrode of the FET is not connected to input terminal 1.
It is connected to the output 17 of an inverter 16, represented in block form, which follows the input circuit for the storage device. In addition, charge up FET1 in Figure 2
1 is connected not to the anode VH of the supply voltage, but to the output 19 of an inverter 18 following the inverter 16, also represented in block form. Furthermore, a common contact 20 of the second electrode of the capacitor 12 with the source of the charge-up FET 11 and the gate of the load FET 10 connects three series-arranged discharges.
It is connected to the gate of FET11 via FET13,14,15.

The operation of the input circuit shown in FIG. 2 will be explained with reference to the pulse diagram shown in FIG. Input terminal 1 of input circuit
Assume that the TTL signal (FIG. 3) applied to the OFF state is initially at a high TTL level, but is now at a signal down level.
Switching FETs 2 and 3, which were previously conducting, are now non-conducting, so that the output 8 of the input stage, which previously indicated the FET signal down level, is now at the known level of the bootstrap capacitor 6. Rapidly high for effect
Due to the bootstrap effect of capacitor 6, the potential of node 23, which takes the FET output level, becomes
When the voltage rises above VH, current flows through FET 10 to the anode VH of the operating current supply because the voltage increase at node 23 caused by bootstrap capacitor 6 is prevented as the potential at node 24 rises. do not have. The output potential at output 8 will rise more slowly and will not reach the full value of the operating voltage source VH. FETs 13, 14, 15 and their control pulses 19, which are opposite in phase to the input signal, cause the gate 20 of FET 10 to
When the potential 23 rises above the value VH, being discharged before dropping to a potential below -VT, the FET 10 becomes positively non-conductive. Since the gate of FET 13 is connected to the anode VH of the operating voltage supply, this FET is always in a conductive state. By connecting the drain and gate, FETs 14 and 15
Wired to form a bipolar circuit element.

The input circuit of FIG. 2 is preferably implemented as a level converter in a dynamic FET storage chip. TTL chip selection signal CS, for example input 1
can be applied to The longest CS cycle is in the range of 100 microseconds since chips must be selected continuously to regenerate dynamic storage cells. The input circuit itself is also regenerated in this way. For example, node 23 will have a leakage current of 100
It is discharged to a value slightly lower than the value VH in microseconds. However, when starting storage, the charge up circuit is still disabled and node 23 is
It is maintained at a value slightly lower than the value VH-VT by FET7 alone. Therefore, at the beginning of the first cycle, the voltage at the output 8 of the input circuit increases only slowly and with a delay because the potential VH-VT at node 23 is low. At the end of the first cycle, node 23 is charged to potential VH via the charge-up circuit, ie via FET 10. In the second and subsequent cycles, the output voltage rises very quickly with virtually no delay.

FIG. 3 shows a pulse diagram of the input circuit described according to the invention, representing the potential changes at each node of the circuit. From this pulse diagram, it can be seen that after the first cycle, the rise time of the potential of the output 8 is about half of the value in the first cycle. The cycle time is assumed to be 360 nanoseconds.

FIG. 4 is a circuit diagram of another embodiment of the invention. The only difference from FIG. 2 is that the switching transistors 2 and 3 are controlled with interconnected source electrodes and a fixed bias potential VB is applied to their interconnected gate electrodes. Due to this feature of circuit functioning, the input signal is in phase with the output signal appearing at output 8. There are no other differences to the circuit diagram of FIG. The operation of the circuit of FIG. 4 is also consistent with that described with respect to FIG. This is proven from the pulse diagram in FIG. In Figure 5, the voltage applied to terminal 1 is
Only the TTL input signal shows an opposite phase compared to the pulse diagram of FIG.

As mentioned above, the circuits of FIGS. 2 and 4 include a Bell converter for the chip select signal and a signal amplifier.
Particularly suitable. Since the chip select signal must drive a very high capacitive load in the storage chip, inverters 16 and 18 are not additionally required in the present invention, but are provided for amplification.

[Brief explanation of drawings]

FIG. 1A is a circuit diagram of an input circuit for a FET storage device with FET or TTL levels, constructed from a known inverter circuit. FIG. 1B is a circuit diagram of an input circuit for a FET storage device operated by FET levels, consisting of a known inverter supplemented with a dynamic charge-up circuit. FIG. 2 is a circuit diagram of a first embodiment based on the present invention. FIG. 3 is a pulse diagram of the input circuit based on FIG. 2; FIG. 4 is a circuit diagram of a second embodiment based on the present invention. FIG. 5 is a pulse diagram of the input circuit based on FIG. 4.

Claims (1)

[Claims] 1. An input circuit for a field effect transistor memory device having a bootstrap circuit operable in response to an input signal and a charge up circuit coupled to the bootstrap circuit, the charge up circuit comprising: a first field effect transistor coupled to a bootstrap node of the bootstrap circuit; a second field effect transistor having a source connected to the gate of the first field effect transistor; and one field effect transistor connected to the gate of the first field effect transistor. a capacitor having electrodes connected thereto, the other electrode of the capacitor being connected to the output of an inverter following the bootstrap circuit, and the gate of the first field effect transistor connected to the second field effect transistor via a discharge path. an input circuit for a field effect transistor memory device connected to the gate of and the output of an inverter following said inverter.