JPH0745818A - Uneven channel doped mos transistor and its manufacture - Google Patents

Abstract

PURPOSE:To enable high-speed operation by reducing the junction capacitance of source and drain sections, in a MOS transistor. CONSTITUTION:In a MOS transistor, the implantation of ions into a channel is twice performed, in two steps, low energy implantation and high energy implantation. The high energy implantation is limited to only the gate, using a mask, and the low energy implantation is performed to the whole face of a channel region 7. Hereby, the concentration of ions is low in the sections of a source 2 and a drain 3, so the junction capacitance decreases, and high- speed operation becomes possible. Moreover, the variation of threshold, in cases where the misalignment between a mask for ion implantation and a gate occurs, becomes small by performing the ion implantation with high energy which influences greatly the threshold to the whole face.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to non-uniform channel doping M.
The present invention relates to an OS transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a conventional MOS transistor, normally, FIG.
The element isolation layer 2 formed on the substrate 23 as shown in FIG.
A mask 22 is formed on the surface of the device isolation layers 20 and 20.
Channel ions are implanted on the entire surface of the device region 21 between them. However, according to this method, as shown in FIG. 7B, the substrate concentration in the source 25 and the drain 26 formed on both sides of the drain 24 is increased, the junction capacitance in the source / drain portion is increased, and the transistor is in operation. However, there was a problem that the load increased and the speed decreased. Therefore,
As shown in FIG. 8A, a method has been proposed in which the junction capacitance is reduced by implanting only a portion to be a channel portion using a mask 22 (Semiconductor device manufacturing method Japanese Patent Application No. 2-13).
4865).

[0003]

However, in the method of implanting only the gate 24 shown in FIG. 8, when the misalignment between the channel implantation mask and the gate mask occurs, the substrate below the gate electrode is removed. There is a problem that a region where the impurity concentration is low is partially formed and the threshold voltage varies. In addition, the reduction of the capacitance on the source 25 side does not usually affect the improvement of the operation speed, and it is desirable that the capacitance is large to some extent for stabilizing the power supply voltage. However, the method of FIG. 8 has a problem that the capacity on the source 25 side is reduced and the power supply voltage becomes unstable.

An object of the present invention is to provide an MO capable of high speed operation.
An object is to provide an S transistor and a manufacturing method thereof.

[0005]

In order to achieve the above object, a non-uniform channel-doped MOS transistor according to the present invention has a non-uniform channel having a gate, a source, a drain, and a high-concentration channel injection region in a substrate. Dope M
In the OS transistor, the gate is formed by laminating a part of the channel region in the substrate through an oxide film, and the source and the drain are arranged on both sides of the gate.
The high-concentration channel injection region extends over the channel region below the gate and the channel region in which the source and the drain are formed, and is formed by being buried in the channel region of the substrate. Formed by injection.

The implantation depth of the high-concentration channel implantation region is such that the depth in the channel region below the gate is deeper than that in the channel regions in the source and drain portions.

Further, the implantation depth of the high-concentration channel implantation region is such that the depths in the channel region under the gate and the channel region in the source portion are deeper than those in the channel region in the drain portion.

The method for manufacturing a non-uniform channel-doped MOS transistor according to the present invention has a high energy ion implantation step and a low energy ion implantation step, and includes a channel region located below the gate and both sides of the gate. A method for manufacturing a non-uniform channel-doped MOS transistor in which a high-concentration channel injection region having different depths is formed over a channel region formed by embedding a source and a drain arranged in The implantation step is a step of performing ion implantation with high energy into the channel region corresponding to the gate portion or the channel region corresponding to the gate and source portions to form a high concentration channel implantation region in the channel region at a constant depth. Yes, the low-energy ion implantation process is equivalent to the entire gate, source, and drain parts. Performs threshold control channel implantation with low energy Yaneru region, the channel region of at least the drain of ion implantation with a high energy has not been performed, a step of shallow high concentration channel injection region.

The method of manufacturing a non-uniform channel-doped MOS transistor according to the present invention includes a high-energy ion implantation step and a rotating oblique ion implantation step, and a channel region located below the gate and both sides of the gate. A method for manufacturing a non-uniform channel-doped MOS transistor, wherein a high-concentration channel-implanted region having different depths is formed across a channel region formed by embedding a source and a drain, which are high energy ion implantation. The process is
This is a step of performing high-energy ion implantation into the channel region corresponding to the gate portion or the channel region corresponding to the gate and source portions to form a high-concentration channel implantation region at a constant depth in the channel region. In the ion implantation process, using the gate laminated in a part of the channel region as a mask, the channel region other than the gate is subjected to threshold energy control channel implantation with low energy, and the ion implantation with high energy is not performed. Is a step of shallowly forming a high-concentration channel injection region in the channel region of the portion.

[0010]

In the present invention, shallow channel implantation, which has a large influence on the threshold voltage, is performed over the entire surface of the element region, so that even if the channel implantation mask and the gate mask are misaligned, A region having a low substrate impurity concentration does not occur, and the fluctuation of the threshold voltage can be reduced.

Further, by implanting the same deep channel as the gate portion into the source portion, the substrate concentration at the source junction portion increases, the capacitance between the source and the substrate increases, and the voltage of the source electrode stabilizes during circuit operation. However, high speed operation is possible.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.
Although the following description will be given for an n-type MOSFET, a p-type M
The same applies to the OSFET.

(Embodiment 1) FIG. 1 is a sectional view showing Embodiment 1 of the present invention.

In FIG. 1, a non-uniform channel-doped MOS transistor according to the present invention comprises a gate 1 and a source 2.
And the drain 3 and the high-concentration channel implantation region 4 on the substrate 5.

The gate 1 is a device isolation layer (see FIG.
Corresponding to the element isolation layers 6 and 6 in the inside) are laminated on a part of the channel region 7 via the oxide film 8, and the source 2 and the drain 3 are arranged on both sides of the gate 1 and 5 is formed by being buried in the channel region 7.

The high-concentration channel implantation region 4 is formed by straddling the channel region 7 below the gate 1 and the channel region 7 in which the source 2 and the drain 3 are formed, and by implanting at different depths. As for the depth of the high-concentration channel injection region 4, the depth D ₁ in the channel region 7 below the gate 1 is deeper than the depth D ₂ in the channel region 7 of the source 2 and drain 3 portions (D ₁ > D ₂ ).

As shown, the high-concentration channel implantation region 4
Is formed up to a deep portion in the channel portion (channel region located below the gate 1), and is formed only in a portion shallower than the source / drain junction in the source / drain portion. Substrate concentration is reduced and the capacity of this part is reduced.

The manufacturing process of this transistor will be described below with reference to FIG.

As shown in FIG. 2A, high-energy channel ion implantation is performed by using a mask 9 having an opening only in the channel portion, and high-concentration channel implantation is performed deeply in the portion where the channel of the substrate is formed. Region 4 is formed.

As shown in FIG. 2B, a low energy threshold control channel implantation is performed using a mask 10 having an opening on the entire surface of the channel region 7 (a mask is not required if it is not a CMOS). As a result, the high-concentration channel injection region 4 is formed in the shallow portion of the entire surface of the channel region 7.

Finally, the gate 1 is formed in a part of the channel region 7 through the oxide film 8 and a mask 10 having an opening over the entire device region is used (a mask is not required if not CMOS).
The source / drain ions are implanted into the channel region 7 located on both sides of the gate 1, the junction between the source 2 and the drain 3 is buried in the channel region 7, and the manufacturing process shown in FIG. When combined with the process, the mask process used in FIG. 2A is a normal channel implantation mask process, and therefore only the mask process of FIG. 2B is added.

Next, another embodiment of the method of manufacturing the MOS transistor shown in FIG. 1 will be described with reference to FIG. Figure 3
As shown in (a), high-energy channel ion implantation is performed using a mask 9 having an opening only in the channel portion to form a high-concentration channel implantation region 4 deep in the substrate where the channel is formed. . After that, Fig. 3 (b)
As shown in, the gate 1 is formed on the channel region 7 through the oxide film 8.

Next, as shown in FIG. 3C, a low energy threshold control channel is formed by rotating oblique ion implantation using a mask 11 having an opening over the entire surface of the element region (a mask is not required in the case of non-CMOS). Make an injection. As a result, the high-concentration channel injection region 4 is formed in the shallow portion of the entire surface of the channel region 7.

Finally, using a mask 11 having an opening on the entire surface of the channel region 7 (a mask is not required if it is not CMOS), source / drain ions are implanted into the channel region 7 excluding the gate 1 to form the source 2 and the drain 3. To form a bond with.

The manufacturing process shown in FIG. 3 is a method not using the mask shown in FIG. In this step, since the same mask is used in FIGS. 3C and 3D, the number of PR steps can be reduced by one as compared with the step of FIG. In the process of FIG. 3, since the crystal recovery by annealing is not performed between the processes of (a) to (c), the disorder of the crystallinity of the channel portion becomes larger than that of other portions, and the impurity in this portion is increased. Is promoted, and the impurities implanted in FIG. 3C are more likely to diffuse into the channel portion.

(Second Embodiment) FIG. 4 is a sectional view showing a second embodiment of the present invention.

As shown in FIG. 4, the high-concentration channel injection region 4
Is the depth of the channel portion D ₁ and the depth of the source 2 D ₂
Is deep, and the high-concentration channel injection region 4 in the drain 3 is formed only in a portion shallower than the coupling of the drain 3. With such a structure, since the substrate concentration of the junction of the drain 3 is low, the capacitance of this portion is reduced, but the capacitance between the source 2 and the substrate 5 is reduced by the conventional MOSFE.
As with T, this capacitance acts as a stabilizing capacitance. Further, in this method, when the channel implantation mask is shifted to the drain side with respect to the gate 1, the threshold voltage hardly changes, and only when it is shifted to the source side, the substrate impurity concentration below the gate is reduced. And the threshold fluctuates. Therefore, due to misalignment compared to the conventional method of FIG.
The probability that the threshold changes will be 1/2. The manufacturing process of this structure is as follows.

In order to manufacture the MOS transistor shown in FIG. 4, as shown in FIG. 5 (a), high energy channel ion implantation is carried out using a mask 9 having an opening only in the channel portion, and the channel of the substrate is The high-concentration channel injection region 4 is formed deep in the substrate in the portion to be formed. Next in FIG.
As shown in (b), using a mask in which the entire surface of the channel region 7 is opened (a mask is not required if it is not CMOS),
Low-energy threshold control channel injection is performed. As a result, the high-concentration channel injection region 4 is formed in the shallow portion of the entire surface of the channel region 7.

As shown in FIG. 5C, a gate 1 is formed, and a source / drain ion implantation is performed using a mask 9 in which the entire surface of the channel region 7 is opened (a mask is not required unless CMOS is used). A junction between the source 2 and the drain 3 is formed.

FIG. 6 is a process chart showing another embodiment of the method for manufacturing the MOSFET shown in FIG. As shown in FIG. 6A, using a mask 9 in which only the channel portion is opened,
High-energy channel ion implantation is performed to form a high-concentration channel implantation region 4 deep in the substrate in the portion where the channel is formed. Then, the gate 1 is formed as shown in FIG. As shown in FIG. 6C, a mask 9 in which the entire surface of the channel region 7 is opened is used (CMOS
If not, a mask is not required), and low-energy threshold control channel implantation is performed by rotating oblique ion implantation. As a result, the high-concentration channel injection region 4 is formed in the shallow portion of the entire surface of the channel region 7. Finally, Fig. 6 (d)
As shown in FIG. 3, a mask 9 in which the entire surface of the channel region 7 is opened
Is used (a mask is not required if not CMOS), and source / drain ion implantation is performed to form a source / drain junction.

[0031]

As described above, according to the present invention, the MOS
The transistor can be operated at high speed by reducing the source / drain or drain junction capacitance of the FET. Further, since shallow channel implantation, which has a large influence on the threshold value, is performed on the entire surface of the element region, it is possible to suppress the threshold voltage variation due to the positional deviation between the channel implantation mask and the gate mask. Further, when only the junction capacitance of the drain portion is reduced, the capacitance between the source and the substrate is the same as that of the conventional MOS transistor.
For this reason, when the source is used as a power supply or ground terminal and the drain is used as a signal terminal, the signal line has a small capacitance and high-speed operation is possible, and at the same time, the capacitance between the power supply and ground is the stabilizing capacitance with the substrate. Since it works, the voltage drop of the voltage at the time of switching becomes small, and the speed is not lowered.

[Brief description of drawings]

FIG. 1 is a sectional view showing a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a process drawing showing an example of a method for manufacturing a MOS transistor according to Example 1 of the present invention.

FIG. 3 is a process drawing showing another embodiment of the method of manufacturing the MOS transistor according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a MOS transistor according to a second embodiment of the present invention.

FIG. 5 is a process drawing showing an example of a method for manufacturing a MOS transistor according to Example 2 of the present invention.

FIG. 6 is a process drawing showing another embodiment of the method of manufacturing the MOS transistor according to the second embodiment of the present invention.

FIG. 7A is a diagram showing a conventional channel ion implantation method that does not limit the implantation range, and FIG. 7B is a device structure diagram.

FIG. 8A is a diagram showing a conventional channel ion implantation method that does not limit the implantation range, and FIG. 8B is a device structure diagram.

[Explanation of symbols]

 1 gate 2 source 3 drain 4 high concentration channel injection region 5 substrate 7 channel region 8 oxide film

Claims (5)

[Claims] 1. A non-uniform channel-doped MOS transistor having a gate, a source, a drain, and a high-concentration channel injection region in a substrate, wherein the gate has an oxide film in a part of the channel region in the substrate. The source and drain are formed on both sides of the gate and buried in the channel region of the substrate.The high-concentration channel injection region is the channel region below the gate. And a channel region in which a source and a drain are formed, and the non-uniform channel-doped MOS transistor is formed by implanting at different depths. 2. The implantation depth of the high concentration channel implantation region is
The nonuniform channel dope M according to claim 1, wherein the depth of the channel region below the gate is deeper than that of the channel region of the source and drain portions.
OS transistor. 3. The implantation depth of the high-concentration channel implantation region is
2. The nonuniform channel-doped MOS transistor according to claim 1, wherein the depth of the channel region under the gate and the depth of the channel region of the source portion are deeper than those of the drain region. 4. A channel region having a high energy ion implantation process and a low energy ion implantation process, the channel region being located below the gate, and a channel formed by embedding a source and a drain arranged on both sides of the gate. A method of manufacturing a non-uniform channel-doped MOS transistor, wherein a high-concentration channel-implanted region having a different depth is formed across a region, wherein the high-energy ion implantation step includes a channel region corresponding to a gate portion or a gate and This is a step of implanting high-energy ions into a channel region corresponding to a source portion to form a high-concentration channel implantation region in the channel region to a certain depth. The low-energy ion implantation step is performed in the gate, source, and drain portions. Channel injection for threshold control with low energy into the entire channel region corresponding to A channel region of at least the drain of ion implantation is not performed by the energy, the production method of the heterogeneous channel dope MOS transistor, which is a process for shallow high concentration channel injection region. 5. A channel region having a high-energy ion implantation process and a rotating oblique ion implantation process, the channel region being located below the gate, and a channel region formed by embedding a source and a drain disposed on both sides of the gate. A method of manufacturing a non-uniform channel-doped MOS transistor in which a high-concentration channel implantation region having different depths is formed over a channel region corresponding to a gate portion or a gate and source region. Is a step of performing high-energy ion implantation in a channel region corresponding to a portion to form a high-concentration channel implantation region in the channel region at a certain depth. Channel injection for threshold control with low energy in the channel region excluding the gate using the formed gate as a mask Performed, the channel region of at least the drain of ion implantation with a high energy has not been performed, the manufacturing method of the non-uniform channel doping MOS transistor, which is a process for shallow high concentration channel injection region.