JP2658810B2 - Non-uniform channel-doped MOS transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a non-uniform channel doped M
The present invention relates to an OS transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a conventional MOS transistor, FIG.
(A), the element isolation layer 2 formed on the substrate 23
A mask 22 is provided on the device isolation layers 20 and 20.
Channel ions were implanted into the entire surface of the element region 21 between them. However, according to this method, as shown in FIG. 7B, the substrate concentration at the source 25 and the drain 26 formed on both sides of the drain 24 is increased, the junction capacitance at the source / drain portion is increased, and the operation time of the transistor is increased. There is a problem that the load is increased and the speed is reduced. Therefore,
As shown in FIG. 8A, a method has been proposed in which the junction capacitance is reduced by implanting only the portion to be a channel portion using the mask 22 (Semiconductor Device Manufacturing Method Japanese Patent Application No. 2-13).
4865).

[0003]

However, in the method of implanting only the gate 24 shown in FIG. 8, when the misalignment between the channel implantation mask and the gate mask occurs, the substrate below the gate electrode is displaced. There is a problem that a region where the impurity concentration is partially low is formed and the threshold voltage fluctuates. Further, the reduction of the capacitance on the source 25 side does not usually affect the improvement of the operation speed, and it is desirable that the capacitance is somewhat large to stabilize the power supply voltage. However, the method of FIG. 8 has a problem in that the capacity on the source 25 side is reduced and the power supply voltage becomes unstable.

An object of the present invention is to provide an MO capable of operating at high speed.
An S transistor and a method for manufacturing the same are provided.

[0005]

To achieve the above object, a non-uniform channel-doped MOS transistor according to the present invention has a non-uniform channel having a gate, a source, a drain, and a high-concentration channel injection region on a substrate. Dope M
In an OS transistor, a gate is formed by laminating a part of a channel region in a substrate via an oxide film, and a source and a drain are arranged on both sides of the gate.
The high-concentration channel implantation region is formed buried in the channel region of the substrate. The high-concentration channel implantation region straddles the channel region below the gate and the channel region where the source and the drain are formed, and has different depths. The high-concentration channel implantation region has an implantation depth of
The depth of the channel region in the channel region and the source portion of the Gate downward is deeper than that of the channel region of the drain part.

[0006]

[0007]

Further, a method of manufacturing a non-uniform channel-doped MOS transistor according to the present invention includes a high energy ion implantation step and a low energy ion implantation step, wherein a channel region located below the gate and both sides of the gate are provided. A method for manufacturing a non-uniform channel-doped MOS transistor which straddles a channel region formed by embedding a source and a drain buried in the substrate and forming a high-concentration channel implantation region having different depths, comprising the steps of: In the implantation step, high-energy ion implantation is performed on a channel region corresponding to a gate portion or a channel region corresponding to a gate and a source portion, and a high-concentration channel implantation region is formed in the channel region. Department
Of the drain region
In the low-energy ion implantation step, a low-energy threshold control channel implantation is performed in all the channel regions corresponding to the gate, source, and drain portions, and a high-energy ion implantation is performed. In this step, a high-concentration channel implantation region is formed shallowly in at least the channel region of the drain portion where the implantation has not been performed.

Further, a method of manufacturing a non-uniform channel-doped MOS transistor according to the present invention includes a high energy ion implantation step and a rotating oblique ion implantation step, wherein a channel region located below the gate and both sides of the gate are provided. A method for manufacturing a non-uniform channel-doped MOS transistor which straddles a channel region formed by burying an arranged source and drain and forms a high-concentration channel-implanted region having a different depth, comprising the steps of: The process is
High-energy ion implantation is performed in a channel region corresponding to the gate portion or a channel region corresponding to the gate and source portions, and a high-concentration channel implantation region is formed in the channel region.
The depth in the channel region is
This is a step of forming a layer deeper than the one , and in the rotation oblique ion implantation step, using a gate stacked on part of the channel region as a mask, a threshold energy control channel implantation with low energy is performed in the channel region except the gate, This is a step of forming a shallow high-concentration channel implantation region at least in the channel region of the drain portion where ion implantation with high energy was not performed.

[0010]

According to the present invention, a shallow channel implantation having a large effect on the threshold voltage is performed over the entire element region, so that even if the misalignment between the channel implantation mask and the gate mask occurs, the lower portion of the gate electrode can be obtained. A region having a low substrate impurity concentration does not occur, and the fluctuation of the threshold voltage can be reduced.

Further, by performing the same deep channel implantation in the source as in the gate, the substrate concentration at the source junction increases, the capacitance between the source and the substrate increases, and the voltage of the source electrode becomes stable during circuit operation. Thus, a high-speed operation becomes possible.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.
The following description will be made with respect to an n-type MOSFET.
The same can be applied to the OSFET.

(Embodiment 1) FIG. 1 is a sectional view showing Embodiment 1 of the present invention.

In FIG. 1, a non-uniform channel-doped MOS transistor according to the present invention has a gate 1 and a source 2
, A drain 3, and a high-concentration channel injection region 4 on the substrate 5.

The gate 1 has an element isolation layer (FIG.
(Corresponding to the element isolation layers 6 and 6 in the middle) are laminated on a part of the channel region 7 with an oxide film 8 interposed therebetween, and the source 2 and the drain 3 are arranged on both sides of the gate 1. 5 buried in the channel region 7.

The high-concentration channel implantation region 4 is formed by straddling the channel region 7 below the gate 1 and the channel region 7 in which the source 2 and the drain 3 are formed, and implanting them at different depths. The depth D _{1 of} the high-concentration channel implantation region 4 in the channel region 7 below the gate 1 is larger than the depth D ₂ in the channel region 7 of the source 2 and the drain 3 (D ₁ > D ₂ ).

As shown in FIG.
Is formed to a deep portion in a channel portion (a channel region located below the gate 1), and is formed only in a portion shallower than a source / drain junction in a source / drain portion. Of the substrate becomes lower, and the capacitance of this portion decreases.

The manufacturing process of this transistor will be described below with reference to FIG.

As shown in FIG. 2A, high-energy channel ion implantation is performed using a mask 9 having an opening only in the channel portion, and high-concentration channel implantation is performed deep into the substrate where the channel is to be formed. Region 4 is formed.

As shown in FIG. 2B, a low-energy threshold control channel implantation is performed by using a mask 10 having an opening on the entire surface of the channel region 7 (no mask is required if the device is not CMOS). Thus, a high-concentration channel implantation region 4 is formed in a shallow portion of the entire surface of the channel region 7.

Finally, the gate 1 is formed in a part of the channel region 7 via the oxide film 8 and a mask 10 having an opening over the entire device region is used (a mask is unnecessary in the case of non-CMOS).
The source / drain ions are implanted into the channel region 7 located on both sides of the gate 1 and the junction between the source 2 and the drain 3 is buried in the channel region 7, and the manufacturing process shown in FIG. When combined with the process, the mask process used in FIG. 2A is a normal channel implantation mask process, and therefore, the number of processes is increased only by the mask of FIG. 2B.

Next, another embodiment of the method for manufacturing the MOS transistor shown in FIG. 1 will be described with reference to FIG. FIG.
As shown in FIG. 3A, high-energy channel ion implantation is performed using a mask 9 having an opening only in a channel portion, and a high-concentration channel implantation region 4 is formed deeply in a portion of the substrate where a channel is to be formed. . Then, FIG. 3 (b)
As shown in FIG. 7, a gate 1 is formed on a channel region 7 via an oxide film 8.

Next, as shown in FIG. 3C, a low-energy threshold control channel is formed by rotating and oblique ion implantation using a mask 11 having an opening over the entire element region (no mask is required if the device is not CMOS). Perform injection. Thus, a high-concentration channel implantation region 4 is formed in a shallow portion of the entire surface of the channel region 7.

Finally, source / drain ion implantation is performed on the channel region 7 excluding the gate 1 by using the mask 11 in which the entire surface of the channel region 7 is opened (a mask is unnecessary in the case of non-CMOS). To form a bond.

The manufacturing process shown in FIG. 3 is a method that does not use the mask of FIG. 2B. In this step, since the same mask is used in FIGS. 3C and 3D, the number of PR steps can be reduced by one compared with the step of FIG. In the step of FIG. 3, during the processes (a) to (c), since the crystal is not recovered by annealing, the disorder of the crystallinity of the channel portion becomes larger than that of the other portions. Is promoted, and the impurity implanted in FIG. 3C is easily diffused into the channel portion.

(Embodiment 2) FIG. 4 is a sectional view showing Embodiment 2 of the present invention.

As shown in FIG. 4, the high-concentration channel injection region 4
Is the depth D ₁ of the channel portion and the depth D 2 of the source ₂
And the high-concentration channel injection region 4 at the drain 3 is formed only in a portion shallower than the junction of the drain 3. With this structure, the substrate concentration at the junction of the drain 3 is low, and the capacitance at this portion is reduced. However, the capacitance between the source 2 and the substrate 5 is the same as that of the conventional MOSFET.
As with T, this capacity acts as a stabilizing capacity. Further, in this method, when the channel implantation mask is shifted to the drain side with respect to the gate 1, the threshold voltage hardly changes, and only when shifted to the source side, the substrate impurity concentration below the gate decreases. And the threshold value fluctuates. For this reason, compared with the conventional method of FIG.
The probability that the threshold changes will be １ ／. The manufacturing process of this structure is as follows.

In order to manufacture the MOS transistor shown in FIG. 4, as shown in FIG. 5A, high-energy channel ion implantation is performed by using a mask 9 having an opening only in the channel portion, so that the channel of the substrate is formed. A high-concentration channel injection region 4 is formed in a portion where the substrate is to be formed to a depth of the substrate. Next, FIG.
As shown in FIG. 2B, using a mask in which the entire surface of the channel region 7 is opened (a mask is unnecessary for a non-CMOS).
A low energy threshold control channel implantation is performed. Thus, a high-concentration channel implantation region 4 is formed in a shallow portion of the entire surface of the channel region 7.

As shown in FIG. 5C, the gate 1 is formed, and the source / drain ions are implanted by using a mask 9 having an opening in the entire surface of the channel region 7 (no mask is required if not CMOS). A junction between the source 2 and the drain 3 is formed.

FIG. 6 is a process chart showing another embodiment of the method for manufacturing the MOSFET shown in FIG. As shown in FIG. 6A, using a mask 9 in which only the channel portion is opened,
High-energy channel ion implantation is performed to form a high-concentration channel implantation region 4 deep into the substrate at a portion of the substrate where a channel is to be formed. Thereafter, a gate 1 is formed as shown in FIG. As shown in FIG. 6C, using a mask 9 in which the entire surface of the channel region 7 is opened (CMOS
If not, a mask is not required), and low-energy threshold control channel implantation is performed by oblique ion implantation. Thus, a high-concentration channel implantation region 4 is formed in a shallow portion of the entire surface of the channel region 7. Finally, FIG.
As shown in FIG. 7, a mask 9 having an opening on the entire surface of the channel region 7
(A mask is not required for a non-CMOS device) to perform source / drain ion implantation to form a source / drain junction.

[0031]

As described above, according to the present invention, the MOS
The transistor can be operated at high speed by reducing the junction capacitance of the source / drain or drain of the FET. In addition, since shallow channel implantation that has a large effect on the threshold is performed over the entire element region, a change in threshold voltage due to a positional shift between the channel implantation mask and the gate mask can be suppressed. Further, when only the junction capacitance of the drain portion is reduced, the capacitance between the source and the substrate is not different from that of the conventional MOS transistor.
Therefore, when the source is used as a power supply or ground terminal and the drain is used as a signal terminal, the capacity of the signal line becomes small and high-speed operation becomes possible. Since it operates, the voltage drop of the voltage at the time of switching becomes small, and the speed does not decrease.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a process chart showing one embodiment of a method for manufacturing a MOS transistor according to Embodiment 1 of the present invention.

FIG. 3 is a process chart showing another embodiment of the method for manufacturing the MOS transistor according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a MOS transistor according to a second embodiment of the present invention.

FIG. 5 is a process chart showing one embodiment of a method for manufacturing a MOS transistor according to Embodiment 2 of the present invention.

FIG. 6 is a process chart showing another embodiment of the method for manufacturing the MOS transistor according to the second embodiment of the present invention.

7A is a diagram showing a conventional channel ion implantation method that does not limit the implantation range, and FIG. 7B is a device structure diagram.

8A is a diagram showing a conventional channel ion implantation method without limiting the implantation range, and FIG. 8B is a device structural diagram.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate 2 Source 3 Drain 4 High concentration channel injection region 5 Substrate 7 Channel region 8 Oxide film

Claims (3)

(57) [Claims] 1. A non-uniform channel-doped MOS transistor having a gate, a source, a drain, and a high-concentration channel injection region on a substrate, wherein the gate is formed on a part of a channel region in the substrate via an oxide film. The source and the drain are disposed on both sides of the gate and are buried in the channel region of the substrate, and the high-concentration channel implantation region is a channel region below the gate. If, it straddles the channel region where the source and drain are formed, which has been formed by injecting at different its depth, implantation depth of the high concentration channel injection region, gate <br / > heterogeneous channel you characterized in that the depth of the channel region in the channel region and the source portion of the bets downward is deeper than that of the channel region of the drain part doped MO
S transistor. 2. A channel including a high-energy ion implantation step and a low-energy ion implantation step, wherein a channel region is located below the gate, and a channel is formed by burying a source and a drain disposed on both sides of the gate. A method for manufacturing a non-uniform channel-doped MOS transistor that straddles a region and forms a high-concentration channel-doped region having a different depth, wherein the high-energy ion implantation step includes the step of: Ion implantation with high energy is performed in a channel region corresponding to the source portion, and a high-concentration channel implantation region is formed in the channel region under the gate.
The depth of the channel region and the source region in the channel region
It is a step of forming deeper than that in the channel region of the drain part , the low energy ion implantation step performs threshold energy control channel implantation with low energy in all the channel regions corresponding to the gate, source and drain, A method for manufacturing a non-uniform channel-doped MOS transistor, comprising a step of forming a shallow high-concentration channel implantation region at least in a channel region of a drain portion where ion implantation by high energy has not been performed. 3. A channel region having a high-energy ion implantation step and a rotating oblique ion implantation step, wherein a channel region located below the gate and a channel region formed by burying a source and a drain disposed on both sides of the gate. And forming a high-concentration channel-doped MOS transistor having a high-concentration channel-implanted region having different depths. The high-energy ion-implanting step comprises: a channel region corresponding to a gate portion, or a gate and a source. A high-concentration channel implantation region is formed in the channel region corresponding to the high-concentration ion implantation by ion implantation with high energy .
The depth of the channel region and the source region in the channel region
This is a process in which the drain region is formed deeper than that in the channel region . In the rotation oblique ion implantation process, the gate laminated on a part of the channel region is used as a mask, and a threshold due to low energy is applied to the channel region excluding the gate. Manufacturing a non-uniform channel-doped MOS transistor, wherein a high-concentration channel-implanted region is formed at least in a channel region of a drain portion where a control channel is implanted and ion implantation with high energy is not performed. Method.