JPH07325792A - Cpu monitoring device - Google Patents

Abstract

PURPOSE:To simply constitute a monitoring device monitoring the operation of each CPU in a system composed of plural CPUs. CONSTITUTION:A 2-port RAM 3 which is asynchronously accessed by a master CPU 1 and a slave CPU 2 is provided with a master CPU counter and a slave counter. The master CPU 1 monitors the value of the counter counted by the slave CPU 2 and the slave CPU 2 monitors the value of the counter counted by the master CPU 1. When the value of the counter is the same as the value at the time of the previous monitoring, the CPU abnormality counter provided on a self-CPU is counted up, and when a count value reaches a prescribed value or more, the corresponded opposite CPU is decided as an abnormality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU monitoring device for monitoring the operating status of each CPU in a system having a plurality of CPUs.

[0002]

2. Description of the Related Art This type of CPU monitoring device is shown in FIG.
It is used in the system shown in. That is, in FIG. 6, 1 is a master CPU, 2 is a slave CPU under the control of the master CPU, 3 is accessible by the master CPU 1 and the slave CPU 2, and each CPU stores data to be passed to the other CPU mutually. 2-port RAM
Is. The 2-port RAM 3 is a memory that has access ports for two systems, A system and B system, in which each CPU can write and read data independently and asynchronously.

Reference numeral 6 is a watch dog timer (Watch Dog Tim) for monitoring the operation of the master CPU 1.
er; WDT) circuit, which is connected to the slave CPU 2. A WDT circuit 7 monitors the operation of the slave CPU 2 and is connected to the master CPU 1. That is, each WDT circuit 6 and 7 corresponds to each corresponding CPU 1,
2 is a circuit that detects an abnormal state when the operating state or signal of No. 2 is monitored and does not change over a predetermined time, and when the abnormal state is detected, the other CPU
An abnormal signal is output to.

In the system configured as described above, when the master CPU 1 attempts to transfer data to the slave CPU 2, first, it is determined whether or not an abnormal signal is output from the WDT circuit 7 which monitors the operating state of the slave CPU 2. Or detect. If no abnormal signal is output from the WDT circuit 7, the slave CPU 2 is considered to be operating normally, and the master CPU 1 writes the data to the 2-port RAM 3. In this case slave CPU2
Is a WDT circuit 6 that monitors the operating state of the master CPU 1.
It is detected whether or not an abnormal signal is output, and if the abnormal signal is not detected, the data written in the 2-port RAM 3 is read and a corresponding process is executed. In this way, the data transfer from the master CPU 1 to the slave CPU 2 is completed.

Further, the slave CPU 2 is the master CPU 1
Similarly, in the case of transferring data, it is similarly detected whether or not an abnormal signal is output from the WDT circuit 6, and if the abnormal signal is not output, it is considered that the master CPU 1 is operating normally, and the data is transferred. Write to 2-port RAM3. The master CPU 1 monitors the operation of the slave CPU 2 in response to the data writing of the slave CPU 2.
If the abnormal signal is not detected after checking whether the abnormal signal is output from the DT circuit 7, the 2-port RAM
Read the data written in 3.

Any one of the CPUs during such data transfer
If an abnormal signal is output from the corresponding WDT circuit to the partner CPU that is operating normally, the C
The PU stops the data transfer.

[0007]

In such a system, WDT circuits for monitoring the CPUs are required for the number of CPUs. Therefore, when the system is composed of many CPUs, the circuit configuration becomes complicated. However, there is a problem that the system cannot be configured at low cost.

Therefore, it is an object of the present invention to simplify a monitoring device for monitoring the operation of each CPU in a system including a plurality of CPUs and to reliably monitor the operation of each CPU.

[0009]

In order to solve such a problem, the present invention provides a two-port RAM which can be asynchronously accessed from two systems, a first and a second system, and a second system RAM. First and second CPUs of a system having a first CPU provided and a second CPU provided in a second system
In the CPU monitoring device that monitors the operation of the
A first counter counted by U and a second CP
2 port R with a second counter counted by U
In addition to the AM, the first monitoring means for monitoring the value of the second counter is provided in the first CPU, and the second monitoring means for monitoring the value of the first counter is provided in the second CPU. It is a thing. Further, the first and second monitoring means, if the value of the counter to be monitored is the same as that at the time of the previous monitoring, the own CPU
If the count value is greater than or equal to a predetermined value, the corresponding CPU
Is determined to be abnormal. Further, a plurality of first and second CPUs arranged in the first and second systems are provided.

[0010]

The first CPU monitors the value of the second counter counted by the second CPU, and the second CP
U monitors the value of the first counter counted by the first CPU. As a result, the correctness of the operation of the partner CPU can be mutually monitored via the first and second counters. If the value of the monitored counter is the same as the value at the previous time of monitoring, the value of the CPU abnormality counter provided in the own CPU is incremented, and when the count value reaches a predetermined value or more, the corresponding partner CPU is determined to be abnormal To do. As a result, since the CPU is determined to be abnormal only after the abnormal state of the CPU continues for a predetermined time, it is possible to accurately determine the abnormality of the CPU. Also, a plurality of first and second CPUs are provided, and each CPU has a 2-port R
Each counter provided corresponding to AM is counted respectively. As a result, the values of the counters are
The present invention can be applied to a large-scale system composed of many CPUs, since the abnormality can be detected by monitoring by.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a system to which the CPU monitoring device according to the present invention is applied, and a WD for monitoring the operation of each CPU from the configuration of the conventional system shown in FIG.
The T circuits 6 and 7 are deleted to simplify the circuit configuration. Also, CPU abnormality counters 8 and 9 described later are provided in the internal RAM of each CPU.

Next, FIG. 2 is a diagram showing a memory configuration of the 2-port RAM 3 shown in the embodiment of FIG. In FIG.
The address a of the 2-port RAM 3 is used as a counter of the master CPU 1, and the area after the address a + 1 is used as a data storage area from the master CPU 1 to the slave CPU 2. Further, the address b is used as a counter of the slave CPU 2, and the area after the address b + 1 is from the slave CPU 2 to the master C.
It is used as a data storage area in PU1.

Here, the master CPU counter 4 provided at the address a of the 2-port RAM 3 is the master CPU 1
When the operation is normal, the master CPU 1 counts up, and this value is detected by the slave CPU 2 to monitor whether the operation of the master CPU 1 is correct. Also, 2
Slave CP provided at address b of port RAM3
The U counter 5 is counted up by the slave CPU 2 when the operation of the slave CPU 2 is normal, and this value is detected by the master CPU 1 and detected.
The correctness of the operation of is monitored.

By providing the master CPU counter 4 and the slave CPU counter 5 in the 2-port RAM 3 as described above, the respective CPUs are able to communicate with each other through the respective counters.
It is possible to monitor the operation of the PU, and thus to monitor the operation of each CPU from the conventional system configuration shown in FIG.
The DT circuits 6 and 7 can be omitted.

FIG. 3 is a flow chart showing the operation of the master CPU 1 or the slave CPU 2 which mutually monitors the operation of the partner CPU using the respective counters 4 and 5 provided in the 2-port RAM 3. An example of the operation of the master CPU 1 that monitors the operation of the slave CPU 2, which is the other CPU, will be specifically described based on this flowchart. When power is supplied to the master CPU 1 and the slave CPU 2 constituting the system and the system is activated, step ST
At 1, the master CPU 1 first clears the above-mentioned CPU abnormality counter 8 provided in the internal RAM of its own CPU for monitoring the abnormality of the partner CPU.

Before reading the transfer data from the slave CPU 2 from the 2-port RAM 3, the master CPU 1
Determines whether the slave CPU 2 is normal. That is, in step ST2, the slave CPU counter 5
Is read, and it is determined in step ST3 whether or not this counter value is the same as the previous value. Slave C here
If the value of the PU counter is not the same as the previous value, it is considered that the slave CPU 2 is operating normally, and the data at address b + 1 and subsequent addresses shown in FIG. 2 of the 2-port RAM 3 set by the slave CPU 2 in step ST4 is read. At the same time as writing to a memory not shown, step S
At T5, the value of the master CPU counter 4, which is its own counter, is incremented by one. Then, the transfer data for the slave CPU 2 is written in a predetermined area of the 2-port RAM 3 in step ST6, and the data transfer process is completed.

If the value of the slave CPU counter 5 is the same as the previous value and it is determined "YES" in step ST3, it is determined that the slave CPU 2 is not operating normally. In this case, it is determined in step ST7 whether or not the counter value of the CPU abnormality counter 8 for monitoring the slave CPU 2 is equal to or larger than the predetermined value n, and if this is "NO", this CPU abnormality counter is determined in step ST8. The value of 8 is incremented by 1, and the process returns to step ST2.

That is, when the value of the slave CPU counter 5 is the same as the previous value and the value of the CPU abnormality counter 8 provided in the own CPU for monitoring the slave CPU 2 is less than or equal to a predetermined value, the master CPU 1 Is slave C
It is judged that PU2 is not operating normally and the slave CP
The CPU error counter is incremented by 1 without reading the transfer data from U2. If the operation of the slave CPU 2 returns to normal, the slave CPU 2 also counts up its own counter 5 just like the master CPU 1 counts up its own counter 4 in step ST5, and as a result, the determination in step ST3 is made. It should be "NO".

However, if the slave CPU 2 is still in an abnormal state, the slave CPU counter 5 is not counted up, so this value holds the same value. Therefore, as a result of the determination of "YES" in step ST3, step S3
The judgment of "CPU abnormality counter> n) of T7 is" YES ".
Until the CPU abnormality counter 8 in the master CPU 1
Are sequentially incremented by the master CPU 1. As a result, when the value of the CPU abnormality counter 8 becomes equal to or larger than the predetermined value n and it is determined to be "YES" in step ST7,
In step ST9, the master CPU 1 determines the abnormality of the partner CPU, that is, the slave CPU 2, and finishes the data transfer process.

As described above, since the slave CPU 2 is determined to be abnormal for the first time when the abnormal state of the slave CPU 2 continues for a predetermined time (corresponding to n counts of the CPU abnormality counter 8), the abnormality of the partner CPU is accurately identified. Can be determined. In addition, in the present embodiment, the slave C is confirmed by checking whether the operation of the slave CPU 2, which is the partner CPU, is correct.
Although the operation of the master CPU 1 that fetches the transfer data from the PU 2 has been described, the operation of the slave CPU 2 is exactly the same. In this case, the partner CPU is the master C 1.
It becomes PU1. As a result, it is possible to mutually monitor the counter value of the other party to judge whether the operation of the other CPU is correct or not. Therefore, the WDT circuit conventionally provided for mutually monitoring the operation of the other CPU becomes unnecessary, and The monitoring device that monitors the operation of the CPU is simplified, and the operation of each CPU can be reliably monitored.

Next, FIG. 4 is a block diagram showing another embodiment of the present invention, in which the above-mentioned 2-port RAM 3 has a slave CP.
A plurality of U2 are connected. That is, 2-port RA
Connect the master CPU1 to one side of M3 and
A plurality of slave CPUs 21 on the other side of the port RAM 3
Configure to connect ~ 2n. And 2 port RA
M3 is configured as shown in FIG. That is, the master CP
U1 is the master CPU counter 4 and its transfer data area, slave CPU 21 is the slave CPU counter 51 and its transfer data area, and slave CPU 22 is the slave CPU counter 52.
And a transfer data area thereof, each CPU is provided with a counter and a transfer data storage area.

The master CPU 1 and a plurality of slave CPUs 21 to 2n are connected via the 2-port RAM 3 constructed as described above.
By connecting with the master CPU 1, the master CPU 1 accesses the slave CPU counters 51 to 5n to access each counter 5
It is determined whether or not the values of 1 to 5n are the same as the previous values, and when the same value continues for n counts of the CPU abnormality counter 8, the corresponding slave CPU is determined to be abnormal. Then, in this case, control is performed so that the transfer data of the slave CPU is not captured. Also, each slave CPU 21 to 2n is a master C in the 2-port RAM 3.
The PU counter 4 is accessed to detect whether this value is the same as the previous value, and when the same value continues for n counts of each CPU abnormality counter 9, the master CPU 1 is determined to be abnormal. Then, in this case, the transfer data of the master CPU 1 is not taken in.

Even when a plurality of slave CPUs are provided in this way, by providing a corresponding counter in the 2-port RAM 3, it is possible to similarly monitor the counterpart CPUs via this counter. Also, when a plurality of master CPUs are provided, it is possible to similarly confirm the operations of the other CPUs via the two-port RAM 3 and to further confirm the master CP.
The same applies when a plurality of U and slave CPUs are provided. As a result, the present invention can be applied to a large-scale system including many CPUs.

[0024]

As described above, according to the present invention, the first CPU monitors the value of the second counter counted by the second CPU, and the second CPU operates by the first CPU. Since the value of the counted first counter is monitored, the correctness of the operation of the partner CPU can be mutually monitored via the first and second counters, and therefore the WDT circuit conventionally provided can be omitted. Therefore, the circuit can be configured simply and the abnormality of the CPU can be accurately detected. If the value of the monitored counter is the same as the value at the previous time of monitoring, the value of the CPU abnormality counter provided inside the own CPU is incremented, and when the count value exceeds a predetermined value, the corresponding partner CPU
Since the CPU is determined to be abnormal, the CPU is determined to be abnormal only after the abnormal state of the CPU continues for a predetermined time, and therefore the abnormality of the partner CPU can be accurately determined. Further, since a plurality of first and second CPUs are provided, and each CPU counts each counter provided corresponding to the 2-port RAM, the value of each counter is monitored by the other CPU and the other CPU is monitored. Since a CPU abnormality can be detected, many C
It can be sufficiently applied to a large-scale system configured by PU.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a system to which a CPU monitoring device according to the present invention is applied.

FIG. 2 is a 2-port R used in the system of the above embodiment.
It is a figure which shows the structure of AM.

FIG. 3 is a flowchart showing the operation of each CPU in the system of the above-described embodiment.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a 2-port RAM used in the system of the other embodiment.

FIG. 6 is a block diagram of a conventional system.

[Explanation of symbols]

1 master CPU, 2,21 ~ 2n slave CPU,
3 2-port RAM, 4 master CPU counter, 5,
51-5n slave CPU counter, 8,9 CPU
Anomaly counter.

Claims (3)

[Claims] 1. A two-port RAM that can be asynchronously accessed from two systems, a first CPU provided in the first system, and a second CPU provided in the second system. The first and second systems having a second CPU installed
In the CPU monitoring device for monitoring the operation of the CPU, a first counter counted by the first CPU and a second counter counted by the second CPU are provided in the 2-port RAM, and The second
The first CPU is provided in the first CPU, and the second CPU is provided in the second CPU to monitor the value of the first counter. CPU monitoring device. 2. The CPU monitoring device according to claim 1, wherein a CPU abnormality counter is provided inside each of the first and second CPUs, and the values of the counters monitored by the first and second monitoring means are the previous values. If it is the same as when monitoring, the CPU abnormality counter provided in the own CPU is incremented, and if the count value is equal to or greater than a predetermined value, the corresponding partner C
A CPU monitoring device characterized by determining that a PU is abnormal. 3. The CPU monitoring device according to claim 1, wherein the first and second CPs are arranged in the first and second systems.
A CPU monitoring device, wherein a plurality of Us are provided and a counter that is counted by each CPU is provided in the 2-port RAM corresponding to each CPU.