JP3624051B2 - Information processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a highly reliable information processing apparatus that detects a failure and performs necessary disconnection processing by connecting at least two processing devices (processors) via a bus and simultaneously executing the same processing.
[0002]
Currently, information processing devices are widely used in various fields, and failure of information processing devices has a significant social and economic impact. For this reason, there is a need for an information processing device with high fault tolerance that can replace a failed processing device and continue processing without stopping the entire processing device when a failure occurs.
[0003]
[Prior art]
FIG. 7 shows an example of a conventional highly reliable information processing apparatus.
The processing devices 10-1 to 10-3 are connected by a bus 40 and simultaneously execute the same processing. The processing results flowing in the bus 40 are compared, and if the processing results do not match, it is determined that there is a failure. In particular, when there are three or more processing devices, a processing device that gives a processing result that does not match the processing results of other processing devices is detected as a failure by the majority logic of the processing results, and the processing device is connected to the bus 40. Disconnect from.
[0004]
In order to detect this failure, specifically, for example, the processing device 10-1 becomes a master, and the processing results are compared in the following procedure.
First, each processing device 10-1 to 10-3 inputs processing request data flowing in the bus 40 ((1) in FIG. 7), and simultaneously executes the data processing requested by each processing circuit 80 (FIG. 7). 7 (2)). Data output to the bus 40 is performed only by the processing device 10-1 serving as a master. When the processing device 10-1 serving as the master sends the data processing result to the bus 40 ((3) in FIG. 7), the other processing devices 10-2 and 10-3 send their processing results to their own devices. Is input to the failure detection circuit 70.
[0005]
On the other hand, the processing circuit 80 of the processing devices 10-2 and 10-3 outputs the processing result for the previous data input to the failure detection circuit 70 of its own device without flowing it to the bus 40 ((3) in FIG. 7). ).
[0006]
The failure detection circuit 70 in each of the processing devices 10-2 and 10-3 compares the processing result of the processing device 10-1 input from the bus 40 with the processing result processed by the own device, and sends and receives the comparison result to each other. ((4) in FIG. 7).
[0007]
As a result of comparing the processing results, if all the processing results match, it can be determined that all the processing apparatuses 10-1 to 10-3 are normal. If the comparison result by the failure detection circuit 70 of either one of the processing devices 10-2 and 10-3 does not match, the processing device 10-2 or the processing device 10-3 is in failure. If the comparison results by the failure detection circuit 70 of the processing devices 10-2 and 10-3 are not identical, it is determined that the processing device 10-1 has failed.
[0008]
The processing device determined to be faulty is automatically disconnected from the bus 40, and the processing by the simultaneous operation is continued by the remaining two processing devices.
[0009]
[Problems to be solved by the invention]
In the high reliability information processing apparatus as described above, since a plurality of processing apparatuses simultaneously perform the same processing operation, it has been impossible in the past to perform only a specific processing apparatus to perform a different processing operation. In addition, if a processing device is disconnected from the bus due to a failure, the processing device cannot be referenced, and the processing device that has recovered the failure is reconnected to the bus without stopping the entire information processing device. Recovery processing was difficult. Also, when testing or debugging failure detection to determine whether a failed processing device is automatically disconnected from the bus, all processing devices operate in the same way at the same time. There was a problem that it was difficult.
[0010]
In order to solve the above problems, the present invention enables a highly reliable information processing device to allow only a specific processing device to perform an operation different from the others, and even in a processing device separated from a bus, Make it possible to refer to specific registers from other devices, and when a new processing device is connected to the bus, information is transmitted to the other processing devices via the specific registers, and The purpose is to make the state coincide with the state of other processing devices that are currently operating at the same time, to operate them simultaneously, and to easily perform a failure detection test or the like.
[0011]
[Means for Solving the Problems]
FIG. 1 shows a configuration example of the present invention. In FIG. 1, 10 is a multiplexing unit composed of a plurality of processing devices, 10-1 to 10-n are processing devices that simultaneously execute the same processing in synchronization with the same clock, and 11 is assigned a different number for each processing device. Specific device number (unique device identifier), 12 is a common device number (common device identifier) in which the same number is given to all processing devices, 13 and 14 are requested by a comparison circuit, 20 is requested by a decoder and an arithmetic circuit, etc. Various processing circuits for performing the processed processing, 21 is a bus connection / disconnection means for disconnecting and connecting the own device from the bus, 22 is a decoder for decoding addresses of registers and memories, and 30 is a device connected to the bus. A bus connection register 31 for notifying other processing devices of whether or not it is disconnected from the bus, and 31 is a bus status record indicating the bus connection status of each processing device. 32, a handshake register for notifying whether data is ready when communicating with another processing device, and 33 is a data communication register for storing data to be communicated with the other processing device. , 40 represents a bus composed of a data line and a control signal line.
[0012]
In the first invention, each of the processing devices 10-1 to 10-n is assigned to each processing device with a unique device number 11 that is different for each processing device, and executes the same processing simultaneously with other processing devices. And a common device number 12 that is valid when When there is a request specifying a device number via the bus 40, the comparison circuits 13 and 14 compare whether the requested device number and the unique device number 11 / common device number 12 match, A response is returned to the bus 40 only if either matches.
[0013]
Apart from the unique device number 11 for each processing device, it has a common device number 12 that is valid when the processing devices are simultaneously executing the same processing, thereby allowing other processing devices (for example, input / output devices not shown) ), The processing devices in the multiplexing unit 10 operating at the same time appear as one processing device. Further, when a certain processing device fails, it is possible to access only that processing device by referring to the unique device number 11 unique to that processing device.
[0014]
Further, in the second invention, each of the processing devices 10-1 to 10-n has the bus connection / disconnection means 21, whereby the processing devices 10-1 to 10-n can be logically disconnected from the bus 40. . The processing device is disconnected from the bus 40 by writing, for example, “0” in the bus connection register 30. In response to the request specifying the unique device number 11, a response is returned even if the processing device having the unique device number 11 is disconnected from the bus 40. Therefore, by issuing a request designating the unique device number 11, necessary information can be acquired from the processing device even if the processing device is disconnected due to a failure.
[0015]
Furthermore, in the third invention, as a request specifying the unique device number 11 in the second invention, it is possible to refer to specific registers such as the bus status register 31, the handshake register 32, the data communication register 33, and the like. And That is, when the comparison result of the comparison circuit 13 indicates “match”, an instruction is given to the decoder 22 in the various processing circuits 20 and the value of the specific register requested from the decoding result is sent to the bus 40.
[0016]
In the fourth aspect of the invention, when a processing device disconnected from the bus 40 or a new processing device is connected to the bus 40, the bus connection / disconnection means 21 sets, for example, “1” in the bus connection register 30. Thus, it is possible to connect without stopping the operation of the multiplexing unit 10. At this time, there is provided means for transmitting information to other processing devices using the handshake register 32 and the data communication register 33.
[0017]
In the fifth aspect of the invention, there is provided means for connecting a processing device or a new processing device separated from the bus 40 to the bus 40 by the bus connection / disconnection means 21, and at this time, the own device is added. Means for notifying other processing devices. Specifically, when “1” is set in the bus connection register 30 and the fact that the own apparatus is connected is written, the value is reflected in the bus status register 31 of another processing apparatus via the bus 40. It has become. That is, the bus status register 31 always holds information indicating whether each processing apparatus is currently connected to the bus 40 or disconnected from the bus 40.
[0018]
In the sixth aspect of the invention, the various processing circuits 20 of the respective processing devices are connected to a specific register (for example, a register for data communication) of the own device when the own device is newly connected to the bus 40 and necessary initialization processing is completed. 33) means for notifying the other processing apparatus that the initialization process of the own apparatus has been completed by writing a value in 33).
[0019]
When a new processing device is connected instead of a processing device that has been disconnected due to a failure, the fact that the processing device is connected is notified. At this time, since the status of the connected processing device is different from the status of the currently operating processing device, communication is performed between the currently operating processing device and the connected processing device, and the status matches. The procedure to make is necessary. According to the fifth and sixth inventions, the process of matching this state can be performed while the multiplexing unit 10 is operating. When the procedure for matching the states is completed, the connected processing device is set to the same operation as the currently operating processing device, and the failure detection operation by the entire processing device is resumed.
[0020]
In the seventh invention, means for referring to a processing device by designating a unique device number in a state where the processing devices in the multiplexing unit 10 are simultaneously performing the same processing operation, and designated for the reference. Since only the processing device having the unique device number 11 that matches the unique device number responds, only the responding processing device is different from the other processing devices from the state in which the processing devices are simultaneously performing the same processing operation. Means for performing the operation, and means for automatically disconnecting the processing device from the bus 40 when the processing device performs another operation.
[0021]
By referring to the device number inherent to the processing device and intentionally shifting the operations of the processing devices performing the same processing at the same time, it becomes possible to easily perform a failure detection test for the processing device.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 is a diagram showing an example of a bus configuration and a packet in the embodiment of the present invention.
[0023]
As shown in FIG. 2A, for example, the bus 40 shown in FIG. 1 includes a 64-bit data line 40a and n bus connection state signal lines 40b (n is the number of processing devices in the multiplexing unit 10). And other control signal lines 40c. Other control signal lines 40c include, for example, a signal line indicating whether or not each processing device is mounted, a signal line indicating whether or not each processing device is operating simultaneously, and the like. The bus connection state signal line 40b is a signal line for connecting the bus connection register 30 and the bus state register 31 of each processing device to each other.
[0024]
As data flowing through the data line 40a, there are a request packet as shown in FIG. 2B and a response packet as shown in FIG. The request packet includes a command indicating a request type such as a read request and a write request, a requesting device number (unique device number 11 or common device number 12), a register or a memory to be read or written, and the like. It consists of an address and write data when the request is a write. The response packet includes a reply type indicating a response, a device number, read data when the request is a read, and the like.
[0025]
FIG. 3 shows a detailed configuration of the processing apparatus according to the embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIG. 1 correspond to those shown in FIG. 1, 15 is a gate circuit, 50 is a request address in a request packet, 51 is a simultaneous operation signal indicating simultaneous operation, 52 Is a memory in the processing device, 53 and 54 are bidirectional buffers, and 55 is a device number in the request packet.
[0026]
In this example, it is assumed that three processing devices 10-1 to 10-3 constitute a multiplexing unit. “01” is given as the unique device number of the processing device 10-1, “10” is given as the unique device number of the processing device 10-2, and “11” is given as the unique device number of the processing device 10-3. By giving the unique device number from the outside, the structures of the processing devices 10-1 to 10-3 can be made common. Here, a signal generation circuit having a unique device number corresponding to each slot is provided so that these numbers “01” to “11” are automatically determined by, for example, a slot into which a board on which each processing device is mounted is inserted. It is provided outside.
[0027]
On the other hand, the common device number is given “00” in common to the processing devices 10-1 to 10-3. This common device number is valid only when the input of the simultaneous operation signal 51 by the gate circuit 15 is valid.
[0028]
When there is a request to access the internal resources of the processing devices 10-1 to 10-3 by the device number 55 in the request packet, the comparison circuit 13 detects that the device number 55 matches the unique device number. Or the comparison circuit 14 detects that the device number 55 matches the common device number, and the response to the request is returned only when the simultaneous operation signal 51 is valid and the gate circuit 15 is open.
[0029]
In accordance with instructions from the various processing circuits 20, the bidirectional buffers 53 and 54 can be controlled to disconnect the processing device from the bus 40. Each processing circuit 20 has a decoder and receives the setting of the bus connection register 30 to determine whether or not to disconnect the processing device from the bus 40 at normal times. However, even in the disconnected state, if the requested device number 55 matches the unique device number of the own device, the registers 31 to 33 (except for the bus connection register 30) are referred to via the bidirectional buffer 54. And respond.
[0030]
The handshake register 32 and the data communication register 33 are registers that can be arbitrarily referred to and written in values from other processing devices. These registers 32 and 33 are used for exchanging information with a set of processing devices operating simultaneously with the added processing device when another processing device is added instead of the processing device separated due to a failure. Is done.
[0031]
FIG. 4 is an explanatory diagram of bus connection / disconnection in the embodiment of the present invention.
The processing devices are disconnected from the bus 40 by setting the bus connection register 30 of each processing device. For example, when the value of the bus connection register 30 is “1”, the bus is connected, and when it is “0”, the bus is disconnected. As shown in FIG. 4A, the signal of the bus connection register 30 is notified to the bus state register 31 of another processing device via the bus connection state signal line 40b.
[0032]
As shown in FIG. 4B, the bus state register 31 holds information on the bus connection / disconnection state from the bus connection register 30 of each processing device. Each processing device can determine the processing device connected to the bus 40 from the bus status register 31.
[0033]
FIG. 5 shows a communication processing flow when a processing device is newly added to a processing device performing simultaneous operation.
For example, it is assumed that two of the processing devices 10-1 to 10-3 shown in FIG. 3 are operating simultaneously, and a new processing device is added after one is disconnected due to a failure. The newly added processing device first performs internal initialization upon connection to the bus (S20 in FIG. 5), and sets "1 (bus connection)" in the bus connection register 30 when the initialization is completed. (S21). As a result, the bus connection state signal line 40b described in FIG. 4 notifies the connection state to the bus state register 31 of the existing simultaneously operating processing device.
[0034]
When the existing processing device confirms the insertion of a new processing device by the bus state register 31 in the time waiting (S10) state (S11), the handshake register 32 and the data communication register 33 of the newly connected processing device. Use to start communication.
[0035]
The handshake register 32 and the data communication register 33 can read and write values set from a new processor and an existing processor. Here, if the initial value of the handshake register 32 is “0”, the handshake register 32 is read to confirm that the value is “0” (S12, S13), and then the new processing device A command of a predetermined format is written to the data communication register 33 (S14), and the handshake register 32 is set to "1" (S15).
[0036]
The new processing device waits for “1” to be set in the handshake register 32 by the existing processing device, and confirms that it has become “1” (S22, S23). Read (S24). Then, the received command read from the data communication register 33 is analyzed and executed (S25). When notifying the existing processing apparatus of the execution result, the information to be notified is written in the data communication register 33 (S26), and "0" is set in the handshake register 32 (S27). Thereafter, the process returns to step S22 and waits for the handshake register 32 to become “1”.
[0037]
The existing processor sets “1” in the handshake register 32 (S15), waits for it to change to “0” (S16, S17), and confirms that it has become “0”. If so, the data communication register 33 is read to read the data written by the new processing device (S18), the received data is analyzed, and the necessary processing is executed (S19). The above sequence is repeated a predetermined number of times until the setting of the new processing device is completed and the new processing device and the existing processing device are in the same state.
[0038]
By communicating via the data communication register 33, it is possible to notify system environment information (for example, information on connected input / output devices, information on memory capacity, etc.) from an existing processing device to a new processing device.
[0039]
FIG. 6 is a diagram for explaining a failure test for confirming that a processing device is disconnected from the simultaneous operation when an arbitrary processing device among the processing devices performing the simultaneous operation performs another operation. is there.
[0040]
In the present invention, it is possible to simply perform a failure test for confirming whether or not the processing device is disconnected from the simultaneous operation by causing a pseudo failure state as follows. In the failure test, first, as shown in FIG. 6A, a predetermined failure test program 61 is loaded into the memories 52 of all the processing apparatuses 10-1 to 10-3 according to an instruction from the console 60 connected to the bus 40. Then, the failure test program 61 is simultaneously executed by all the processing devices 10-1 to 10-3.
[0041]
The processing flow is shown in FIG. In this example, it is assumed that the processing apparatus having the unique apparatus number “01”, that is, the processing apparatus 10-1 is put into a pseudo failure state. By changing the value of the unique device number, other processing devices can be brought into a failure state and disconnected.
[0042]
When there is a request for reference with the unique device number “01” via the bus 40 (S30, S31), the processing device 10-2, 10- is compared with the unique device number of its own device in each processing device (S32). 3 executes the processes of S32 to S34, and the processing apparatus 10-1 executes the processes of S35 to S37.
[0043]
That is, since the requested unique device numbers are different from the unique device numbers of the own devices, the processing devices 10-2 and 10-3 continue normal simultaneous operation without responding to the request (S32). . On the other hand, since the unique device numbers match, the processing device 10-1 operates differently from other processing devices by responding to the request (S35).
[0044]
When the processing device 10-1 executes processing different from the others, a mismatch occurs due to operation comparison with the processing devices 10-2 and 10-3 operating simultaneously, and the failure detection circuit 70 causes the processing device 10- 1 is considered to have failed. The failure detection logic of the failure detection circuit 70 is the same as that of the prior art described with reference to FIG. When the processing device 10-1 is regarded as a failure, the processing device 10-1 is automatically detached from the simultaneously operating processing devices.
[0045]
The processing devices 10-2 and 10-3 confirm that the processing device 10-1 having the unique device number “01” has been disconnected by the bus status register 31 shown in FIG. S33). The confirmed result is written in a predetermined area of the memory 52 and logged (S34).
[0046]
On the other hand, the processing device 10-1 confirms that it has been disconnected by means of a register or the like set by the failure detection circuit 70 (S36), and similarly, a predetermined area of the memory 52 in the own processing device 10-1. The confirmation result is written in and logged (S37).
[0047]
Later, by reading the logging information collected in the memory 52 of each of the processing devices 10-1 to 10-3 from the console 60, it is checked whether or not the processing device 10-1 with the unique device number “01” is surely disconnected. Thus, the failure detection operation can be verified.
[0048]
【The invention's effect】
As described above, according to the present invention, in an information processing apparatus that improves the reliability of the entire processing apparatus by causing two or more processing apparatuses to execute the same process simultaneously, it is common to all the processing apparatuses operating simultaneously. In addition to assigning the device number, and assigning a unique device number to each individual processing device, the processing device in which the failure has occurred can be easily identified.
[0049]
In addition, since communication can be performed with a processing device disconnected from the bus, information on the processing device that is currently operating simultaneously is notified to the processing device to be connected instead of the failed processing device. Therefore, the connected processing device is set to the same state as the currently operating processing device, and the failure detection operation by the entire processing device can be resumed without stopping the entire information processing device, so that fault tolerance can be improved. become.
[0050]
In addition, it is possible to easily perform a test for detecting a failure of a processing device by deliberately shifting the operation of the processing device performing the same processing at the same time with reference to the device number inherent to the processing device. .
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of the present invention.
FIG. 2 is a diagram illustrating an example of a bus configuration and a packet in the embodiment of the present invention.
FIG. 3 is a diagram showing a detailed configuration of a processing apparatus according to an embodiment of the present invention.
FIG. 4 is an explanatory diagram of bus connection / disconnection in the embodiment of the present invention.
FIG. 5 is a diagram illustrating a communication processing flow when a processing device is newly added to a processing device performing simultaneous operation.
FIG. 6 is an explanatory diagram of a failure test in the embodiment of the present invention.
FIG. 7 is a diagram illustrating an example of a conventional highly reliable information processing apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Multiplexing units 10-1 to 10-n Processing device 11 Unique device number 12 Common device number 13 Comparison circuit 14 Comparison circuit 20 Various processing circuits 21 Bus connection / disconnection means 22 Decoder 30 Bus connection register 31 Bus state register 32 Handshake Register 33 Data Communication Register 40 Bus

Claims (7)

In an information processing apparatus having a function of comparing at least two processing devices connected via a bus, having these processing devices execute the same processing simultaneously in synchronization with the same clock, and comparing the results.
Each of the processing devices is
Means for holding a unique device identifier that is different for each processing device;
Means for holding a common device identifier which is given in common to each processing device and becomes effective when the same processing is executed simultaneously with other processing devices;
Means for comparing whether the unique device identifier or the common device identifier matches a request specifying a device identifier;
An information processing apparatus comprising means for responding to the request only when either the unique device identifier or the common device identifier matches. The information processing apparatus according to claim 1,
Means for logically separating the processing unit from the bus;
In response to a request specifying the unique device identifier, the processing device that holds the unique device identifier that matches the specified unique device identifier includes means for responding even when the own device is disconnected from the bus. An information processing apparatus characterized by the above. The information processing apparatus according to claim 2,
The information processing apparatus characterized in that the request specifying the unique apparatus identifier is a request for referring to a specific register provided in the processing apparatus. The information processing apparatus according to claim 3,
Means for connecting a processing device or a new processing device separated from the bus to the bus without stopping the operation of the information processing device;
Each of the processing devices includes a register for transmitting information to another processing device. The information processing apparatus according to claim 3,
Means for connecting a processing device or a new processing device separated from the bus to the bus without stopping the operation of the information processing device;
When the own device is newly connected to the bus, the processing device writes a value in a specific register of the own device, thereby reflecting the value in a register of another active processing device. An information processing apparatus comprising: means for notifying another processing apparatus of addition. The information processing apparatus according to claim 3,
Means for connecting a processing device or a new processing device separated from the bus to the bus without stopping the operation of the information processing device;
When the own device is newly connected to the bus and the initialization process is completed, the processing device writes the value to a specific register of the own device, thereby initializing the own device to another processing device. An information processing apparatus comprising means for notifying that the process has ended. The information processing apparatus according to claim 1,
Means for designating the unique device identifier and referring to the processing device in a state where the processing device is simultaneously performing the same processing operation;
Only the processing device that holds the unique device identifier that matches the specified unique device identifier responds to the reference, so that only the processing device that responded from the state where the processing device is performing the same processing operation at the same time Means for performing an operation different from the processing device of
An information processing apparatus comprising: means for separating the processing apparatus from the bus when the processing apparatus performs another operation.

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