JPH07312558A - Serial/parallel converter, parallel/serial converter and arithmetic processing unit - Google Patents

Abstract

PURPOSE:To prevent overwrite with simple circuit configuration by connecting a 1st serial parallel S/P conversion circuit and a 3rd S/P conversion circuit or a 2nd S/P conversion circuit and the 3rd conversion circuit differentially, receiving data of a group serially and outputting the data in parallel. CONSTITUTION:When switches UiA (i=1-3) of a 1st group and switches Uj (j=4-9) of a 3rd group are sequentially closed by a 1st read pointer, data being components of input data IN are latched sequentially in registers RiA and Rj. Similarly the data are sequentially delayed by 1st bit unit time delay elements H1B-H3B of a 2nd group and delayed by 1st bit unit time delay elements H4-H9 by a 2nd write pointer WPB. A 1st read enable signal REA and a 2nd signal REB are applied alternately in an alternate timing. Then the signal REA or REB is applied to a switch Tj via an OR circuit ORR, then data latched in the registers R4-R9 are outputted from an output terminal OUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel converter and a parallel / parallel converter used for digital processing of video signals.
The present invention relates to a serial converter and an arithmetic processing device having a serial / parallel converter and a parallel processor using the parallel / serial converter. In particular, the present invention relates to a serial / parallel converter, a parallel / serial converter, and a digital video signal processing device suitable for signal processing of video signals.

[0002]

2. Description of the Related Art First, a conventional serial / parallel converter will be described. FIG. 13 is a circuit configuration diagram of a conventional serial / parallel converter. This serial / parallel converter is, in this example, a 9-word serial / parallel converter, and includes nine registers R1 to R9 and nine 1-bit unit time delay elements H for delaying the write pointer WP.
1 to H9, nine switches U1 to U9 provided on the input side of the registers R1 to R9, and nine switches T1 to T9 provided on the output side of the registers R1 to R9. First, the basic operation of this serial / parallel converter will be described. The 1-bit unit time delay elements H1 to H9 are connected in series, and a 1-bit write pointer WP that sequentially energizes (turns on) the switches U1 to U9 is sequentially delayed by application of the input data IN. The elements H1 to H9 are delayed. The applied write pointer WP energizes the switch U1, and further, the write pointer WP sequentially delayed by the 1-bit unit time delay elements H1 to H8 sequentially energizes the switches U2 to U9. Data DAT forming input data IN
A1 to DATA9 are sequentially registered in the register Ri (i = 1 to 9)
Will be stored in. For example, when the input data IN is a video signal, each of the individual data DATA1 to DATA9 corresponds to pixel data in one frame (1H) forming the video signal, and these pixel data are stored in the register Ri. The write pointer WP is applied according to the application timing of the first pixel data of one frame, and the second
The 1-bit unit time delay elements H1 to H9 are delayed according to the input timing of the th pixel data. Data DATA1 to DATA9 (DA that compose the input data IN
TAi) is respectively stored in the register Ri, the write enable signal WE is applied to simultaneously activate the switch Ti provided on the output side of the register Ri to output the data DATAi stored in the register Ri as the output data. O
Output in parallel as UTi (i = 1 to 9). As a result, 9 pieces of data DATA1 to D input serially are input.
The input data IN composed of ATA9 is output as parallel output data OUT1 to OUT9, and serial / parallel conversion is performed.

The operation of the serial / parallel converter described above will be described in detail with reference to FIG. Data DATA11 to DAT constituting the first cycle input data IN
A19 is sequentially (serially) input. For example, when the input data IN is a video signal, individual data DA
Each of TA11 to DATA19 corresponds to pixel data for each frame forming a video signal. First data D
At the same time that the ATA 11 is input, the 1-bit write pointer WP is also input. Since the switch U1 is turned on by this write pointer WP, the first input data DA
TA11 is stored in the register R1. The write pointer WP is transferred to the first 1-bit unit time delay element H1 and delayed, and the switch U2 is turned on by the output write pointer WP. At this time, since the second data DATA12 is input as the input data IN, this input data DATA12 is stored in the register R2. Thereafter, the input data DATA13 to DAT are similarly processed.
A19 is stored in the registers R3 to R9. Register R
When outputting the data DATA1 to DAT9 stored in 1 to R9, the last data DATA of the input data IN
After storing 9, the write enable signal WE is applied. By applying this write enable signal WE, the switch T1
~ T9 (Ti) are turned on at the same time, and nine registers Ri
Nine data DATA stored in (i = 1 to 9)
1i is simultaneously output as nine pieces of parallel output data OUTi. However, here, in this parallel data output operation, the input of individual data of the input data IN is set to 1
When it is set as a cycle, it will take time for the three cycles. That is, correct data is output only when the data is continuously held in the register Ri (i = 1 to 9) for three cycles after the write enable signal WE is input.

The last data D of the input data IN in the second cycle and the first cycle
After three cycles from the application of ATA9, input data I
New data DATA21 to DATA29 forming N
Is entered. Switch U using the write pointer WP
1 to U9 are sequentially energized, and these data DATA21 to
The operation of storing DATA29 in the registers R1 to R9 is performed in the same manner as the operation of the first cycle. Then the first
Similarly to the cycle, the write enable signal WE is applied to the data DATA2 stored in the registers R1 to R9.
1 to DATA 29 are output in parallel. This parallel data output also takes time for three cycles.

If the first cycle data group DATA1
1 to the last input data DATA19 of DATA19,
When the time between the data group DATA21 to DATA29 of the second cycle and the first input data DATA21 is not longer than three cycles, the circuit configuration of this serial / parallel converter allows the serial / parallel conversion after the second cycle to be performed normally. I can't do it. The reason is data DATA
Even if the write enable signal WE is input immediately after all 11 to DATA 19 are stored in the registers R1 to R9,
It takes three cycles to output the parallel data, but within the three cycles, the first data DA of the second cycle is output.
This is because TA21 is input together with the write pointer WP, stored in the register R1 via the switch U1, and the data DATA1 stored until then is overwritten. That is, the register R1 is overwritten by the new data DATA21 before the data DATA11 stored in the register R1 is completely output.

When there is no timing margin between the input and the output and data arrives continuously in this way, the two-bank system has been used as a conventional means.
The two-bank method uses two serial / parallel converters alternately and avoids that the contents of the register are overwritten with new data at the timing of parallel output. That is,
The first serial data groups DATA11 to DATA19 are input to the first serial / parallel converter to perform parallel conversion, and the subsequent second serial data groups DATA21 to DATA21.
The DATA 29 is input to the second serial / parallel converter to perform parallel conversion. The subsequent third serial data group DATA31 to DATA39 is the first serial / DATA
The data is input to the parallel converter to perform parallel conversion, and then the fourth serial data group DATA41 to DATA4
The DATA 49 is input to the second serial / parallel converter for parallelization. The same applies thereafter. By doing so, when paying attention to each serial / parallel converter, there is a time margin of 9 cycles until the next data arrives. As a result, each serial / parallel converter can perform parallel conversion without being overwritten. However, such a two-bank system has a problem that the circuit scale is doubled.

Next, a conventional parallel / serial converter will be described. FIG. 15 is a circuit diagram of a conventional parallel / serial converter. This parallel / serial converter
In this example, it is a 9-word parallel / serial converter, and includes nine registers Q1 to Q9, nine 1-bit unit time delay elements G1 to G9 that sequentially delay the 1-bit read pointer RP, and registers Q1 to Q9. 9 switches S1 to S9 provided on the input side of, and 9 switches V1 to V9 provided on the output side of the registers Q1 to Q9. First, the basic operation of this parallel / serial converter will be described. 1-bit unit time delay elements G1 to G9
Are connected in series and sequentially delay the 1-bit read pointer RP that sequentially activates (turns on) the switches V1 to V9. When the write pointer WP is applied together with the input of nine pieces of parallel input data IN1 to IN9 forming the input data IN, the switches Si (i = 1 to 1) are input.
9) are turned on at the same time, and 9 parallel input data IN
1 to IN9 are simultaneously stored in the register Qi. When outputting the data stored in the register Qi, the 1-bit read pointer RP is applied and sequentially delayed by the 1-bit unit time delay elements G1 to G9. The read pointer RP sequentially and serially outputs the data stored in the register Qi as the output data OUT. Through the above operation, parallel / serial conversion is performed.

The operation of this serial / parallel converter will be described in detail with reference to FIG. In the first cycle, as nine pieces of parallel input data IN1 to IN9, nine pieces of first group parallel data DATA51 to DATA59
Are input together with the write enable signal WE. The switch Si is simultaneously turned on by the write enable signal WE, and the input data DATA51 to DATA5
9 is simultaneously stored in the register Qi. It is assumed that this storing operation takes 3 cycles. That is, if the write enable signal WE is not input for three cycles, the register Q
It is assumed that the data is not completely stored in i (i = 1 to 9). 3 from application of data DATA51 to DATA59
After the period, the read pointer RP is applied. As a result, the read pointer RP causes the first switch V1
Is turned on and the first input data DATA51 stored in the register Q1 is output as the output data OUT. The read pointer RP is delayed by the first 1-bit unit time delay element G1, and the delayed read pointer RP turns on the switch V2 and outputs the input data DATA52 stored in the register R2 as output data OUT. Thereafter, similarly, the input data DATA53 to DA
TA59 is serially output in sequence. 9 for this output operation
It takes a cycle.

After outputting the second cycle data DATA59, new second group data DATA61 to DATA69 are input over three cycles, and at the same time, the write enable signal WE is applied. As a result, as in the first cycle, the data DATA 61 to D
ATA9 is stored in the register Qi. After that, the read pointer RP is applied to serially output the data DATA61 to DATA69 stored in the register Qi.

If the data group DATA5 of the first cycle
1 to DATA59 and data group DATA6 of the second cycle
If there is not more than 9 cycles between 1 and DATA 69, parallel / serial conversion cannot be performed in this parallel / serial converter. Because the data DAT
A11 to DATA19 take three cycles to register Q1 to Q
Even if the read pointer RP is input immediately after being stored in 9, it takes time for 9 cycles to serially output the 9 data. This is because the register Q9 in which the data DATA59 is stored is overwritten. That is, the register Q9 is overwritten with the data DATA69 before the data DATA59 stored in the register Q9 is output.

When data comes continuously in this way, a two-bank system can be cited as a conventionally used means. This system uses two parallel / serial converters alternately to avoid overwriting with new data at the time of serial output. That is, the first data group DA
TA51 to DATA59 are input to the first parallel / serial converter for serial conversion, and subsequent second data groups DATA61 to DATA69 are input to the second parallel / serial converter for serial conversion. The third data groups DATA71 to DATA79 are input to the first parallel / serial converter to perform serial conversion, and the subsequent fourth data group DATA81 to DATA81.
The DATA 89 is input to the second parallel / serial converter to perform serial conversion. The same applies thereafter. By doing so, when paying attention to the respective parallel / serial converters, there is a time margin of 9 cycles or more between the input data groups. This allows parallel / serial conversion without overwriting. However, the circuit scale is 2 in the 2-bank method.
There is a problem that it will be doubled.

The above-mentioned serial / parallel converter and parallel / serial converter are preferably used, for example, as an input data buffer and an output data buffer of a digital video signal processing device. A configuration example of the digital video signal processing device will be described with reference to FIG.
This digital video signal processing device comprises a serial / parallel converter (S / P), a plurality of processor elements, and a parallel / serial converter (P / S). When the input data IN is a video signal, each processor element processes each pixel data in one frame of the video signal. That is, 1 processor element
It is provided as many as the number of pixels in the frame. In this example, it is assumed that there are nine pixels in one frame for the sake of illustration, and nine processor elements are provided. Input data IN is serially applied from the input terminal to the serial / parallel converter illustrated in FIG. 13, and the data stored in the register is applied to the processor element. Each of the nine processor elements has a memory and an arithmetic circuit and performs desired arithmetic processing.
The output of the nine processor elements is one horizontal period (1
The video signal corresponding to H) is output to the output terminal from the parallel / serial converter illustrated in FIG. In this digital video signal processing device, the data of each pixel of the video signal supplied to the serial / parallel converter every horizontal period (1H) is passed to the processor element within the subsequent horizontal blanking period. The input data passed to this processor element is processed during the next one horizontal period. Then, in the subsequent horizontal blanking period, the data processed in the processor element is written in the parallel / serial converter, and the data processed in the subsequent horizontal period (video signal) is taken out from the output terminal. In this way, for example, digital processing of the video signal is performed. In FIG. 17, one horizontal period (1H)
The data capacity for 9 minutes is set to 9, but this is for simplifying the illustration and is actually several hundreds to several thousands.

Assuming that the input data IN is a video signal, if the horizontal blanking period of the video signal is sufficiently long as in the case of the NTSC signal, parallelization / parallel / parallel / parallel / parallel conversion by the serial / parallel converter is performed within that period. The serialization in the serial converter can be processed with sufficient timing. However, for example, M illustrated in FIG.
Some video signals, such as USE signals, have extremely short horizontal blanking periods. In such a case, the horizontal blanking period is used to serial / parallel convert the data and input the parallel data to the processor element, or the data processed by the processor element is received and serialized by the parallel / serial converter. It is impossible to do at the timing. Because, as mentioned earlier, when the data comes continuously, due to the time constraint,
This is because serial / parallel conversion by the serial / parallel converter and parallel / serial conversion by the parallel / serial converter cannot be performed. Of course, the serial / parallel converter and the parallel / serial converter can be avoided by using the two-bank type, but this causes the circuit scale to become too large.

As a digital processing apparatus for video signals, for example, Jim Chiders, et al, "SVP: Serial Video Pro" is used.
cessor, Proceedings of the IEEE, 1990, Custom Integra
The device described in tedCircuits Conference, pp.17.3.1 to 17.3.4 "is known. The structure of the digital video signal processing device is shown in Fig. 18. This digital video signal processing device is composed of parallel processors. The parallel processor is a SIMD (Sigle Instruction Multiple D) in which M processor elements, which are the same as the number of data (pixel number) for one horizontal period = M, are provided in parallel.
ata: Single instruction multiple data processing) type processor. The SIMD method will be described later. The details of the digital video signal processing device illustrated in FIG. 18 will be described. The digital video signal processing device includes a shift register circuit 100,
It has a memory circuit 200, an arithmetic circuit 300, an address decode circuit 400, and a control circuit 500. As input data IN of the digital video signal processing device, a video signal consisting of M pixels is serially applied for one horizontal period. Each pixel data is composed of a plurality of bits.

The shift register circuit 100 functions as a serial / parallel mutual conversion circuit, and M 1-bit unit time delay elements G1 to G provided in series.
m, M 1-bit unit time delay elements H1 to Hm connected in series, M registers R1 to Rm, and 2M pairs of switch circuits provided before and after these M registers, for example, a pair of switches. It has a switch U1: S1 and a pair of switches V1: T1. The shift register circuit 100 functions as a serial / parallel conversion circuit as described later. The M 1-bit unit time delay elements G1 to Gm are
The read pointer RP is sequentially delayed. The read pointer RP is a pointer (control data) used to control the switches V1 to Vm in order to read the data stored in the registers R1 to Rm. The M 1-bit unit time delay elements H1 to Hm sequentially delay the write pointer WP. The write pointer WP includes registers R1 to R1.
A pointer used to energize (turn on) the switches U1 to Um for writing data to Rm. The video signal applied to the word (pixel) serial as the input data IN is activated by a switch activated based on the write pointer WP, for example, the switch U1 in the first stage, and the video signal is changed in the first stage. It is stored in the eye register R1. By sequentially performing this operation for the registers of the second and subsequent stages, the video signals applied in word serial are sequentially stored in the M registers R1 to Rm. Since the pixel data stored in the registers R1 to Rm are used in the arithmetic operation in the arithmetic circuit 300, the pixel data is temporarily stored in the M register R1.
~ Rm is transferred to the corresponding memory circuit 210, 220, 230, 240 provided in parallel in the memory circuit 200, and then the arithmetic circuit 310 provided in parallel corresponding to the memory circuit provided in parallel. 320, 330, 340
M memory circuits 210, 22 provided in parallel or directly from the registers R1 to Rm.
0, 230, 240 via the read bit line RB1. The transfer is performed by the address decoding circuit 400.
Applies read control data RW to the switches T1 to Tm to simultaneously energize the switches T1 to Tm. The address decoding circuit 400 applies the write control data WP to the switches S1 to Sm based on the calculation results of the calculation circuits 310, 320, 330 and 340 or the calculation results stored in the memory circuits 210, 220, 230 and 240. Then M
By simultaneously energizing the individual switches S1 to Sm, they are transferred to the registers R1 to Rm in the shift register circuit 100 via the write bit line WB1. The operation result transferred to the registers R1 to Rm is the read pointer R
By sequentially energizing the switches V1 to Vm based on P, the output data OUT is output.

The memory circuit 200 has M memory circuits 210, 220, 230 and 240 arranged in parallel. Each memory circuit, for example, the memory circuit 21
In this example, 0 is three-stage register R10, R11, R1.
2, switches T10, T11, T12 provided on the input side of these registers, and switches S10, S11, S provided on the output side of these registers.
12 and. Energization (ON) and deenergization (OFF) of the switches S10, S11, S12 are performed based on the word write signals WW0, WW1, WW2 from the address decoding circuit 400. Also, the switches T10, T11, T1
Energization and deactivation of 2 are performed based on word read signals RW0, RW1 and RW2 from address decode circuit 400. M read bit lines RBi (i = 1 to m)
Indicates a read bit line of the memory circuit 200,
When any one of the switches Ti in the shift register circuit 100 and the switches Ti0, Ti1, Ti2 in the memory circuit 200 is turned on, the shift register circuit 10 is turned on.
The data stored in the register Ri in 0 and the registers Ri0, Ri1 and Ri2 in the memory circuit 200 is called on the read bit line RBi. By controlling the switches described above, the register Ri in the shift register circuit 100 and the register Ri0 in the memory circuit 200,
The data stored in Ri1 and Ri2 is supplied to any of the corresponding arithmetic circuits 310, 320, 330, and 340. The M write bit lines WBi (i = 1 to m) represent the write bit lines of the memory circuit 200, and appropriately represent the switches Si in the shift register circuit 100 and the switches Si0, Si1, Si2 in the memory circuit 200. When either of them is turned on, the data on the write bit line WBi is transferred to the register Ri in the shift register circuit 100.
And registers Ri0, Ri1 in the memory circuit 200,
It can be stored in Ri2. That is, by controlling the above switches, the calculation result of the calculation circuit 300 can be stored in the register Ri in the shift register circuit 100 and the registers Ri0, Ri1, Ri2 in the memory circuit 200.

The arithmetic circuit 300 includes M arithmetic circuits 31.
0, 320, 330, 340. These arithmetic circuits can simultaneously operate in parallel. The control circuit 500 controls the control signal CTRL necessary for controlling the operation of the arithmetic circuit 300,
And the address signal A to the address decoding circuit 400.
Output DRS. The address decode circuit 400 decodes the address signal ADRS input from the control circuit 500 to generate the word read signal RW and the word write signal WW for the shift register circuit 100 and the word write signals WW0 to WW2 for the memory circuit 200. And word read signals RW0 to RW2.

In this digital video signal processing device, the shift register circuit 100 is provided every horizontal period of the video signal.
The data of each pixel for each frame (1H) of the video signal supplied to is written in the register in the memory circuit 200 in the subsequent horizontal blanking period. The data written in the memory circuit 200 is supplied to the arithmetic circuit 300 during the next one horizontal period, and the value arithmetically processed in the arithmetic circuit 300 is again written in the register in the memory circuit 200. Within the subsequent horizontal blanking period,
The data stored in the register of the memory circuit 200 is written in the register in the shift register circuit 100,
From the output terminal OUT, the video signal arithmetically processed in the arithmetic circuit 300 is taken out every horizontal period.

As described above, the digital video signal processing apparatus shown in FIG. 18 has SIMD (Sigle Instruction Multiple) having the same number (M) of processor elements as the number (M) of pixel data for one horizontal period of the video signal. Data)
The method is a parallel processor. Since the same arithmetic processing is often performed on all pixels in video signal processing, SIMD that gives the same processing instruction to all arithmetic circuits.
The method is sufficient and there is no inconvenience even if the same arithmetic processing is performed. The SIMD method requires only one control, which requires only one control circuit 500, which has the advantage of reducing the circuit scale of the digital video signal processing device.

The detailed operation and timing of the digital video signal processing apparatus shown in FIG. 18 will be described with reference to FIG. FIG. 19 is a diagram showing an operation in the shift register circuit 100 and an operation between the memory circuit 200 and the arithmetic circuit 300 in time series. The timing T1 video signal is word (pixel) serially applied as the input data IN applied to the digital video signal processing device within one horizontal period (1H) period (timing T1). At the same time that the first pixel data of the video signal is applied, a 1-bit write pointer WP is also applied, and this write pointer WP turns on (energizes) the first switch U1. As a result, the switch U1 is closed and the first pixel data of the video signal is stored in the register R1. The write pointer WP is applied to the 1-bit unit time delay element H1 and delayed. This delay time is set to the time when the next pixel data is input. The next pixel data is input at the next video signal transmission timing, but the write pointer WP that activates the switch U1 is set to 1
The switch U is output from the bit unit time delay element H1.
2 is energized to close the switch U2 and the next pixel data applied as the input data IN is stored in the register R2. Thereafter, similarly, the pixel data of the video signal is sequentially stored in the registers R3 to Rm in the memory circuit 200.
That is, a video signal for one horizontal period (1H) is stored in the registers R1 to Rm for each pixel (timing T in FIG. 19).
9).

[0021] In the timing T2 horizontal blanking period (timing T2),
Word read signal RW from address decode circuit 400
The switches T1 to T1 in the shift register circuit 100 are
Tm is activated, and at the same time, the word read signal RW0 is activated.
To RW2 activate any of switches Ti0 (i = 1 to m), Ti1 and Ti2 in the memory circuit 200. As a result, the pixel data stored in the register Ri in the memory circuit 200 is stored in the read bit line RB.
Corresponding arithmetic circuit (ALU) 310, 32 via i
0, 330, 340 and the respective arithmetic circuits 3
Predetermined image processing calculations are performed at 10, 320, 330, and 340. In this example, the SIMD equation is used. After the arithmetic processing, the switch Si0 in the memory circuit 200 is turned on by the word write signal WWi (i = 0 to 2) from the address decoding circuit 400, and the arithmetic circuits 310, 320, and 33 via the write bit line WBi.
0 and 340 are used as the calculation results in the memory circuits 210 and 22.
It is stored in the register Ri0 in 0, 230, 240 (timing T10).

Timing T3 During the next one horizontal period (timing T3), the word write signal WWi (i = 0) from the address decoding circuit 400.
2), the memory circuits 210, 220, 230,
The switches Si0, Si1, Si2 in 240, and
The switches Ti0, Ti1 and Ti2 are turned on, and the registers Ri0 in the memory circuits 210, 220, 230 and 240 are
Data from the Ri1 and Ri2 are calculated by the arithmetic circuits 310 and 320,
330, 340, and arithmetic circuits 310, 320, 3
Memory circuits 210, 220, 23 via 30, 340
The registers Ri0, Ri1 and Ri2 in 0 and 240 are returned (timing T12). Then, the final calculation result is stored in the register Ri2 in the memory circuits 210, 220, 230, 240. The video signal applied to the digital video signal processing device during this horizontal period is the timing T1.
Similarly, the data is stored in the M registers R1 to Rm in the shift register circuit 100 (timing T11).

[0023] In the timing T4 horizontal blanking period (timing T4),
Word read signal RW from address decode circuit 400
2 depending on the memory circuit 210, 220, 230, 240
The switch Ti2 therein is turned on, and the switch Si in the shift register circuit 100 is turned on by the word write signal WW. As a result, the operation result data stored in the register Ri2 is transferred to the read bit line RBi and the operation circuit 31.
Write bit line W via 0, 320, 330, 340
Register R in shift register circuit 100 via Bi
The data is stored in i (timing T13).

The arithmetic circuits 310, 320, 330, 34 are added to the timing T5 register Ri.
After storing the calculation result at 0, the read pointer RP for turning on the switch V1 is input at the beginning of the next one horizontal period (timing T5). As a result, the switch V1 in the shift register circuit 100 is turned on, and the operation result stored in the register R1 is output data OU.
It is output as T. The switch V1 is the read pointer R
It is energized only while P is applied and then turns off. Immediately thereafter, the write pointer WP is applied to energize the switch U1 to close the contact of the switch U1. At this time, the pixel data of the next video signal is input as the input data IN, and the first pixel data is output as the output data OUT and stored in the empty register R1. The read pointer RP is transferred to the 1-bit unit time delay element G1 and delayed there, and the output thereof turns on the switch V2, and the operation result stored in the register R2 is output. Similarly to the above, the switch V2 is energized only while the read pointer RP is applied, and then turned off. Immediately thereafter, the write pointer WP from the 1-bit unit time delay element G1 is applied to the switch U2 to energize and close the switch U1. The pixel data next to the video signal is applied, and the pixel data is output from the register R2 and stored in the empty register R2. Thereafter, similarly, the calculation results stored in the registers R3 to Rm are sequentially output. As a result, 1
The output data OUT of the calculation result for the horizontal period (1H) is output in word (pixel) serial (timing T1
5). At the same time, the pixel data of the next video signal is stored in the registers R1 to Rm. The pixel data stored in the registers R1 to Rm at the timing T15 is
At timing T16, as at timing T12,
Data transfer and arithmetic processing are performed.

Thereafter, the same processing as described above is performed. At timing T6 and timing T17, processing similar to that at timing T13 is performed. Timing T7 At timing T18 and timing T19, the same processing as at timing T14 and timing T15 is performed. At timing T20, at timing T1
The same processing as 6 is performed. At timing T8 and timing T21, processing similar to that at timing T13 and timing T17 is performed.

In the digital video signal processing device shown in FIG. 18, the data in the adjacent memories cannot be used for arithmetic operation. For example, the read bit line RBi and the read bit line RBi + 1 are connected to each other. If the data is supplied to the adjacent arithmetic circuit 300 via a selector (not shown), the data in the register Rij (j = 0 to 2) and the data in the register R (i + 1) j are used. It can be calculated by the arithmetic circuit 300. The selector circuit is also controlled by the control circuit 500. However, the selector for calculating the data in the adjacent registers (memory) in the memory circuit 200 is not directly related to the present invention, and is therefore omitted in FIG. It is also omitted in the description of the invention.

Further, in FIG. 18, one memory circuit, for example, the memory circuit 210 is composed of three registers, but normally the memory circuit 210 is composed of 128 to 1024 registers according to the number of pixels. To be done. Here, in order to simplify the description, the memory circuit 2
The number of registers in 10 is three.

In the above processing of the video signal, the video signal in which the blanking period exists for a sufficiently long time has been described. For example, as shown in FIG. 20, like the MUSE signal,
Some video signals have extremely short horizontal blanking periods (see, for example, "MUSE-Hi-Vision transmission method, Yuichi Ninomiya, published by The Institute of Electronics, Information and Communication Engineers", Chapter 3, page 45).

[0029]

The problem of the conventional serial / parallel converter illustrated in FIG. 13 will be described. When data comes continuously, overwriting occurs in the above-mentioned serial / parallel converter and the data is destroyed. If the circuit configuration of the 2-bank system that solves this overwriting is taken, the circuit configuration becomes complicated.

The problem of the conventional parallel / serial converter illustrated in FIG. 15 will be described. This parallel / serial converter also encounters the same overwriting problem as the serial / parallel converter. If the circuit configuration of the 2-bank system that solves this overwriting is taken, the circuit configuration becomes complicated.

The above-mentioned serial / parallel converter overwriting arithmetic / processing device using the parallel / serial converter has the above-mentioned problems.

The problem of the digital video signal processing device illustrated in FIG. 18 will be described. In the MUSE signal, the horizontal blanking period is only 11 sample periods. In such a short blanking period, the shift register circuit 100
It is not possible to transfer data from the M registers R1 to Rm in the memory to the registers in the memory circuit 200 in terms of timing. Similarly, during a short blanking period, the shift register circuit 10 shifts from the register in the memory circuit 200.
Writing data to the registers R1 to Rm in 0 is not possible in terms of timing.

The reason will be described in detail. The shift register circuit 100 is controlled by the control signal from the address decoding circuit 400.
Switches Ti (i = 1 to m) before and after the register Ri in
Also, the switch Si0 is turned on to set the pixel data of the video signal stored in the register Ri to the read bit line RBi.
To the memory circuit 20 via the write bit line WBi.
It stores in the register Ri0 in 0. Further, the switch Ti2 and the shift register circuit 1 in the memory circuit 200
The switch Si in 00 is turned on to turn on the memory circuit 200.
In order to store the operation result stored in the register Ri2 in the register Ri2 in the shift register circuit 100 via the read bit line RBi, the operation circuit 300, and the write bit line WBi, 12 samples (cycles) in the MUSE signal are stored. Suppose it takes more time. One horizontal period (1H)
Minute data is the register R in the shift register circuit 100.
Immediately after being stored in 1 to Rm, that is, from the horizontal blanking period, for example, the start of timing T4 in FIG. 19, the data in the register Ri in the shift register circuit 100 is transferred to the register Ri0 in the memory circuit 200, and the register Ri is transferred.
2 data to the register R in the shift register circuit 100
i is transferred (timing T13), but 1
Since it takes 2 samples or more, new pixel data is input at the time of the transfer and is stored in the register R1 via the switch U1 (timing T1).
4). Therefore, the existing data in the register R1 in the shift register circuit 100 is overwritten with new data before the transfer to the memory circuit 200 is completed, and the data is destroyed. That is, the original data cannot be normally transferred to the memory circuit 200.

As described above, the shift register circuit 100 receives the video signal having an extremely short horizontal blanking period or the video signal having substantially no horizontal blanking period.
There is no time margin to write from the register inside to the memory circuit 200, and conversely, there is no time margin to write from the memory circuit 200 to the register inside the shift register circuit 100. As a result, the conventional digital video signal processing device encounters a problem that it cannot process a video signal having a short horizontal blanking period.

The object therefore, the present invention of the present invention, even if the input data is continuously arriving without causing the destruction of data due to overwriting, and provides a serial / parallel converter without increasing the circuit scale To do.

Another object of the present invention is to provide a parallel / serial converter which does not cause data destruction due to overwrite even if input data continuously arrives and does not increase the circuit scale. is there.

It is a further object of the present invention that, in the arithmetic processing unit using the serial / parallel converter overwriting parallel / serial converter, the destruction of data due to overwriting occurs even if input data continuously arrives. An object of the present invention is to provide an arithmetic processing device that does not increase the circuit scale.

An object of the present invention is to provide a digital video signal processing device capable of performing a predetermined process even on a video signal having a short horizontal blanking or a video signal having substantially no horizontal blanking period. Especially.

[0039]

According to the present invention, a serial operation of serially inputting input data consisting of M = (m + n) pieces of data per predetermined time and outputting the data in parallel is performed. The / parallel converter inputs m data in serial and outputs in parallel, m
Number of first register circuits, m number of second register circuits that are provided in parallel with the first register circuits and that input m number of data serially and output in parallel, and n number of data And n third register circuits for serial input and parallel output.

The number of m register circuits is defined by the number that the first or second register circuit can receive data of the next cycle during parallel output. Specifically, the number of m register circuits is defined by the parallel output time and the input time interval of M = (m + n) pieces of data that are periodically input.

Specifically, each of the first register circuit, the second register circuit and the third register circuit is provided with a register for storing each data and a write pointer provided on the input side of the register. It has an input switch that is energized and an output switch that is energized by a write enable signal provided on the output side of the register.

Preferably, each of the first register circuit, the second register circuit and the third register circuit delays a 1-bit write pointer for activating the input switch in accordance with the data input timing. It has a 1-bit unit time delay element. The 1-bit unit time delay elements in the respective register circuits are connected in series, and the 1-bit first write pointer is sequentially delayed in accordance with the data input timing, so that the first register circuit and the second register circuit Of the last stage 1-bit unit time delay element in the first register circuit and the first-stage 1-bit unit time delay element in the second register circuit so as to continuously activate the corresponding input switch of Connected in series. In addition, the 1-bit second write pointer, which is alternately applied with the application of the first write pointer in response to the data input timing, is sequentially delayed so as to be applied in the first register circuit and the third register circuit. The last-stage 1-bit unit time delay element in the first register circuit and the first-stage 1-bit unit time delay element in the third register circuit are connected in series so as to continuously energize the input switch. It

Specifically, the input data is M (= m
+ N) is a 1-frame video signal composed of pixel data, and the input time interval is a horizontal blanking period.

Further, according to the present invention, M = (α
A parallel / serial converter that periodically inputs input data consisting of + β) pieces of data and serially outputs the data is an α piece of data that inputs α pieces of data in parallel and outputs them serially. Is provided in parallel with the first register circuit of, the β second register circuit for inputting β data in parallel and outputting serially, and the β second data register circuit for paralleling β data. , And third serial register circuits for serially outputting the same.

The number of the β register circuits is defined by the number which can receive the data of the next cycle during the parallel data input. Specifically, the number of the β register circuits is defined by the parallel data input / output time and the input time interval of M = (α + β) data that is periodically input.

Specifically, each of the first register circuit, the second register circuit, and the third register circuit stores a register for storing each of the data, and a write enable signal provided on the input side of the register. And an output switch provided on the output side of the register and energized by a read pointer.

More specifically, each of the first register circuit, the second register circuit and the third register circuit is
It has a 1-bit unit time delay element for delaying a 1-bit read pointer for activating the output switch in accordance with the input timing of the data. The 1-bit unit time delay elements in each register circuit are connected in series.
The read pointer applied to the data output timing is sequentially delayed to activate the corresponding output switch in the first register circuit and the second register circuit, so that the final stage of the first register circuit is activated. The 1-bit unit time delay element and the first-stage 1-bit unit time delay element in the second register circuit are connected in series. Further, the read pointer is sequentially delayed at the data output timing next to the data output timing so that the first register circuit and the third register circuit
The 1-bit unit time delay element at the final stage in the first register circuit and the 1-bit unit time delay element at the first stage in the third register circuit are activated so as to energize the corresponding output switch in the register circuit. Connected in series.

Specifically, the input data is M (= α
It is a 1-frame video signal composed of + β) pixel data, and the input time interval is a horizontal blanking period.

Further, according to the present invention, an arithmetic processing unit for serially inputting input data consisting of M = (m + n) = (α + β) pieces of data per predetermined time and arithmetically processing the data in parallel is provided. The serial / parallel converter, processor means having M processor elements for independently processing the data output from the serial / parallel converter, and M processor results of the processor means in parallel. There is provided an arithmetic processing device having the parallel / serial converter for inputting and serially outputting.

The arithmetic processing unit according to the first aspect of the present invention serially inputs input data consisting of M data per predetermined time, performs arithmetic processing on these M data in parallel, and executes these parallel arithmetic operations. An arithmetic processing unit for serially outputting a result, wherein N = M / 2 pieces of data are serially input and output in parallel, and N pieces of parallel data are input and serially output. , N
= Second register circuit for serially inputting M / 2 pieces of data and outputting in parallel and inputting N pieces of parallel data and outputting serially, and first half N pieces of data for the first register A serial / parallel inter-converter having control means for inputting to the circuit for parallel output and for inputting the latter half N pieces of data to the second register circuit for parallel output; and N pieces from the first register circuit. Of the parallel data received from the first register circuit, performs a predetermined calculation on the received parallel data, and outputs the calculation result to the first register circuit, and N pieces of N pieces from the second register circuit. Second arithmetic circuit means for receiving the parallel data, performing a predetermined arithmetic operation on the received parallel data, and transmitting the arithmetic result to the second register circuit.

Specifically, the first arithmetic circuit means is the first arithmetic circuit means.
Of N register circuits for receiving parallel data from the register circuit and N operation circuits for performing a predetermined operation on the received parallel data, and the operation result is directly or through the memory circuit. It is sent to the first register circuit. The second arithmetic circuit means also includes N memory circuits that receive the parallel data from the second register circuit,
And N arithmetic circuits for performing a predetermined arithmetic operation on the received parallel data, and outputs the arithmetic result to the second register circuit via the memory circuit or directly.

More specifically, the first register circuit and the second register circuit respectively include a register for storing the data, a first input switch for inputting serial input data to the corresponding register, and the register. A first output switch for outputting the data stored in the arithmetic circuit means to the arithmetic circuit means, a second input switch for inputting the arithmetic result from the arithmetic circuit means to the register, and a second input switch for outputting the arithmetic result stored in the register. It has an output switch. The first input switch is activated in response to the input timing of the serial input data, and the first output switch is activated in response to the parallel output timing to the arithmetic circuit means.
The second input switch is energized in response to the operation output timing of the arithmetic circuit means, and the second output switch is energized according to the serial output timing.

The arithmetic processing unit of the second form of the arithmetic processing unit of the present invention serially inputs input data consisting of M pieces of data per predetermined time, performs arithmetic processing of these M pieces of data in parallel, and An arithmetic processing unit for serially outputting a parallel arithmetic result, wherein a first serial / parallel converter for inputting N = M / 2 data in serial and outputting in parallel, and N = M / 2 for The second serial / serially input data and output in parallel
A parallel converter and a first parallel / serial converter that inputs N pieces of parallel data and serially outputs the data.
A second parallel / serial converter for inputting N parallel data and serially outputting the parallel data, and N parallel data from the first serial / parallel converter are received, and the received parallel data has a predetermined value. A first arithmetic circuit means for performing an arithmetic operation and transmitting the arithmetic result to the first parallel / serial converter, and N parallel data from the second serial / parallel converter are received and received. It has a second arithmetic circuit means for performing a predetermined arithmetic operation on the parallel data and transmitting the arithmetic result to the second parallel / serial converter, and a control circuit means.

Specifically, the first arithmetic circuit means is the first
, N memory circuits that receive parallel data from the serial / parallel converter and N operation circuits that perform a predetermined operation on the received parallel data, and the operation results are passed through the memory circuit. Alternatively, the second arithmetic circuit means sends the data directly to the first parallel / serial converter and the second arithmetic circuit means converts the parallel data from the second serial / parallel converter into N memory circuits and the received parallel data. And N arithmetic circuits for performing a predetermined arithmetic operation, and outputs the arithmetic result to the second parallel / serial converter via the memory circuit or directly.

Specifically, each of the first serial / parallel converter and the second serial / parallel converter has a register for storing the input data, an input switch for inputting serial input data to the corresponding register,
The first parallel / serial converter and the second parallel / serial converter each have an output switch for outputting the data stored in the register to the arithmetic circuit means, and the first parallel / serial converter and the second parallel / serial converter respectively store the arithmetic result and the arithmetic result. To the register, and an output switch for serially outputting the data stored in the register. The first parallel / serial converter and the second parallel / serial converter respectively include an input switch for inputting the calculation result from the calculation circuit means to the register and an output switch for outputting the calculation result stored in the register. Have. The input switch of the serial / parallel converter is activated in response to the input timing of the serial input data, and the output switch of the serial / parallel converter is activated according to the parallel output timing to the arithmetic circuit means. The input switch of the parallel / serial converter is activated in response to the operation output timing of the arithmetic circuit means, and the output switch of the parallel / serial converter is activated according to the serial output timing.

The arithmetic processing unit according to the third aspect of the present invention is
A first serial / parallel mutual conversion circuit, a second serial / parallel mutual conversion circuit, and second input data are selectively supplied to the first serial / parallel mutual conversion circuit or the second serial / parallel mutual conversion circuit. The parallel data is received from the input data selection circuit and the first serial / parallel mutual conversion circuit or the second serial / parallel mutual conversion circuit that are input to, and a predetermined operation is performed, and again,
Arithmetic circuit means for sending to the first serial / parallel mutual conversion circuit or the second serial / parallel mutual conversion circuit, and the first serial / parallel mutual conversion circuit or the second
And an output data selection circuit which selectively outputs the serial output of the serial / parallel mutual conversion circuit.

[0057]

In the serial / parallel converter of the present invention, m pieces of data are cyclically alternately input to the first register circuit and the second register circuit serially, and n pieces of data are input to the serial input. Subsequently, serial input is performed to the third register circuit, and the serially input data is simultaneously output in parallel. Since the first register circuit and the second register circuit are used alternately, no overwrite occurs. The number of m register circuits is defined by the number that can receive the data of the next cycle during the parallel output, but the circuit configuration is very small as compared with the conventional 2-bank system.

In the parallel / serial converter of the present invention, α pieces of data are input in parallel to the first register circuit, and then β pieces of data are alternately alternated to the second register circuit and the third register circuit. Parallel input to the register circuit, and further serially output the data input to the first register circuit and the second or third register circuit. Overwriting does not occur because the second and third register circuits are used alternately. The number of β register circuits is defined by the number that can receive the data of the next cycle during the serial output. Compared to the conventional case where the parallel / serial converter has two banks, , The circuit configuration is small.

The arithmetic processing unit of the present invention is the serial /
Since the parallel converter and the parallel / serial converter are used, the circuit configuration is simplified and the problem of overwriting does not occur.

The operation of the arithmetic processing unit according to the first embodiment of the present invention will be described. The control means in the serial / parallel mutual converter inputs the first half N pieces of data to the first register circuit and outputs them in parallel, and outputs the latter half N pieces of data to the second half.
Input to the register circuit and output in parallel. Further, the control means operatively connects the first register circuit and the second register circuit in series, receives the operation result output from the first operation circuit means in the first register circuit, and outputs the operation result serially. The operation result output from the second operation circuit means is received by the second register circuit and serially output following the serial output of the first register circuit.

The operation of the arithmetic processing unit according to the second embodiment of the present invention will be described. The control circuit means inputs the first half N serial input data to the first serial / parallel converter and inputs the second half N serial input data to the second serial / parallel converter. Further, the control circuit means outputs the operation result serially stored in the first parallel / serial converter and, following the serial output of the operation result, outputs the operation result serial output stored in the second parallel / serial converter. To do. The control means in the serial / parallel mutual converter inputs the first half N pieces of data to the first register circuit for parallel output, and inputs the latter half N pieces of data to the second register circuit for parallelization. Output. Further, the control means operatively connects the first register circuit and the second register circuit in series, receives the operation result output from the first operation circuit means in the first register circuit, and outputs the operation result serially. The operation result output from the second operation circuit means is received by the second register circuit and serially output following the serial output of the first register circuit.

The operation of the arithmetic processing unit according to the third embodiment of the present invention will be described. Since this arithmetic processing unit has a serial / parallel mutual conversion circuit having a 2-bank configuration, when there is no time margin between the input data and the next input data, the normal 2
Operate in bank system. On the other hand, when there is sufficient time margin between the input data and the next input data, the input data selection circuit is operated to alternate between the first serial / parallel mutual conversion circuit and the second serial / parallel mutual conversion circuit. Input data is applied to and complex calculations are possible using these data. The operation result is selected and output by the output data selection circuit.

[0063]

First, a serial / parallel converter will be described. FIG. 1 shows a first serial / parallel converter of the present invention.
FIG. 3 is a circuit configuration diagram of a serial / parallel converter as an example of FIG. In the present embodiment, this serial / parallel converter is a 9-word serial / parallel converter, and includes the first group of registers R1A to R3A, the second group of registers R1B to R3B, and the third group of registers R4 to. R9, first
1 of the first group that delays the write pointer WPA of
Bit unit time delay elements H1A to H3A, 1-bit unit time delay elements H1B to H3B that delay the second write pointer WPB by a unit time, and Third bit delay unit that delays the first write pointer WPA and the second write pointer WPB by a unit time. 1-bit unit time delay elements H4 to H9 of the group, input switches U1A to U3A of the first group, and input switch U of the second group
1B to U3B, third group switches U4 to U9, first group output switches T1A to T3A, second group output switch T
1B to T3B, the third group of switches T4 to T9, the first OR circuit ORW, and the second OR circuit ORR are connected as illustrated. The 1-bit unit time delay elements H1A to H3A, H1B to H3B, H4 to H9
Is configured to sequentially energize the input switches U1A to U3A or U1B to U3B and U4 to U9 by the first write pointer WPA and the second write pointer WPB, and sequentially store the sequentially input data in the register. Therefore, the unit time corresponding to the input time of continuous data is delayed.

The first group of 1-bit unit time delay elements H1A to H3A for delaying the first write pointer WPA are connected in series. A second group of 1-bit unit time delay elements H1B to H3B for delaying the second write pointer WPB
Are also connected in series. First write pointer WPA
The 1-bit unit time delay elements H4 to H9 of the third group, which delay the second write pointer WPB, are also connected in series. 1-bit unit time delay elements H1A to H1 of the first group
3A and 1-bit unit time delay elements H1B to H of the second group
Although it is provided in parallel with 3B, the 1-bit unit time delay element H4 of the third group is divided into a 1-bit unit time delay element H3A and a 1-bit unit time delay element H3B via the first OR circuit ORW. It is connected. That is, when the 1-bit unit time delay element H3A delays and outputs the first write pointer WPA, or the 1-bit unit time delay element H3B outputs the second write pointer WPB.
Are delayed and output, any one of these write pointers is input to the 1-bit unit time delay element H4.

When the first write pointer WPA is input, the 1-bit unit time delay elements H1A to H3A of the first group are inputted.
Are sequentially delayed, and further sequentially delayed by the 1-bit unit time delay elements H4 to H9 of the third group. Register RiA (i = 1 to 3) of the first group and register Rj of the third group
The input unit of (j = 4 to 9) has a first group of input switches Ui.
A (i = 1 to 3) and the input switch Uj (j of the third group)
= 4 to 9), and the first read pointer R
If the switch UiA of the first group and the switch Uj of the third group are sequentially turned on in PA, the data DATA1 to DATA9 forming the input data IN are sequentially output and the register R of the first group R
iA and the third group of registers Rj. Similarly, when the second write pointer WPB is input, the second write pointer WPB is input.
The 1-bit unit time delay elements H1B to H3B of the group are sequentially delayed, and the 1-bit unit time delay element H of the third group is further delayed.
It is delayed sequentially from 4 to H9. Second group of registers Ri
B (i = 1 to 3) and the above-mentioned third group of registers Rj
The input switch Ui of the second group is also provided in the input section of (j = 4 to 9).
B (i = 1 to 3) and the above-mentioned third group of input switches Uj (j = 4 to 9) are provided, and if the switches UiB and Uj are turned on by the second read pointer RPB, the input data is input. Data DATA1 forming IN
~ DATA9 are sequentially stored in the register RiA and the register Rj. However, the first write pointer WPA and the second write pointer WPB are applied at alternate timings.

At the output of the first group of registers RiA, the first
There is a group output switch TiA, and when the first read enable signal REA is given, the switch TiA (i = 1 to 3)
Is turned on, and the data stored in the register RiA is output as output data OUTi (i = 1 to 3).
The output of the second group of registers RiB also has a second group of output switches TiB, and the second read enable signal REB
Switch TiB (i = 1 to 3) is turned on,
The data stored in the register RiB is the output data O
It is output as UTi (i = 1 to 3). First read enable signal REA and second read enable signal R
It is applied at an alternate timing with EB. The first read enable signal REA or the second read enable signal REB is transmitted through the OR circuit ORR to the switch Ti (i =
4 to 9), these switches Tj
(J = 4 to 9) is turned on, and the data stored in the registers R4 to R9 becomes the output data OUTi (i =
1 to 3), followed by output data OUT4 to OUT
It is output as 9.

The detailed operation of the serial / parallel converter will be described with reference to FIG. Data groups DATA11 to DATA19 and data group DATA that form the input data IN
21-DATA29, data group DATA31-DATA
39 is sequentially input. The data group is, for example, image data for each frame of the video signal.
In this example, the first group of data groups DATA11 to DATA
The last input data DATA19 of 19 and the first input data D of the data groups DATA21 to DATA29 of the second group
It is considered that there is no gap between the ATA 21 and the ATA 21, that is, the case where data continuously arrives. Along with the input of the first data DATA1, the first write pointer WPA is also input. The switch U1A is turned on by the write pointer WPA, and the data DATA11 is stored in the register R1A. The switch U2 is switched by the first write pointer WPA delayed by the first 1-bit unit time delay element H1A.
A is turned on, and the second input data DATA12 is stored in the register R2A. The switch U3A is turned on by the first write pointer WPA delayed by the first 1-bit unit time delay element H2A, and the third input data DATA13 is stored in the register R3A. The first write pointer WPA turns on the input switch U4 via the OR circuit ORW. As a result, the fourth input data DATA14 is stored in the register R4. The first write pointer WPA is transferred to the 1-bit unit time delay element H4 of the third group and turns on the input switch U5 to store the fifth input data DATA15 in the register R5. Hereinafter, similarly, the input data DATA16 to DATA19
Are stored in the registers R6 to R9. Data DATA
Immediately after 19 is input, the first read enable signal REA is applied. As a result, the switch TiA (i
= 1 to 3) and the switch Tj (j = 4 to 9) are simultaneously energized (turned on), so that the register RiA (i = 1 to 1).
3) and the data DATA1i and the data DATAj stored in the register Rj (j = 4 to 9) are simultaneously output in parallel as output data OUTi (i = 1 to 9). In this embodiment, it is assumed that this output time takes three cycles.

In this example, when a video signal is considered as the input data IN, the last input data DATA of the data of the first group, as in the example in which the horizontal blanking period does not exist.
It is assumed that the first input data DATA21 of the second group of data is input immediately after the input of 19 is completed. At the same time that the data DATA21 is input, the second write pointer WPB is also input. Light pointer W
Switch U1B is turned on by PB, and data DAT
A21 is stored in the register R1B. The switch U2B is turned on by the second write pointer WPB delayed by the first 1-bit unit time delay element H1B, and the second write pointer WPB is turned on.
The input data DATA22 of is stored in the register R2B. The switch U3B is driven by the second write pointer WPB delayed by the second 1-bit unit time delay element H2B.
Is turned on, and the third input data DATA23 is stored in the register R3B. The second write pointer WPB turns on the input switch U4 via the OR circuit ORW. As a result, the fourth input data DATA24 is stored in the register R4. The second write pointer WPB is transferred to the 1-bit unit time delay element H4 of the third group, and the input switch U5 is turned on to turn on the fifth input data DATA.
25 is stored in the register R5. Similarly, the input data DATA26 to DATA29 are registered in the registers R6 to R
9 is stored. The second read enable signal REB is applied immediately after the data DATA 29 is input.
As a result, the switch TiB (i = 1 to 3) and the switch Tj (j = 4 to 9) are simultaneously energized (turned on), so that the register RiB (i = 1 to 3) and the register Rj are activated.
The data DATA2i and the data DATAj stored in (j = 4 to 9) are output data OUTi (i = 1 to 1).
9) are simultaneously output in parallel. This output also takes 3 cycles.

In the above-mentioned operation, the second group data D
ATA21, DATA22, and DATA23 are input after the last data DATA19 of the first group without input idle time such as horizontal blanking period.
The data DATA21 to DATA23 are stored in the registers R1B to
Since they are respectively stored in R3B, the first group of registers R
Data DATA11, D stored in 1A to R3A
ATA12 and DATA13 are the next data DATA
It is not overwritten and is not destroyed by 21, DATA22 and DATA23. Further, when new data DATA24 to DATA29 input at the next timing are stored in the shared third group of registers R4 to R9, the data DATA14 stored in the third group of registers R4 to R9 is stored. Since ~ DATA19 has already been output, overwriting does not occur in the third group of registers R4 to R9.

Further data groups DATA31 to DAT
At the same time that the first input data DATA31 of A39 is input, the first write pointer WPA is input, and the data DATA31 to DATA39 are stored in the first group of registers RiA.
(I = 1 to 3) and the third group of registers Rj (j = 4 to
9). The second read enable signal REB is input immediately after the data DATA 29 is input,
Register RiB (i = 1 to 3) and register Rj (j
= 4 to 9), the input data DATA2i stored in
Is a switch TiB (i = 1 to 3) and a switch Tj
Output data OUTi (i = 1 through i = 4 to 9)
~ 9) are output in parallel.

Data DATA31, DATA32, DA
The TA 33 is continuously input after the data DATA 29, but since these data DATA 31 to DATA 33 are stored in the registers R 1 A to R 3 A, respectively, the data DATA 2 stored in the registers R 1 B to R 3 B is stored.
1, DATA22 and DATA23 are not overwritten. The parallel outputs of the data groups DATA21 to DATA29 are three cycles immediately after the data DATA29 is input,
That is, new data DATA31, DATA32, DA
It takes place at the time when TA33 is entered, but during this time,
As described above, the data DATA2i (i = 1 to 3)
Is continuously stored in the register RiB (i = 1 to 3), no overwrite occurs. Also, register R4
Since the data DATA34 to DATA39 are stored in the registers R4 to R9 after the output of the data DATA24 to DATA29 stored in the registers R4 to R9, the registers R4 to R9 are not overwritten.

Thereafter, similarly to the above, the first write pointer WPA and the second write pointer WPB are alternately given together with the serial input of the input data IN to store the data in the register, and then the first read enable signal. RE
A and the second read enable signal REB are alternately applied to output the data stored in the register in parallel.
In this way, when the input side of the serial / parallel converter (the part having the subscripts 1 to 3) is partially of the two-bank type, the data in which the horizontal blanking period does not exist continuously comes. Even without overwriting, serial / parallel conversion can be done without problems. Number of registers R1A to R1A in the first group (m), register R1B in the second group
~ The number of R3B (m) and the number of switches (m) provided on the input side and the output side of these registers are, in this example, the time required for parallel output, that is, the number for saving the time for preventing overwriting. m = 3. The minimum value mmin of this number m is defined by the following equation. mmin = Tpo-Ti (1) where Tpo is the parallel output time, and Ti is the input data time interval, that is, the serial input time of the last data of a certain data group and the first data of the next data group. Of course, if the input data time interval Ti is longer than the parallel output time Tpo, it is not necessary to redundantly provide m registers and switches. In this way, the circuit of the serial / parallel converter of the present invention requires only m circuits to be redundant, and the circuit configuration is simpler than the case where all two conventional serial / parallel converters are used.

In the above description, the 9-word serial / parallel converter has been described, but it goes without saying that the present invention can be applied to other numbers of words. For example, when exemplifying a video signal, the number of data in one frame, for example, 1024 words. When processing a large amount of data like this, the conventional 2-bank method
Although it is necessary to provide double registers such as 1024 registers and switches, in the present invention, it is sufficient to provide a redundant circuit corresponding to the parallel output time. The effect of the converter is great.

Next, the parallel / serial converter of the present invention will be described. FIG. 3 is a circuit diagram as an embodiment of the parallel / serial converter of the present invention. This parallel / serial converter is a 9-word parallel / serial converter in the present embodiment, and includes six first group registers Q1 to Q.
6, 3 second group registers Q7A to Q9A, 3rd group 3 registers Q7B to Q9B, 6 first group 1-bit unit time delay elements G1 to G6, 3 second group registers 1-bit unit time delay elements G7A to G9A, 1 of 3 third groups
Bit unit time delay elements G7B to G9B, six first group input switches S1 to S6, three second group input switches S7A to S9A, and three third group input switches S7B
To S9B, six first group output switches V1 to V6, 3
Second group output switches V7A to V9A, three third switches
It is composed of a group of output switches V7B to V9B, a first selector circuit SELW, and a second selector circuit SELR.

Six groups of 1-bit unit time delay elements G1 to G connected in series for delaying the read pointer RP
6 and three of the second group of 1-bit unit time delay elements G7A to G9A connected in series are connected in series via a selector circuit SELR. Similarly, the 1-bit unit time delay elements G1 to G6 of the first group and the 3-group 1-bit unit time delay elements G7B to G9B connected in series are connected in series via the selector circuit SELR. It The 1-bit unit time delay elements G1 to G6 and the 1-bit unit time delay elements G7A to G9A are connected in series, or the 1-bit unit time delay elements G1 to G6 and the 1-bit unit time delay elements G7B to G9B are connected in series. Selector circuit SELR
Selectively done by. That is, the output of the 1-bit unit time delay element G6 is set to 1 via the selector circuit SELR.
It is input to the bit unit time delay element G7A or the 1-bit unit time delay element G7B. The selection of the selector circuit SELR is controlled by a signal from the control circuit CNT.
If the selector circuit SELR is selected on the side of the 1-bit unit time delay element G7A, the read pointer RP delayed by the 1-bit unit time delay element G6 is input to the 1-bit unit time delay element G7A, and the 1-bit unit time delay element G7A is input. The read pointer RP is not input to the time delay element G7B. If the selector circuit SELR is selected on the side of the 1-bit unit time delay element G7B, the read pointer RP delayed by the 1-bit unit time delay element G6 is 1
It is input to the bit unit time delay element G7B and is not input to the 1 bit unit time delay element G7A. The read pointer RP includes registers Q1 to Q6 (Qi (i = 1 to 1
6)), registers Q7A to Q9A (QjA (j = 7 to
9)), registers Q7B to Q9B (QjB (j = 7 to
9)) output switches V1 to V6 provided on the output side
(Vi (i = 1 to 6)), output switches V7A to V9A
(VjA (j = 7 to 9)), output switches V7B to V9
It is used for energizing (ON) B (VjB (j = 7 to 9)). However, the output switches V7A to V9A (VjA (j
= 7-9)) and output switches V7B-V9B (VjB
(J = 7-9)) is selectively activated. When these switches are activated, the data stored in the registers Q1 to Q6, the registers Q7A to Q9A, or the registers Q7B to Q9B are serially output. Registers Q1 to Q
6 (Qi (i = 1 to 6)), registers Q7A to Q9A
(QjA (j = 7 to 9)) or registers Q7B to Q9
The input portion of B (QjB (j = 7 to 9)) has an input switch Si (i = 1 to 6) and an input switch SjA (j = 7 to 9).
9) and the input switch SjB (j = 7 to 9). However, the input switch SjA (j = 7 to 9) and the input switch SjB (j = 7 to 9) are selectively energized. Switch Si and switch SjA or switch SjB
Are simultaneously turned on by the write enable signal WE, the parallel input data INi (i = 1 to 9) are simultaneously stored in the register Qi and the register QjA or the register QjB. Register QjA or register QjB
Which of the parallel input data IN7 to IN9 is stored depends on which of the selector circuits SELW is selected. The selector circuit SELW is controlled by the signal from the control circuit CNT. If the selector circuit SELW is selected on the switch SjA side, the switch SjA is selected by the write enable signal WE.
(J = 7-9) is turned on, the data is stored in the register RiA, and the switch SjB (j = 7-9) remains off. If the selector circuit SELW is selected on the side of the switch SjB, the switch SjB (j = 7 to 9) is turned on by the write enable signal WE, the data is stored in the register RiB, and the switch SjA (j = 7).
~ 9) remains off.

Parallel / illustrated in FIG. 3 with reference to FIG.
The details of the operation of the serial converter will be described. Here, the first parallel data group DATA51 to DATA59 (DA
It is assumed that TA5i (i = 1 to 9)) is input in three cycles, and six cycles later, the next data groups DATA61 to DATA69 are input in three cycles. That is, it is assumed that there are 6 cycles between the first data group and the next data group. As the first group of parallel input data IN1 to IN9, the data DATA
51 to DATA 59 (DATA 5i (i = 1 to 9)) are input. The write enable signal WE is input simultaneously with the input of the data DATA51 to DATA59, and the control circuit CNT causes the selector circuit SELW to switch to the switch Sj.
Selected to A side. According to the write enable signal WE, the switch Si (i = 1 to 6) and the switch SjA (j
= 7-9) is turned on and the input data DATA5i (i
= 1 to 9) are the registers Qi (i = 1 to 6) and the register Q.
It is stored in jA (j = 7 to 9). Immediately after the first data group DATA5i has been input, the read pointer input terminal RP is input, the switch V1 is turned on, and the input data DATA stored in the register Q1 is input.
51 is output as output data OUT. Then, the read pointer RP is sent to the 1-bit unit time delay element G1 and delayed to turn on the switch V2 to output the input data DATA52 stored in the register Q2. Thereafter, similarly, the input data DA stored in the register Qi (i = 3 to 6) and the register QjA (j = 7 to 9)
TA53 to DATA59 are serially output in order. While these data are being serially output over 9 cycles, the read pointer RP has a 1-bit unit time delay element G.
After being output from 6, the selector circuit SELR is selected by the control circuit CNT to the 1-bit unit time delay element G7A side.

Six cycles after the data group DATA5i is input, the next data group DATA6i is input.
At the same time that the data DATA61 to DATA69 are input, the write enable signal WE is input, and the selector circuit SELW is selected on the switch SiB side. As a result, the switch Si (i = 1 to 6) and the switch SjB
(J = 7-9) is turned on and the input data DATA6i
(I = 1 to 9) are stored in the register Qi (i = 1 to 6) and the register QjB (j = 7 to 9).

In this way, the data DATA6i (i = 1
~ 9) are data DATA57, DATA58, DAT
A59 is input when it is not output yet,
Data DATA67 to DATA69 are registered in the register Q7B to
Registers Q7A-Q are stored in Q9B respectively.
Data DATA57-DAT still stored in 9A
Overwriting does not occur in A59. Also, data D
Register Q in which ATA51 to DATA56 are stored
New data DATA61 to DATA6 for 1 to Q6
6 is stored, but data DATA51 to DATA56
Is already output, so there is no problem. That is,
The data DATA51 to DATA56 stored in the register Qi (i = 1 to 6) before the data DATA6i (i = 1 to 9) is input are output to output the data DATA.
6i (i = 1 to 9) is input to register Qi (i = 1 to 1)
6) and 3 stored in the register QiB (i = 7 to 9)
Since the data DATA57 to DATA59 stored in the register QjA (j = 7 to 9) are output at the time of the cycle, the serial output of the first data group DATA51 to DATA59 can be correctly output.

Six cycles after the input of the data group DATA6i, the next data group DATA7i is further input. At the same time that the data DATA71 to DATA79 are input, the write enable signal WE is input, and the selector circuit SELW is selected on the switch SiA side.
As a result, the switch Si (i = 1 to 6) and the switch S
jA (j = 7 to 9) is turned on and the input data DATA
7i (i = 1 to 9) is stored in the register Qi (i = 1 to 6) and the register QjA (j = 7 to 9). Data group D
The read pointer RP is input immediately after the ATA 6i is input over three cycles. As a result, the switch V1 is turned on, and the input data DATA61 stored in the register Q1 is output. Then, the read pointer RP is transferred to and delayed by the 1-bit unit time delay element G1, the switch V2 is turned on, and the input data DATA62 stored in the register Q2 is output. Thereafter, data DATA stored in the registers Qi (i = 3 to 6) and the register QjB (j = 7 to 9) are similarly stored.
63 to DATA 69 are serially output in order. However,
While serially outputting these data over 9 cycles,
The control circuit CNT selects the selector circuit SELR to the 1-bit unit time delay element G7B side.

The data DATA7i (i = 1 to 9) is input at the timing when the data DATA67 to DATA69 are not yet output, but the data DATA77 is to the register Q7A and the data DATA78 is to the register Q8A.
Further, since the data DATA79 is stored in the register Q9A, respectively, the data DATA67, DATA68, D still stored in the registers Q7B, Q8B, Q9B.
ATA69 has no problem of overwriting. Further, new data DATA71 to DAT are stored in the registers Q1 to Q6 in which the data DATA61 to DATA66 are stored.
A76 is stored, but data DATA61 to DATA
There is no problem because 66 has already been serially output.

The data DATA61 to DATA66 stored in the register Qi (i = 1 to 6) before the data DATA7i (i = 1 to 9) is input are output, and the data DATA7i (i = 1 to 9) is output. Is input to register Q
i (i = 1 to 6) and the time of three cycles stored in the register QiA (i = 7 to 9), the register QiB (i = 7 to
Data stored in 9) DATA67 to DATA6
Since 9 is output, data groups DATA61 to DATA6
The serial output of 9 can be output correctly. After that, similarly,
The selector circuit SELW and the selector circuit SELR are alternately switched.

Thus, the output side of the parallel / serial converter of the present invention (the part having the subscripts 7 to 9) is partially divided into two.
By using the bank type, parallel / serial conversion can be performed without causing overwriting. In the present invention, the circuit is simpler than the case of using two conventional parallel / serial converters because it is a partial two-bank system in which redundancy is partially provided. The number (β) of the registers Q7A to Q9A of the second group, the number (β) of the switches S7A to S9A before and after these registers, the number (β) of the switches V7A to V9A, and the registers Q7B to Q9B of the third group. Of the switches S7B to S9B before and after these registers (β), and the switch V7B.
In the above example of Hitoshi, the number (β) of V9B to V9B is defined by the parallel input time as described above. More generally,
The minimum value βmin of the above number β is defined by the following equation. βmin = Tpi−Ti (1) where Tpi is the parallel input time, and Ti is the input data time interval, that is, the serial input time of the last data of a certain data group and the first input of the next data group. Of course, if the input data time interval Ti is longer than the parallel input time Tpi, it is not necessary to provide β registers and switches redundantly. As described above, the circuit of the parallel / serial converter of the present invention is redundant with β circuits, and the circuit configuration is simpler than the case where all two conventional serial / parallel converters are used.

In the above description, the parallel / serial converter of 9 words has been described, but it goes without saying that the present invention can be applied to other numbers of words. For example, when exemplifying a video signal, the number of data in one frame, for example, 1024 words. When processing a large amount of data like this, the conventional 2-bank method
Although it is necessary to provide double registers such as 1024 registers and switches, in the present invention, it is only necessary to provide a redundant circuit corresponding to the parallel input time. The effect of the converter is great.

The arithmetic processing unit of the present invention will be described. If the arithmetic processing unit having the parallel processor described in the conventional example is configured by using the serial / parallel converter and the parallel / serial converter of the present invention described above, a video signal having a short horizontal blanking period or MUSE Even when there is almost no horizontal blanking period, it is possible to handle without overwriting.

FIGS. 5 and 6 are block diagrams of the first embodiment of the digital video signal processing apparatus as a preferred example of the arithmetic processing apparatus of the present invention. This digital video signal processing device has a first shift register circuit (SRA) 100A, a first memory circuit 200A, a first arithmetic circuit 300A, an address decoding circuit 400A, a control circuit 500A, and a gate circuit 600. Further, the digital video signal processing device has a second shift register circuit (SRB).
100B, a second memory circuit 200B, and a second arithmetic circuit 300B. First shift register circuit 100A
Accepts serially input data, outputs the data in parallel to the first arithmetic circuit 300A, and outputs the first arithmetic circuit 3A.
It functions as a serial / parallel mutual conversion circuit that functions as a circuit for both the serial / parallel converter and the parallel / serial converter that receives the operation result of 00A in parallel and outputs it in serial. Similarly, the second shift register circuit 100B also functions as a serial / parallel mutual conversion circuit.

First shift register circuit 100A, first
The memory circuit 200A, the first arithmetic circuit 300A, the address decode circuit 400A, and the control circuit 500A of FIG.
8, the shift register circuit 100 and the memory circuit 2 illustrated in FIG.
00, arithmetic circuit 300, address decode circuit 400
A, which corresponds to the control circuit 500, and its basic configuration is substantially the same. However, N = M / 2. M is 1
It is equal to the number M of pixel data of video signals for the horizontal period.
Therefore, N is half the number M of pixel data of video signals for one horizontal period. In association with the number of pixels (m + n) of the serial / parallel converter described above, M = m + n. However, hereinafter, the parameters m and n are used regardless of the numbers m and n in the serial / parallel converter. Further, in the description of this embodiment, when the parameters M and N are expressed as subscripts, the lower case letters m and n are used. Further, in association with the number of pixels (α + β) of the parallel / serial converter described above, M = α + β.

The shift register circuit 100A includes 1-bit unit time delay elements G1 to Gn, N (= M) for storing read pointers for N pixel data in one horizontal period of a video signal.
/ 2) 1-bit unit time delay elements H1 to Hn for storing a write pointer for pixel data, registers R1 to Rn for N pixel data, and register pixel data of a corresponding video signal provided in the preceding stage of these registers R1 to Rn R1 to Rn
To store in the switch pair U1: S1 to Un: Sn,
The switch pairs V1: T1 to Vn: Tn are provided in the subsequent stage of these registers R1 to Rn to output the pixel data of the corresponding video signals from the registers R1 to Rn. The memory circuit 200A has N memory circuits 210, 220, 230, 240 provided in parallel. Each of the memory circuits 210, 220, 230, 240 has the same circuit configuration. For example, the memory circuit 210 is
It has three stages of registers R10 to R12, and switches S10: T10 to S1 are provided on both sides of these registers R10 to R12.
2: T12 is provided. The arithmetic circuit 300A has N
Arithmetic circuits 310, 320, 330 provided in parallel
340.

In the digital video signal processing device, in the circuit configuration illustrated in FIG. 5, a gate circuit 600 is added to the shift register circuit 100A, the memory circuit 200A, and the arithmetic circuit 300A, and the circuit illustrated in FIG. That is, the second shift register circuit (SRB) 10
0B, second memory circuit 200B, second arithmetic circuit 30
0B is added. Second shift register circuit 100
B, the second memory circuit 200B, and the second arithmetic circuit 300B respectively include the first shift register circuit 10
0A, the first memory circuit 200A, and the first arithmetic circuit 300A. The shift register circuit 100B includes 1-bit unit time delay elements G (n + 1) to Gm, M for storing read pointers for M pixel data.
1-bit unit time delay elements H (n + 1) to Hm for storing a write pointer for pixel data, registers R (n + 1) to Rm for M pixel data, and these registers R (n + 1) to
A switch pair Un + 1: Sn + 1 to Um: Sm provided in the preceding stage of Rm for storing the pixel data of the corresponding video signal in the registers R (n + 1) to Rm, and these register R
The switch pairs Vn + 1: Tn + 1 to Vm: Tm are provided in the subsequent stage of (n + 1) to Rm to output the pixel data of the corresponding video signal from the registers R (n + 1) to Rm. The memory circuit 200B has M memory circuits 250, 260, 270, and 280 arranged in parallel. Each of the memory circuits 250, 260, 270 and 280 has the same circuit configuration. For example, the memory circuit 250 includes three stages of registers R (n + 1) 0 to R (n +
1) 2 and these registers R (n + 1) 0 to R (n
Switch S (n + 1) 0: T (n +) on both sides of +1) 2
1) 0 to S (n + 1) 2: T (n + 1) 2 are provided. The arithmetic circuit 300B has M arithmetic circuits 350, 360, 370, 380 provided in parallel.

The first shift register circuit 100A and the second
The shift register circuit 100B of FIG. That is, the 1-bit unit time delay element Gn for storing the read pointer at the final stage in the shift register circuit 100A and the 1-bit unit time delay element G (n + 1) for storing the read pointer at the first stage in the shift register circuit 100B are the read pointers. Are connected so that they can be stored continuously. Similarly,
The last-stage write pointer storing 1-bit unit time delay element Hn in the shift register circuit 100A and the first-stage write pointer storing 1-bit unit time delay element H (n + 1) in the shift register circuit 100B continuously write pointers. Are connected so that they can be stored. 1 and 2
In this digital video signal processing device, the first shift register circuit 100A and the second shift register circuit 1
Although 00B is shown as a separate circuit configuration, they may be integrally configured.

Also in this embodiment, SIMD type arithmetic processing is performed. Therefore, only one control circuit 500A is provided. The arithmetic circuits 310, 320, 330, and 340 provided in parallel in the first arithmetic circuit 300A have the same circuit configuration. Arithmetic circuits 350, 360, 370, 3 provided in parallel in the second arithmetic circuit 300B
80 also has the same circuit configuration.

The gate circuit 600 includes the first AND circuit 6
01, second AND circuit 602, third AND circuit 60
And a fourth AND circuit 604, and the control circuit 500
In response to the enable signals EN1 to EN4 output from A, the word write signal WW and the word write signal WW0 output from the address decode circuit 400A are gated. The first enable signal EN1 and the second enable signal EN2 are exclusively (alternately) output from the control circuit 500A, and the AND circuit 601 or the AND circuit 602 outputs the register R in the first shift register circuit 100A.
1 to 0 word write signal WWA for activating switches S1 to Sn connected to 1 to Rn, or registers R (n + 1) 1 to R in second shift register circuit 100B.
Any of the 2-0th word write signal WWB for activating the switches S (n + 1) to Sm connected to m is output. The third enable signal EN3 and the fourth enable signal EN4 are exclusively (alternately) output from the control circuit 500A, and the AND circuit 603 or the AND circuit 604 outputs the respective memory circuits in the first memory circuit 200. 1-1 word write signal WW0A for activating switches S10-Sn0 connected to the first-stage registers R10-Rn0 in the register, or the second shift register circuit 100B.
Any of the 2-1th word write signal WW0B for activating the switches S (n + 1) 0 to Sm0 is output to the registers R (n + 1) 0 to Rn0 of the first stage among them. That is, from the control circuit 500A, "write bit line WBi to register R
The “write to i” instruction is the address decode circuit 40.
Address decode circuit 400A generated for 0A
Thus, even if the instruction is decoded and the word write signal WW in the "on" state is generated, if the enable signal EN1 is "off (low level)", the 1-0th word write signal W is generated.
W is off, and pixel data is registered in the register Ri (i = 0 to 0).
It is not written in n). The word write signal WW and the second enable signal EN2 are applied to the AND circuit 602, and the output thereof is the second shift register circuit 1
It is used as an ON signal for the switches Sn + 1 to Sm in 00B. Even if the control circuit 500B generates an instruction "write from the write bit line WBi to the register Ri" and the address decode circuit 400A decodes the instruction to generate the word write signal WW in the ON state, the AND circuit 602. If the enable signal EN2 applied to the second shift register circuit 100B is off, the 1-0th word write signal WWB is not turned on, and pixel data is stored in the register Ri (i = n + 1 to m) in the second shift register circuit 100B. ) Is not written. The word write signal WW0 and the third enable signal EN3 are input to the AND circuit 603, and the output thereof is used as an ON signal for the switches S10 to Sn0 in the first memory circuit 200. Even if the control circuit 500A generates an instruction "write from the write bit line WBi to the register Ri0" and the address decode circuit 400A decodes the instruction to generate an ON word write signal WW0, the third enable signal is generated. If the signal EN3 is off, the word write signal WW0A remains off, and the pixel data is registered in the register Ri.
It is not written to 0 (i = 0 to n). AND circuit 60
The word write signal WW0 and the fourth enable signal EN4 are input to the switch 4, and the output thereof is the switch Sn.
It is used as an ON signal for +10 to Sm0. From the control circuit 500A, "write bit line WBi to register R
Even if the "write to i0" command is generated and the address decode circuit 400A decodes the command to generate the word write signal WW0 in the ON state, if the enable signal EN4 is OFF, the word write remains at the OFF level. It is the built-in signal WW0B, and the pixel data is the register Ri0.
It is not written in (i = n + 1 to m).

The memory circuit 2 will be generally described below.
The registers in 00A and 200B are replaced by the register Rij
(I = 1 to m, j = 0 to 2). First shift register circuit 100A and second shift register circuit 10
Registers in 0B are set to register Ri (i = 1 to n, n + 1
~ M) and switches Ui, Si, Vi, Ti. First
The registers and switches in the circuit in the memory circuit 200A, and the registers and switches in the circuit in the second memory circuit 200B are also generally described by using subscripts as in the above.

In the first shift register circuit 100A and the second shift register circuit 100B, when the switch Ui is turned on, the pixel data as the input data IN is stored in the register Ri, and when the switch Si is turned on, the write bit is written. Pixel data from line WBi is in register R
It is stored in i. When the switch Vi provided in the output part of the register Ri is turned on, the data stored in the register Ri is output as output data OUT, and when the switch Ti is turned on, the data stored in the register Ri is a write bit. Output on line RBi.

The operation of the digital video signal processing device illustrated in FIGS. 5 and 6 will be described. In this example, FIG.
With reference to, the most severe condition without any horizontal blanking period will be described. In FIG. 7, between the timing T1 and the timing T2, between the timing T2 and the timing T3, between the timing T3 and the timing T4, similarly, there is no horizontal blanking period. Timing T1 (1) Timing T11, 12 The video signal is applied in word (pixel) serial as input data IN. One horizontal period (timing T1 in FIG. 2)
The write pointer WP is input at the same time that the first pixel data of is input. As a result, the switch U1 in the first shift register circuit 100A is turned on, so that the first pixel data corresponds to the first shift register circuit 100A.
It is stored in the register R1. The write pointer WP is transferred to the 1-bit unit time delay element H1 and delayed there. Next, since the switch U2 is turned on by the write pointer WP delayed by the 1-bit unit time delay element H1, the next pixel data is stored in the register R2. Thereafter, pixel data are similarly stored in the first shift register circuit 100A in the registers R3 to Rn and in the second shift register circuit 100B in the register R (n +).
1) to Rm are sequentially stored. In this way, pixel data for one horizontal period (1H) is stored in the registers R1 to Rn,
And it is stored in the registers R (n + 1) to Rm (timing T11 and timing T12).

(2) Timing T13 In the latter half of the timing T1, the control circuit 500A "reads data from the register Ri to the read bit line RBi,
A command “write to register Ri0” is issued via the arithmetic circuit ALUi and the write bit line WBi. Address decode circuit 400A responds to the instruction by generating word read signal RW in the ON state and word write signal WW0 in the ON state. The control circuit 500A also outputs a third enable signal EN3 in the on state and a fourth enable signal EN4 in the off state. As a result, the word write signal WW0A turns on, but the word write signal WW0B turns off. Therefore, only the input data stored in the registers R1 to Rn is written in the registers R10 to Rn0 in the first memory circuit 200A, and the register Rn + 1.
The data stored in Rm to Rm is the second memory circuit 20.
It is not written to the registers Rn + 10 to Rm0 in 0B.

Timing T2 (1) Timing T14, 15 At the beginning of the next one horizontal period (timing T2), the control circuit 500A reads "data from the register Ri to the read bit line RBi and outputs the data to the arithmetic circuit ALUi and the write bit line WBi. Write to register Ri0 ”via the command. Address decode circuit 400A outputs an on-level word read signal RW and word write signal WW0 in response to the instruction. At the same time, the control circuit 50
0A outputs an on-level fourth enable signal EN4 and an off-level third enable signal EN3. As a result, the word write signal WW0B turns on, but the word write signal WW0A remains off. Therefore, the register R in the second shift register circuit 100B
Only the pixel data stored in (n + 1) to Rm are written in the registers R (n + 1) 0 to Rm0, and the data stored in the registers R1 to Rn are stored in the registers R10 to R10.
It is not written to Rn0 (timing T15). At the end of the timing T15, the registers R10 to Rn0
Pixel data is stored in the registers Rn + 10 to Rm0.

(2) Timing T16 Next, at a timing T16 which is an intermediate point of the timing T2, the control circuit 500A and the address decoding circuit 40.
Depending on the signal from 0A, switches Si0, Si
1, Si2, Ti0, Ti1, Ti2 (i = 0 to n, n
+1 to m) are turned on to control the arithmetic operation in the arithmetic circuit ALUi, thereby supplying data from the registers Ri0, Ri1, Ri2 to the arithmetic circuit ALUi, and the arithmetic circuit ALUi.
An operation of returning the calculation result in (1) to the registers Ri0, Ri1, Ri2 is performed (timing T16). Then, the final calculation result is stored in the register Ri2. This operation is controlled by the control circuit 500A. Also, during this operation period, the enable signal EN3 and the enable signal EN
Leave 4 on level.

(3) Timing T19 At the end of timing T2, the control circuit 500A "reads the data from the register Ri2 to the read bit line RBi and writes the data to the register Ri via the arithmetic circuit ALUi and the write bit line WBi". Issue a command. In response to the instruction, the address decode circuit 400A
An ON signal is given to the write bit lines RW2 and WW. At the same time, the control circuit 500A turns on the enable signal E of the on level.
It outputs N1 and the enable signal EN2 at the off level. As a result, the word write signal WWA is turned on, but the word write signal WWB remains off. Therefore, only the above-mentioned operation result data stored in the registers R12 to Rn2 is stored in the registers R1 to Rn.
Data stored in the registers Rn + 12 to Rm2 are not written to the registers Rn + 1 to Rm (timing T19).

At the beginning of the next one horizontal period (timing T3) following timing T3 , the read pointer RP is input. As a result, the switch V1 is turned on, and the calculation result stored in the register R1 is output as the output data OUT. Then, the read pointer RP is transferred to the 1-bit unit time delay element G1 and delayed, and the switch V2 is turned on by its output, and the operation result stored in the register R2 is output. Thereafter, the registers R3 to R are similarly processed.
The calculation result data stored in n is output. As a result, the first half of one horizontal period (1H) (n = m
The calculation result of / 2) is output in word (pixel) serial (timing T21).

At the same timing (time) as the timing T21, that is, in the first half of the timing T3, the control circuit 500A reads "from register Ri2 to read bit line RB".
Data is read to i and written to the register Ri via the arithmetic circuit ALUi and the write bit line WBi. "
Issue a command. In response to the instruction, address decode circuit 400A gives an ON signal to read bit line RW2 and outputs an ON level word write signal WW. At the same time, the control circuit 500A controls the on level second enable signal EN2 and the off level first enable signal EN.
1 is output. As a result, the word write signal WWB
Is on level, but the word write signal WWA remains off level. Therefore, the registers Rn + 12 to Rm
Only the above-mentioned operation result stored in 2 is the register R of
(N + 1) to Rm, and registers R12 to Rn
2 The stored data is not written in the registers R1 to Rn (timing T23).

In the middle of the timing T3, the read pointer RP reaches the 1-bit unit time delay element G (n + 1) in the second shift register circuit 100B. As a result, in the latter half of the timing T3, the switch V (n + 1)
~ Vm are sequentially turned on, and registers R (n + 1) to Rm
The calculation result stored in is output. That is, the calculation result of the latter half portion of one horizontal period (1H) is output from the data output terminal OUT in word (pixel) serial (timing T26).

The same operation as described above is performed for the next pixel data delayed by one horizontal period (timing T4, timing T).
14, timing T17, timing T18, timing T22, timing T24, timing T28, timing T30, timing T32, timing T3.
5). Further, the same operation as above is performed on the next data delayed by another horizontal period (timing T20, timing T25, timing T27, timing T31, timing T33, timing T37).

According to the circuit configuration and operation described above, the video signal can be processed even if there is no horizontal blanking period. That is, in the present embodiment, (1) as the shift register circuit as the serial / parallel mutual conversion circuit for performing the serial / parallel conversion and the parallel / serial conversion, the first half N of the M image data are A first (first half) shift register circuit (SRA) 100A for performing serial / parallel conversion and parallel / serial conversion, and serial / parallel conversion and parallel / serial conversion for the latter N pieces of M pieces of image data. It is divided into a second (second half) shift register circuit (SRB) 100B to be performed, and (2) a gate circuit 600 is provided, and further AND circuits 601 and 60 are provided.
2 makes it possible to independently write pixel data from the memory circuits 200A and 200B to the shift registers 100A and 100B in the first half shift register and the second half shift register. (3) Furthermore, the memory circuit 2
The register Ri0 in 00A and 200B is also in the first half (i =
0 to n) and the latter half (i = n + 1 to m), and the AND circuits 603 and 604 divide the shift registers 100A and 1
Pixel data can be independently written from 00B to the memory circuits 200A and 200B in the first half and the second half. As a result, the shift registers 100A and 100B can be used even for a video signal having no horizontal blanking period.
From the memory circuits 200A and 200, and from the memory circuits 200A and 200B to the shift registers 100A and 100.

A modification of the digital video signal processing device of the present invention will be described. 5 and 6, a unit time delay element group for delaying the write pointer by a unit time, H1 to
Hm and a unit delay element group for transferring (storing) the read pointer, G1 to Gm. However, as can be seen from the above description, both the input timing of the read pointer RP and the input timing of the write pointer WP are always at the beginning of the horizontal period, and therefore the unit delay element Gi for the read pointer transfer at the same time. And the unit delay element H for the write pointer transfer.
It is the same as the data of i. Therefore, the unit delay element Gi
And the unit delay element Hi can also be used. The circuit configuration for that purpose will be described. For example, the read pointer input terminal RP and the unit delay element Gi (i = 1 to m) are removed, and the ON signal of the switch Vi is changed to the unit delay element H (i-
It may be given by 1).

Further, in FIGS. 5 and 6, the register in the first shift register circuit 100A and the register in the second shift register circuit 100B are replaced with an input shift register and an output shift register. Used in combination. That is, the register Ri stores the input data IN
Is for receiving the video signal as described above and transferring the data to the memory, and for receiving the data of the operation result from the memory and outputting and transferring the data as the output data OUT. In the present invention, the above register may be divided into an input shift register and an output shift register. As the circuit configuration, a register for receiving the input data IN and transferring the data to the memory and a register for transferring the operation result from the memory are provided independently.
That is, the circuit configuration is as illustrated in FIG. However, in this case, the serial / parallel converter has a circuit configuration where m = n for M = m + n image data of one frame. That is, two serial / parallel converters for processing N pixel data, which is half the pixel data M of one frame, are provided. Similarly, as a parallel / serial converter, M = α for one frame
For + β image data, the circuit configuration is when α = β. That is, two parallel / serial converters for processing N pixel data, which is half the pixel data M of one frame, are provided.

As described above, in the present invention, the shift register is divided into the first half (SRA) and the second half (SRB), and the AND circuits AND1 and AND2 enable the writing from the memory to the shift register independently in the first half and the second half. In addition, the register Ri0 in the memory also has the first half (i = 0
~ N) and the second half (i = n + 1 to m) and AND circuit A
Writing from the shift register to the memory can be independently performed in the first half and the second half by ND3 and AND4.
As a result, even in a video signal having an extremely short horizontal blanking period, it becomes possible to write data from the shift register to the memory and then write data from the memory to the shift register.

A second embodiment of the digital video signal processing device as an example of the arithmetic processing device of the present invention will be described. FIG. 8 is a block diagram of a second embodiment of the digital video signal processing device. This digital video signal processing device includes a first shift register circuit 100C, a second shift register circuit 100D, a memory circuit 200, and an arithmetic circuit 3 which are provided in parallel.
00, address decode circuit 400B, control circuit 500
Have B.

The first shift register circuit 100C includes M 1-bit unit time delay elements G1A to GmA (hereinafter, generally GiA, i = 1) for storing the read pointer RP.
˜m)), M 1-bit unit time delay elements H1A to HmA (HiA) for storing the write pointer, serial / parallel conversion for storing the pixel data of the video signal and further functioning as an input / output buffer. Registers R1A to RmA, these registers R1A to RmA (Ri
M) switches U1A to UmA provided before and after A)
(UiA), M switches S1A to SmA (Si
A), M switches V1A to VmA (ViA), and M switches T1A to TmA (TiA). The 1-bit unit time delay elements H1A to HmA are connected in series, and the first write pointer WPA is sequentially sent to the 1-bit unit time delay elements H1A to HmA. Similarly, the 1-bit unit time delay elements G1A to GmA are also connected in series, and the first read pointer RPA is sequentially sent to the 1-bit unit time delay elements G1A to GmA. If the switch UiA is turned on, the pixel data of the video signal as the input data IN is stored in the register RiA, and if the switch SiA is turned on, the write bit line WB.
The data from i is stored in register RiA. When the switch ViA is turned on, the data stored in the register RiA is output as output data OUT, and when the switch TiA is turned on, the data stored in the register RiA is output to the write bit line WBi.

The second shift register circuit 100D has the same circuit configuration as that of the first shift register circuit 100C, and the M 1-bit unit time delay elements G1B to GmB (GiB, i = 1) for storing the read pointer RP. ~ M),
M 1-bit unit time delay elements H1B to HmB (HiB) for storing the write pointer, pixel data of the video signal are stored, serial / parallel conversion is performed, and further input /
M registers R1B to R functioning as output buffers
mB (RiB), M switches U1B to UmB (Ui provided before and after these registers R1B to RmB.
B), M switches S1B to SmB (SiB), M switches V1B to VmB (ViB), and M switches T1B to TmB (TiB). The 1-bit unit time delay elements H1B to HmB are connected in series.
Write pointer WPB of 1-bit unit time delay element H
It is sequentially sent to 1B-HmB. Similarly, the 1-bit unit time delay elements G1B to GmB are also connected in series, and the second read pointer RPB is sequentially sent to the 1-bit unit time delay elements G1B to GmB. If the switch UiB is turned on, the pixel data of the video signal is stored in the register RiB, and if the switch SiB is turned on, the pixel data from the write bit line WBi is stored in the register RiB. If the switch ViB is turned on, the register R
The data stored in iB is output as the output data OUT, and if the switch TiB is turned on, the register Ri
The data stored in B is output to the write bit line RBi.

The memory circuit 200 has M memory circuits 210, 220, 230 and 240 provided in parallel. Each of the memory circuits 210, 220, 230, 240 corresponds to each of the memory circuits 210, 220, 2 illustrated in FIG.
It has the same circuit configuration as 30, 240. That is, the memory circuit 200 has the register Rij (i = 1 to m, j = 0.
2), switches Sij (i = 1) provided before and after the switch
~ M, j = 0 to 2), switch Tij (i = 1 to m, j
= 0 to 2). The arithmetic circuit 300 has M arithmetic circuits 310, 320, 330, and 340. Also in this embodiment, since the SIMD type arithmetic processing is performed, the arithmetic circuits 310, 320, 330 and 340 have the same circuit configuration. The control circuit 500B uses the address signal ADRS and the arithmetic circuits 310, 320, 330, 340 (ALU1 to ALU1).
The control signal CTRL for controlling the calculation in m) is generated. The address decoding circuit 400B includes the control circuit 50.
Address signal ADRS from 0A is received and decoded, and first word write signal WWA, first word read signal RWA, second word write signal WWB, second word read signal RWB, word write Embedded signals WW0 to WW2,
It outputs word read signals RW0 to RW2. These signals are transmitted to the switch S1A in the shift register circuit 100B.
-SmA, switches T1A-TmA, switches S1B-SmB in the shift register circuit 100D, switch T1
B to TmB, the switch Sij (i in the memory circuit 200
= 1 to m, j = 0 to 2), switch Tij (i = 1 to 1)
m, j = 0 to 2) are used to control energization and deenergization.

This digital video signal processing device is a 2-bank type digital video signal processing device. That is, two shift register circuits (first
Shift register SRA) 100C and shift register circuit (second shift register SRB) 100D are alternately used, similar to the digital video signal processor of the first embodiment described with reference to FIGS. 5 and 6. In addition, it prevents the problem that occurs when the horizontal blanking period is very short or there is no horizontal blanking period, "overwriting with new data at the time when data is being transferred between registers". ing. However,
The difference from the digital video signal processing device of the first embodiment is that
It is as follows. (1) The first shift register circuit 100C and the second shift register circuit 100D are not connected in series but are provided in parallel. Related thereto, the switch SiA and the switch SiB are connected to the same write bit line WBi, and the switch TiA and the switch TiB are connected to the same read bit line RBi. Furthermore, two types of read pointers are used: a first read pointer for the first shift register circuit 100C and a second read pointer for the second shift register circuit 100D. (2) The number of memory circuits 200 is one. (3) The number of the arithmetic circuits 300 is also one. (4) The address decode circuit 400B generates a word write signal WWA and a word read signal RWA for the first shift register circuit 100C, and a word write signal WWB and a word read signal RWB for the second shift register circuit 100D. To do. (5) The gate circuit 600 is not provided. Compared to the digital video signal processing device illustrated in FIGS. 5 and 6, this digital video signal processing device requires only one system for the memory circuit 200 and the arithmetic circuit 300, and thus has a simple circuit configuration.

The operation of the digital video signal processing device illustrated in FIG. 8 will be described with reference to FIG. FIG. 9 is an operation timing chart when the horizontal blanking period is the shortest, that is, when there is no horizontal blanking period. As the timing T1 input data IN, a video signal is supplied in word (pixel) serial. One horizontal period (timing T1 in FIG. 5)
When the write pointer WPA is input at the same time that the first pixel data is input to the switch U1A, the switch U1A is turned on, so that the first pixel data is stored in the register R1A. For the next input pixel data, the write pointer WP is sent to the 1-bit unit time delay element H1A and the switch U
Since 2A is turned on, it is stored in the register R2A. Thereafter, similarly, the input data is registered in the registers R3A to RmA.
Stored in. As a result, data for one horizontal period (1H) is stored in the registers R1A to RmA (timing T11).

Timing T2 The pixel data input during the next one horizontal period (timing T2) is stored in the registers R1B to RmB by inputting the write pointer WPB at the beginning of timing T2 (timing T22). . At the same time, at the beginning of the timing T2, the switch TiA (i = 1 to 1
Turn on m). As a result, the above-mentioned input pixel data stored in the register RiA is input to the arithmetic circuit ALUi via the register RBi. And switch S
By turning on i0, the above-mentioned input pixel data can be stored in the register Ri0 in the memory circuit 200 via the read bit line RBi, the arithmetic circuit ALUi, and the write bit line WBi (timing T21). By the word write signals WW0 to WW2 from the address decode circuit 400B, the switches Si0, Si in the memory circuit 200 are appropriately selected.
1, Si2, Ti0, Ti1, Ti2 are turned on, and the arithmetic circuit A is operated by the control signal CTRL from the control circuit 500B.
By controlling the operation in LUi, registers Ri0, R1
Pixel data is supplied to the arithmetic circuit ALUi from i1 and Ri2, and the arithmetic result in the arithmetic circuit ALUi is registered in the register Ri0,
The operation of returning to Ri1 and Ri2 is performed (timing T
23). Then, the final calculation result is stored in the register Ri2. At the end of the timing T2, the switch T
By turning on i2 and turning on the switch SiA,
The above-mentioned operation result stored in the register Ri2 is stored in the register RiA via the read bit line RBi, the operation circuit ALUi, and the write bit line WBi (timing T24).

The read pointer RPA is input at the beginning of one horizontal period (timing T3) after it is stored in the register in the timing T3 shift register circuit 100C. This allows the switch V
Since 1A is turned on, the calculation result stored in the register R1A is output as output data OUT. Then, the read pointer RPA is sent to the 1-bit unit time delay element G1A and delayed, and the switch V2A is turned on by its output, and the operation result stored in the register R2A is output as output data OUT. After that, similarly, the calculation result stored in the registers R3A to RmA is output as the output data OUT. In this way
The calculation result for one horizontal period (1H) is serially output as output data OUT in a word (pixel) manner (timing T32). That is, the pixel data input during the first horizontal period is the timing T11 and the timing T2.
The operation is performed in the order of 1, timing T23, timing T24, and timing T32. The pixel data input during the next one horizontal period is operated in the order of timing T22, timing T33, timing T34, timing T35, and timing T43. Is performed, and the data input during the next one horizontal period is the timing T31,
Timing T41, Timing T44, Timing T4
The operation is performed in the order of 5. This series of operations is performed by the control signal CTRL output from the control circuit 500B.

As described above, the first shift register circuit 1
It is input during the period of transfer of the input data from 00C (SRA) to the memory circuit 200 (timing T21) and the transfer of the data of the operation result from the memory circuit 200 to the first shift register circuit 100A (timing T24). The pixel data is stored in the second shift register circuit 100D (S
RB) (timing T22). From the second shift register circuit 100D (SRB) to the memory circuit 20
Transfer of input pixel data to 0 (timing T33),
From the memory circuit 200 to the second shift register circuit 100
The pixel data input during the period of the data transfer of the calculation result to D (timing T35) is input to the first shift register circuit 100C (SRA) (timing T31). Therefore, it is possible to avoid "overwriting with new data at a time during the transfer".

A third embodiment of the digital video signal processing device of the present invention will be described. As described above with reference to the first and second embodiments, all video signals, that is, a video signal with a long horizontal blanking period, a video signal with a short horizontal blanking period, and a horizontal blanking period. The circuit illustrated in FIG. 5 and FIG. 6 is used in consideration of the case where the horizontal blanking period is short, or the case where the horizontal blanking period is almost nonexistent, in order to provide a configuration capable of supporting a video signal that hardly exists. The configuration or the two-bank system had to be used as illustrated in FIG. However, if these digital video signal processing devices are applied to a video signal having a long horizontal blanking period, the circuit configuration is complicated, for example, two shift register circuits are provided, and the cost becomes high. There is. That is, for a video signal having a long horizontal blanking period, one shift register circuit is sufficient, but in the digital video signal processing device shown in FIG. The configuration is also complicated. In other words, as shown in FIG. 8, the configuration of the 2-bank type digital video signal processing device is effective for a video signal having a short horizontal blanking period, but is effective for a video signal having a long horizontal blanking period. However, one of the shift register circuits, for example, the second shift register circuit 100D is not working effectively. The third embodiment of the present invention solves the above problems.

FIG. 10 is a block diagram of the digital video signal processing device of the third embodiment. The digital video signal processing device of the third embodiment is different from the digital video signal processing device of the second embodiment illustrated in FIG. 8 in that an input pixel data selection switch (selector) 610 and an output pixel data selection switch (selector) 620 Has been added. Two input terminals INA and INB are provided, and the first input terminal I
Input pixel data from the NA is directly input to the first shift register circuit 100C (SRA). The input pixel data from the first input terminal INA and the input pixel data from the second input terminal INB are input to the selector 610.
Through the second shift register circuit 100D (SRB)
Has been entered in. Also, two output terminals OUTA, O
The shift register circuit 100 is provided with the UTB.
The output data of C and 100D are output to the first output terminal OUTA via the selector 620, and the output of the second shift register circuit 100D is directly output to the second output terminal O.
It is output to UTB. This digital video signal processing device also has a two-bank configuration, and the other circuit configurations are the same as those of the digital video signal processing device of the second embodiment except for the configuration described above. Selector 610 and selector 6
20 is controlled by the control signal CTR from the control circuit 500C.
L may be used or may be given from the outside of this digital video signal processing device. In this embodiment, the control circuit 500C controls the selector 610 and the selector 620.

The operation of the digital video signal processing device illustrated in FIG. 10 will be described separately for the case where the horizontal blanking period is long and the case where the horizontal blanking period is short. First, the operation of the circuit of the present invention when a video signal having a short horizontal blanking period is targeted will be described with reference to FIG. In this case, the selector 610 is selected on the side of the first input terminal INA, and the selector 620 selects the first shift register circuit 10 every horizontal period.
0C (SRA) output and second shift register circuit 1
00D (SRB) output is selected and output alternately.
Be energized. The timing T1 video signal is word (pixel) serially supplied from the first data input terminal INA. At the same time as the first pixel data of one horizontal period (timing T1 in FIG. 7) is input,
The first write pointer WPA is input. As a result, the switch U1A is turned on and the first input pixel data is stored in the register R1A. Write pointer WP
A is stored in the 1-bit unit time delay element H1A. At the next pixel data input timing, the switch U2A is turned on by the write pointer WPA stored in the 1-bit unit time delay element H1A, and the next pixel data is stored in the register R2A. Thereafter, similarly, the input pixel data is stored in the registers R3A to RmA. In this way, data for one horizontal period (1H) is stored in the registers R1A to RmA in the first shift register circuit 100C.
(Timing T11).

Timing T2 Pixel data input to the first input terminal INA during the next one horizontal period (timing T2) and input to the second shift register circuit 100D via the selector 610 is the timing T2. At the beginning of the second write pointer WP
B is applied and 1-bit unit time delay elements H1B to HmB
Are sequentially transferred, and the switches U1B to UmB are sequentially turned on to be stored in the registers R1B to RmB (timing T22). At the same time, at the beginning of the timing T2, the address decoding circuit 400B
The switch TiA (i = 1 to m) in the first shift register circuit 100C is turned on by the word read signal RWA from the register R1A at timing T11.
To the read bit line R
It is applied to the arithmetic circuit ALUi via Bi. After that, the word write signal WW from the address decode circuit 400B
The switch Si0 in the memory circuit 200 is turned on by 0 to store the above pixel data in the register Ri0 via the read bit line RBi, the arithmetic circuit ALUi, and the write bit line WBi (timing T21). Further, the switches Si0, Si1, Si2, and the switches Ti0, T are appropriately selected according to the signal from the address decoding circuit 400B.
i1 and Ti2 are turned on, the arithmetic operation in the arithmetic circuit (ALUi) is controlled by the control signal CTRL from the control circuit 500C, and the register Ri0 in the memory circuit 200,
Data is supplied to the arithmetic circuit ALUi from Ri1 and Ri2, and the arithmetic result in the arithmetic circuit ALUi is registered in the register Ri0,
The operation of returning to Ri1 and Ri2 is performed (timing T
23). The final calculation result is stored in the register Ri2. At the end of the timing T2, the memory circuit 200
Inside the shift register circuit 100C via the read bit line RBi, the arithmetic circuit ALUi, and the write bit line WBi by turning on the switch Ti2 and turning on the switch SiA. The data is stored in RiA (timing T24).

Timing T3 At this timing, the selector 620 has the control circuit 500
The first shift register circuit 1 is controlled by the control signal from C.
It is biased to a position that selects the output from 00C. At the beginning of one horizontal period (timing T3) after the pixel data is stored in the register RiA, the read pointer R
PA is applied. As a result, the switch V1A is turned on, and the calculation result stored in the register R1A is output as the output data OUTA via the selector 620. This read pointer RPA is transferred to the 1-bit unit time delay element G1A and delayed, and as a result, the switch V
2A is turned on, and the calculation result stored in the register R2A is output as output data OUTA via the selector 620. Thereafter, similarly, the registers R3A to R
The calculation result stored in mA is output as output data OUTA via the selector 620. in this way,
The calculation result stored in the registers R1A to RmA for one horizontal period (1H) is output as output data OUTA in word (pixel) serial fashion (timing T32).

As described above, the data input during the first horizontal period is operated in the order of timing T11, timing T21, timing T23, timing T24, and timing T32. Timing T3
During the operation of the timing T32 in the period of, the selector 620 keeps the first shift register circuit 100
The output of C is selected (timing T36). As a result, the data from the first shift register circuit 100C (SRA) which is the calculation result of the calculation circuit 300 is output as the output data OUTA. Pixel data input during the next one horizontal period includes timing T22, timing T33, timing T34, timing T35,
The operation is performed in the order of timing T43. Timing T
While the timing T43 is being operated in the period of 4, the selector 620 keeps the second shift register circuit 100
The output of D (SRB) is biased to be selected (timing T46). As a result, the second shift register circuit 10 holding the calculation result of the calculation circuit 300.
The output from 0D (SRB) is output from the selector 620. Further, the data input during the next one horizontal period is operated in the order of timing T31, timing T41, timing T44, and timing T45. The same applies thereafter. Thus, except that the control circuit 500C switches the selector 620 between the output side of the first shift register circuit 100C (SRA) and the output side of the second shift register circuit 100D (SRB) every horizontal period. For example, the arithmetic processing is performed by the same operation as that of the embodiment shown in FIG.

Next, the operation of the circuit of the present invention when a video signal having a long horizontal blanking period is targeted will be described with reference to FIG.
Will be described with reference to. Here, a case is considered in which two types of signals are input as the video signal, a calculation is performed using these two signals, and a video signal of the two types of calculation results is output. The digital video signal processing device described above has only one input / output terminal, so
It was not possible to input various kinds of video signals and perform complicated arithmetic processing. In this case, the selector 610 is set to the second input terminal INB side, and the selector 620 is set to the output side of the first shift register circuit 100C (SRA).

Timing T2 The first video signal is applied in word (pixel) serial from the data input terminal INA. 1 horizontal period (timing T
At the same time that the first pixel data of the video signal is input at the beginning of 1), the write pointer WPA is input, the switch U1A is turned on, and the first input pixel data is stored in the register R1A. The next input pixel data is stored in the register R2A by the write pointer WPA being sent to the 1-bit unit time delay element H1A and turning on the switch U2A by its output. Thereafter, similarly, the input pixel data are sequentially stored in the registers R3A to RmA.
Stored in. Thus, the pixel data for one horizontal period (1H) is stored in the registers R1A to RmA (timing T11).

At the same time, the second video signal is also applied word-wise (pixel) serially from the data input terminal INB. The first pixel data of the video signal is input at the first timing of one horizontal period (timing T1), and at the same time, the write pointer WPB is input to turn on the switch U1B and store the first pixel data in the register R1B. . The next input pixel data is stored in the register R2B because the write pointer WPB is transferred to the 1-bit unit time delay element H1B and the output thereof turns on the switch U2B. Thereafter, similarly, the input pixel data are sequentially stored in the registers R3B to RmB. In this way, data for one horizontal period (1H) is stored in the registers R1B to RmB (timing T13). At the beginning of the subsequent horizontal blanking period (timing T2), the second word read signal RWB from the address decoding circuit 400
Switch TiA (i in the shift register circuit 100D of
= 1 to m) are turned on. As a result, the register RiA
The first input pixel data stored in is input to the arithmetic circuit ALUi via the read bit line RBi. Then, by turning on the switch Si0 by the word write signal WW0 from the address decoding circuit 400, the above-mentioned first input pixel data is transferred to the register Ri0 via the read bit line RBi, the arithmetic circuit ALUi, and the write bit line WBi. (Timing T12). At the end of the timing T2, the address decoding circuit 400B
The word read signal RWB from the switch TiB
Turn on (i = 1 to m). This allows register R
The above-mentioned second input pixel data stored in iB is input to the arithmetic circuit ALUi via the read bit line RBi. Then, by using the word write signal WW1 from the address decoding circuit 400B to turn on the switch Si1, the second input pixel data is transferred to the register Ri1 via the read bit line RBi, the arithmetic circuit ALUi, and the write bit line WBi. (Timing T33).

Timing T3 During the next one horizontal period (timing T3), the switches Si0, Si1, Si2 and the switches Ti0, Ti are appropriately selected.
By turning on 1 and Ti2 and controlling the operation in the operation circuit (ALUi), data is supplied from the registers Ri0, Ri1 and Ri2 to the operation circuit ALUi, and the operation circuit ALUi is supplied.
An operation of returning the calculation result in <1> to the registers Ri0, Ri1, Ri2 is performed (timing T32). Final first
The result of the calculation is stored in the register Ri1, and the second result of the calculation is stored in the register Ri2.

[0126] In the beginning of the timing T4 subsequent horizontal blanking period (timing T4), similarly to the control method described above, the switch T
By turning on i1 and turning on the switch SiA,
The first operation result stored in the register Ri1 is stored in the register RiA via the read bit line RBi, the operation circuit ALUi, and the write bit line WBi (timing T41). At the end of timing T4, switch T
When i2 is turned on and the switch SiB is turned on, the second operation result stored in the register Ri2 is stored in the register RiB via the read bit line RBi, the operation circuit ALUi, and the write bit line WBi (timing T4
2).

Timing T5 One horizontal period (timing T
At the beginning of 5), the read pointer RPA is applied. As a result, the switch V1A is turned on, and the first calculation result stored in the register R1A is output as the output data OUTA. Then, the read pointer R
PA is transferred to the 1-bit unit time delay element G1A, the output of which turns on the switch V2A and the register R2A.
The calculation result stored in is output as output data OUTA. After that, the registers R3A to RmA are similarly set.
One of the calculation results stored in is output data OUTA
Is output as. In this way, one horizontal period (1
One of the calculation results of H) is output in word (pixel) serial as output data OUTA (timing T5).
2).

At the same time, the read pointer RPB is applied. As a result, the switch V1B is turned on and the other operation result stored in the register R1B is output data O.
It is output as UTB. Then, the read pointer RP
B is transferred to the 1-bit unit time delay element G1B, the output thereof turns on the switch V2B, and the other operation result stored in the register R2B is output as output data OUTB. Thereafter, similarly, the registers R3B to R
The other operation result stored in mB is the output data OU.
It is output as TB. Thus, one horizontal period (1
The other calculation result of (H) is output in word (pixel) serial as output data OUTB (timing T5).
5).

The same operation is performed for the next data delayed by one horizontal period (timing T31, timing T34,
Timing T41, Timing T42, Timing T5
3, timing T61, timing T62, timing T72, timing T75). Further, the same operation is performed on the next data delayed by another horizontal period (timing T51, timing T54, timing T61, timing T62, timing T73, timing T81,
Timing T82).

In this digital video signal processing device, the unit delay element group H for transferring the write pointer WPA is used.
1A to HmA and unit delay element groups G1A to GmA for transferring the read pointer RPA are provided separately and independently.
As can be seen from the above description, the read pointer RPA
Both the application timing of the write pointer WPA and the application timing of the write pointer WPA are always at the beginning of the horizontal period. Therefore, the 1-bit unit time delay element Gi at the same time
The values transferred to A and the 1-bit unit time delay element HiA are the same. Therefore, the 1-bit unit time delay element Gi
It is possible to use both A and the 1-bit unit time delay element HiA. For example, the input terminal of the read pointer RPA and the 1-bit unit time delay element GiA (i = 1
~ M) may be removed and the ON signal of the switch ViA may be given by the 1-bit unit time delay element HiA. The same applies to the 1-bit unit time delay elements H1B to HmB and the 1-bit unit time delay elements G1B to GmB. For example, the input terminal of the read pointer RPB and the 1-bit unit time delay element GiB (i = 1. ~ M) may be removed and the ON signal of the switch ViB may be given by the 1-bit unit time delay element HiB.

In the digital video signal processing device described above, the registers R1A to RmA and the register R are also included.
Although 1B to RmB are used as the input shift register and the output shift register respectively, the input shift register and the output shift register may be separated. That is, the register RiA (B) is for receiving the input data and transferring the input pixel data to the memory circuit 200, and for receiving the data of the operation result from the memory circuit 200 and transferring the data to the output terminal. However, the register for receiving the input data and transferring the pixel data to the memory circuit 200 and the register for receiving the calculation result from the memory circuit 200 and transferring the data to the output terminal may be separated.

As described above, in the present invention, the input selector (SIN) 610 and the output selector (SOUT) 62.
By adding 0, it is possible to operate as a 2-bank system when a video signal with a short horizontal blanking period is targeted, and when a video signal with a long horizontal blanking period is targeted, it is possible to operate as a 2-bank system. It is possible to perform an unprecedentedly complicated arithmetic operation in which a signal of one kind is input and an arithmetic operation is performed using these two signals to output a video signal of two kinds of operation results. That is, conventionally, when a video signal having a long horizontal blanking period is targeted, one shift register is over-spec, but in the present invention, two kinds of signals can be input and output by this over-spec. I am doing it. Further, instead of inputting two types of video signals, a signal with a long tone may be input from the first input terminal INA on the upper side and may be input from the second input terminal INB on the lower side. For example, input terminals INA, INB
Each have an 8-bit width, and when a video signal with a long horizontal blanking period is targeted,
It is possible to input a video signal having a bit tone.

[0133]

According to the serial / parallel converter of the present invention, overwriting can be prevented with a simple circuit configuration, and normal serial / parallel conversion can be performed.

According to the parallel / serial converter of the present invention, overwriting can be prevented and the parallel / serial conversion can be normally performed with a simple circuit configuration.

The serial / parallel converter and the arithmetic processing unit using the parallel / serial converter of the present invention can perform predetermined parallel arithmetic without complicating the circuit configuration.

According to the arithmetic processing unit of the present invention, even when there is no time until the next input data arrives, or even when it is very short, overwrite is prevented and the serially input data is parallelized. Can be calculated and the result can be output serially.

Furthermore, the serial / serial configuration of the two banks of the present invention
According to the arithmetic processing device having the parallel mutual conversion circuit and further provided with the input selector circuit and the output selector circuit at the input and output of these serial / parallel mutual conversion circuits, the time until the next input data arrives. If there is no
Or, even if it is very short, overwriting can be prevented, data input in serial can be calculated in parallel, and the result can be output in serial, and the time until the next input data arrives If there is enough, two serial / parallel mutual conversion circuits can be utilized to perform complicated arithmetic processing.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a serial / parallel converter of the present invention.

FIG. 2 is an operation timing diagram illustrating an operation of the serial / parallel converter illustrated in FIG.

FIG. 3 is a circuit configuration diagram of an embodiment of a parallel / serial converter of the present invention.

FIG. 4 is an operation timing diagram illustrating an operation of the parallel / serial converter illustrated in FIG.

FIG. 5 is a first partial circuit configuration diagram of a first example of the digital video signal processing device of the present invention.

FIG. 6 is a second partial circuit configuration diagram of the first example of the digital video signal processing device of the present invention.

FIG. 7 is an operation timing chart explaining an operation of the digital video signal processing device illustrated in FIGS. 5 and 6;

FIG. 8 is a circuit configuration diagram of a second example of the digital video signal processing device of the present invention.

9 is an operation timing diagram illustrating an operation of the digital video signal processing device illustrated in FIG.

FIG. 10 is a third example of the digital video signal processing device of the present invention.
It is a circuit block diagram of an example.

11 is a first operation timing chart for explaining the operation of the digital video signal processing device illustrated in FIG.

12 is a second operation timing chart for explaining the operation of the digital video signal processing device illustrated in FIG.

FIG. 13 is a circuit configuration diagram of a conventional serial / parallel converter.

FIG. 14 is an operation timing diagram illustrating an operation of the serial / parallel converter illustrated in FIG.

FIG. 15 is a circuit configuration diagram of a conventional parallel / serial converter.

16 is an operation timing diagram illustrating an operation of the parallel / serial converter illustrated in FIG.

FIG. 17 is a configuration diagram of an arithmetic processing unit.

FIG. 18 is a circuit configuration diagram of a conventional digital video signal processing device.

19 is an operation timing diagram illustrating an operation of the digital video signal processing device illustrated in FIG.

FIG. 20 is a MUSE format.

[Explanation of symbols]

 100, 100A, 100B ··· shift register circuit 200, 200A, 200B · · memory circuit 300, 300A, 300B · · arithmetic circuit 400, 400A · · address decoding circuit 500, 500A · · control circuit R · · register H, G ..1 bit unit time delay element

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location G06T 1/00 G06F 15/80 G11C 19/00 B (72) Inventor Masuyoshi Kurokawa 6 Kita-Shinagawa, Shinagawa-ku, Tokyo No. 7-35 Sony Corporation (72) Inventor Takao Yamazaki 6-7 Kita-Shinagawa, Shinagawa-ku, Tokyo No. 35 Sony Corporation (72) In-house Seiichiro Iwase 6-7 Kita-Shinagawa, Shinagawa-ku, Tokyo No. 35 Sony Corporation

Claims (20)

[Claims] 1. A serial / parallel converter for periodically inputting input data consisting of M = (m + n) pieces of data per predetermined time and periodically outputting the data in parallel. m first register circuits for serially inputting m pieces of data and outputting in parallel; and m pieces of first register circuits provided in parallel with the first register circuits, and serially inputting m pieces of data and outputting in parallel M second register circuits, and n third register circuits that serially input n pieces of data and output n pieces of data in parallel, and m pieces of data are cyclically alternated with each other. Serially input to the first register circuit or the second register circuit, serially input n pieces of data to the third register circuit after the m serial data inputs, and further input the serially input M data. = (M + n) pieces of data are simultaneously output in parallel, and the number of the m pieces of register circuits is equal to the number of pieces of data of the next cycle during the parallel output. A serial / parallel converter defined by the number that can accept. 2. The number of the m register circuits is the parallel output time and M = (m +) which is periodically input.
2. The serial / parallel converter according to claim 1, which is defined by an input time interval of n) pieces of data. 3. The first register circuit, the second register circuit and the third register circuit are respectively provided with a register for storing each of the data and a write pointer provided on the input side of the register. 3. The serial / parallel converter according to claim 1, further comprising an input switch that is activated and an output switch that is activated by a write enable signal provided on the output side of the register. 4. The first register circuit, the second register circuit and the third register circuit each delay a 1-bit write pointer for energizing the input switch in accordance with the input timing of the data. A 1-bit unit time delay element, 1-bit unit time delay elements in each register circuit are connected in series, and a 1-bit first write pointer is sequentially delayed corresponding to the data input timing, and The last-stage 1-bit unit time delay element in the first register circuit and the third register circuit are configured to continuously energize corresponding input switches in the first register circuit and the third register circuit. The first-stage 1-bit unit time delay element in the register circuit is connected in series, and alternates with the application of the first write pointer in response to the data input timing. The second register so that the applied 1-bit second write pointer is sequentially delayed to continuously activate the corresponding input switches in the second register circuit and the third register circuit. 4. The serial / signal according to claim 1, wherein the last-stage 1-bit unit time delay element in the circuit and the first-stage 1-bit unit time delay element in the third register circuit are connected in series.
Parallel converter. 5. The serial / parallel converter according to claim 4, wherein the input data is a video signal for one horizontal period consisting of M (= m + n) pixel data, and the input time interval is a horizontal blanking period. . 6. A parallel / serial converter for periodically inputting input data consisting of M = (α + β) pieces of data per predetermined time and serially outputting those pieces of data. A first register circuits that input the data in parallel and serially output the data, and β second register circuits that input the β data in parallel and serially output the data, It is provided in parallel with the register circuit, and has β third register circuits that input β data in parallel and serially output, and input α data in parallel to the first register circuit. At the same time, β pieces of data are cyclically alternately input in parallel to the second register circuit or the third register circuit, and further, the first register circuit and the second or third register circuit are input. Is configured to serially output the data input to the parallel / serial converter. The number of the β register circuits is defined by the number that can receive the data of the next cycle during the parallel data input. . 7. The number of the β register circuits is defined by the parallel data input / output time and the input time interval of M = (α + β) data that are periodically input. Parallel / serial converter. 8. The first register circuit, the second register circuit and the third register circuit are respectively provided with a register for storing each of the data and a write enable signal provided on the input side of the register. 7. An input switch that is energized and an output switch that is provided on the output side of the register and that is energized by a read pointer.
Or the parallel / serial converter described in 7. 9. The first register circuit, the second register circuit and the third register circuit each delay a 1-bit read pointer for energizing the output switch in accordance with the input timing of the data. A 1-bit unit time delay element, the 1-bit unit time delay elements in each register circuit are connected in series, the read pointer applied to the data output timing is sequentially delayed, and the first register 1-bit unit time delay element at the final stage in the first register circuit and 1 at the first stage in the second register circuit so as to energize the circuit and the corresponding output switch in the second register circuit. A bit unit time delay element is connected in series, and the read pointer is sequentially delayed at the data output timing next to the data output timing. 1 bit unit time delay element of the last stage in the first register circuit and the third register circuit so as to energize the corresponding output switch in the first register circuit and the third register circuit. 9. The parallel / serial converter according to claim 6, wherein the first-stage 1-bit unit time delay element is connected in series. 10. The parallel / serial converter according to claim 9, wherein the input data is a video signal for one horizontal period composed of M (= α + β) pixel data, and the input time interval is a horizontal blanking period. . 11. A predetermined time M = (m + n) = (α
6. An arithmetic processing unit for inputting input data consisting of + β) data serially, arithmetically processing the data in parallel, and serially outputting the arithmetic result, wherein / Parallel converter, processor means having M processor elements for independently processing data output from the serial / parallel converter, and serially inputting M operation results of the processor means in parallel An arithmetic processing device comprising: the parallel / serial converter according to claim 6. 12. An arithmetic processing device for serially inputting input data consisting of M pieces of data per predetermined time, arithmetically processing these M pieces of data in parallel, and outputting the parallel arithmetic results serially. A first register circuit for inputting N = M / 2 pieces of data serially and outputting in parallel and inputting N pieces of parallel data and outputting serially, N = M / 2 pieces of data serially A second register circuit for inputting to and outputting in parallel, and N parallel data for inputting and serially outputting, and the first half N data to the first register circuit for parallel output, A serial / parallel mutual converter having control means for inputting the latter half N pieces of data to the second register circuit and outputting them in parallel, and the N pieces of data from the first register circuit. First arithmetic circuit means for receiving the real data, performing a predetermined arithmetic operation on the received parallel data, and transmitting the arithmetic result to the first register circuit; and N parallel data from the second register circuit. And second arithmetic circuit means for receiving a predetermined arithmetic operation on the received parallel data and transmitting the arithmetic result to the second register circuit, wherein the control means includes the first register circuit. And the second register circuit are operatively connected in series, and the calculation result output from the first calculation circuit means is received in the first register circuit and serially output, and the second calculation circuit means outputs the calculation result from the second calculation circuit means. An arithmetic processing unit that receives the output arithmetic result in the second register circuit and serially outputs the serial output of the first register circuit. 13. The first arithmetic circuit means includes N memory circuits for receiving parallel data from the first register circuit, and N arithmetic circuits for performing a predetermined arithmetic operation on the received parallel data. And sends the operation result to the first register circuit via the memory circuit or directly, and the second operation circuit means receives N parallel data from the second register circuit. 2. A memory circuit and N arithmetic circuits for performing a predetermined arithmetic operation on the received parallel data, and outputs the arithmetic result to the second register circuit via the memory circuit or directly.
The arithmetic processing unit according to 2. 14. The first register circuit and the second register circuit.
Register circuits for storing the data, a first input switch for inputting the serial input data to the corresponding register, and a first output for outputting the data stored in the register to the arithmetic circuit means. A switch, a second input switch for inputting a calculation result from the calculation circuit means to the register, and a second output switch for outputting a calculation result stored in the register, wherein the first input switch is the It is energized in response to the input timing of serial input data, the first output switch is energized according to the parallel output timing to the arithmetic circuit means, and the second input switch is operated by the arithmetic circuit means. The device is energized in response to an output timing, and the second output switch is energized according to the serial output timing. 13. The arithmetic processing unit according to 13. 15. An arithmetic processing device which inputs serially input data consisting of M data per predetermined time, arithmetically processes these M data in parallel, and serially outputs the parallel arithmetic result. A first serial / parallel converter for inputting N = M / 2 data serially and outputting in parallel, and a second serial / parallel converter for inputting N = M / 2 data serially and outputting in parallel Serial / parallel converter, a first parallel / serial converter that inputs N parallel data and serially outputs, and a second parallel / serial that inputs N parallel data and serially outputs The converter and N parallel data from the first serial / parallel converter are received, a predetermined operation is performed on the received parallel data, and the operation result is obtained. The first parallel /
First arithmetic circuit means for sending to the serial converter, and N parallel data from the second serial / parallel converter are received, a predetermined arithmetic operation is performed on the received parallel data, and the arithmetic result is obtained. Second parallel /
Second arithmetic circuit means for sending to the serial converter, and N serial input data of the first half are input to the first serial / parallel converter, and N serial input data of the second half are input to the second serial. / Parallel converter, serially outputs the operation result stored in the first parallel / serial converter, serially outputs the operation result, and then stores in the second parallel / serial converter. An arithmetic processing unit having a control means for serially outputting an arithmetic result. 16. The first arithmetic circuit means includes N memory circuits for receiving parallel data from the first serial / parallel converter, and N memory circuits for performing a predetermined arithmetic operation on the received parallel data. An arithmetic circuit, and sends the arithmetic result to the first parallel / serial converter via the memory circuit or directly, and the second arithmetic circuit means includes the second serial / parallel converter. And N arithmetic circuits for receiving parallel data from the second parallel data, and N arithmetic circuits for performing a predetermined arithmetic operation on the received parallel data, and the arithmetic result is directly or through the memory circuit. The arithmetic processing device according to claim 15, wherein the arithmetic processing device outputs the data to a parallel / serial converter. 17. The first serial / parallel converter and the second serial / parallel converter, respectively.
A register for storing the input data, an input switch for inputting the serial input data to the corresponding register,
An output switch for outputting the data stored in the register to the arithmetic circuit means, each of the first parallel / serial converter and the second parallel / serial converter is a register for storing the arithmetic result. An input switch for inputting the operation result to the register and an output switch for serially outputting the data stored in the register, wherein the input switch of the serial / parallel converter responds to an input timing of the serial input data. The output switch of the serial / parallel converter is activated in accordance with the parallel output timing to the arithmetic circuit means, and the input switch of the parallel / serial converter is activated to the arithmetic output timing of the arithmetic circuit means. In response, the output switch of the parallel / serial converter is activated. Processor of claim 16 is biased depending on real output timing. 18. An arithmetic processing unit for inputting input data consisting of M pieces of data per predetermined time serially, arithmetically processing these M pieces of data in parallel, and outputting the parallel arithmetic results serially. , Input M data serially and output in parallel,
A first serial / parallel mutual conversion circuit for inputting M pieces of parallel data and outputting serially, and inputting M pieces of data serially and outputting in parallel,
A second serial / parallel mutual conversion circuit for inputting M parallel data and serially outputting the same, and selecting the first input data or the second input data to the second serial / parallel mutual conversion circuit. The M input parallel data from the input data selection circuit for outputting and the first serial / parallel mutual conversion circuit or the second serial / parallel mutual conversion circuit is received, and a predetermined operation is performed on the received parallel data. Arithmetic circuit means for sending the operation result to the first serial / parallel mutual conversion circuit or the second serial / parallel mutual conversion circuit, and the first serial / parallel mutual conversion circuit or the second serial / Output data selection circuit for selecting serial output data from the parallel / parallel conversion circuit. 19. The arithmetic circuit means includes M memory circuits for receiving parallel data from the first or second serial / parallel mutual conversion circuit, and N memory circuits for performing a predetermined arithmetic operation on the received parallel data. 18. The arithmetic processing device according to claim 17, further comprising: an arithmetic circuit for transmitting the arithmetic result to the first or second serial / parallel mutual conversion circuit via the memory circuit or directly. 20. The first or second serial / parallel mutual conversion circuit respectively stores a register for storing the data, a first input switch for inputting the serial input data to the corresponding register, and a storage for the register. A first output switch for outputting the calculated data to the arithmetic circuit means, a second input switch for inputting the arithmetic result from the arithmetic circuit means to the register, and a second output switch for outputting the arithmetic result stored in the register Output switch, the first input switch is activated in response to an input timing of the serial input data, and the first output switch is activated in response to a parallel output timing to the arithmetic circuit means. The second input switch is activated in response to a calculation output timing of the calculation circuit means, and the second output switch is The arithmetic processing unit according to claim 18, wherein the arithmetic processing unit is energized according to the serial output timing.