JPH07303017A - Power amplifier and high frequency semiconductor device - Google Patents

Abstract

PURPOSE:To provide a power amplifier whose operating frequency and operating biasing point can be varied. CONSTITUTION:An MMIC 110 is formed by integrating two stages of FETs 112, 114, three matching circuit parts 111, 113 and 115, and two gate bias resistors 116, 117. A drain bias circuit part 101 and a gate bias circuit part 102 are formed on a packaging substrate 100, and they are connected to drain voltage supply terminals 121, 122 and gate voltage supply terminals 123, 124, respectively. A signal is inputted from a signal input terminal 126, and is outputted from a signal output terminal 127. The operating frequency can be adjusted by changing the position of a bypass capacitor on the transmission line of the drain bias circuit part 101, etc. The operating biasing point can be adjusted by applying a gate bias by resistor division using a variable resistor in the gate bias circuit part 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier using an FET mounted on a GaAs substrate used for mobile communication or the like, and more particularly to a power amplifier capable of changing an operating frequency and an operating bias point. Is.

[0002]

2. Description of the Related Art In recent years, various mobile communication systems have been studied in various countries around the world, and a power amplification device for transmission corresponding to each system has been demanded.

Conventionally, as a power amplification device for transmission in this field, a module using GaAs MESFET, JFET or HBT, an integrated type integrated circuit (hereinafter referred to as MM).
Various configuration examples of (referred to as IC) have been reported. For example, in a general MMIC structure, since the band gap of GaAs is wide and the electrical conductivity of intrinsic GaAs is low even at room temperature, it is possible to obtain a semi-insulating GaAs substrate. Etc., and active elements such as spiral inductors, interdigital capacitors, MIM capacitors, transmission lines, thin film resistors, and other passive elements are integrated and integrally formed. Also,
As disclosed in IEEE GaAs IC sympo. Tech. Digest pp.53-56 1993, a module (multichip IC) in which an MMIC incorporating the above-described active element and passive element is formed inside a package and mounted on a substrate. Has been reported. Then, this MMIC or module is mounted on a substrate and applied to various uses. In other words, when assembled using a single transistor and individual components, if the operating frequency becomes high, a large variation in microwave characteristics will occur due to errors in the mounting position of the components and variations in the characteristics of the components themselves, leading to a high manufacturing yield. Although it is lowered, by configuring such an MMIC or module, it is possible to stably exhibit predetermined characteristics.

[0004]

[Problems to be Solved by the Invention] However, on the other hand,
The above-mentioned conventional MMIC and module have the following problems. That is, since these are designed only for a specific system, there are cases where satisfactory characteristics cannot be obtained when the operating frequency is changed and used. Further, the operating bias point or operating class (eg, class A, class B, etc.) of the FET cannot be changed externally. For example, the above IEEE GaAs IC sympo. Tech. Di.
In the module shown in gest pp.53-56 1993, it is impossible to change the operating frequency and the operating bias point from the outside because all the circuit blocks are formed inside the package.

In the MMIC and the module, G
Expensive GaA due to the large occupied area of passive elements such as capacitors and inductances mounted on the aAs substrate.
There is a problem that the chip size of the s substrate becomes large and it is difficult to reduce the manufacturing cost.

The present invention has been made in view of the above problems, and a first object thereof is to improve the operating frequency of the MMIC when incorporating it in a mounting board without causing characteristic variations. An object of the present invention is to provide an amplifier configured so that adjustment can be performed accordingly.

A second object is to reduce the manufacturing cost by reducing the area occupied by the compound semiconductor substrate in a high frequency circuit using an expensive compound semiconductor substrate or a power amplifier equipped with this high frequency circuit. Especially.

[0008]

In order to achieve the above-mentioned first and second objects, in the present invention, in the MMIC and the MMI.
By dividing and forming the circuit section constituting the power amplifier on the substrate on which C is mounted, the operating frequency and the operating bias point are made variable.

Specifically, the measures of claims 1 to 24 are taken.

The means taken by the invention of claim 1 is premised on a power amplifier provided with an integrated circuit in which an active element, a passive element and the like are integrally formed, and a substrate for mounting the integrated circuit. The power amplifier includes at least one FET formed of a gate electrode, a drain electrode and a source electrode in the integrated circuit for amplifying a high frequency signal, and a voltage is applied to the drain electrode of the FET provided in the integrated circuit. A drain voltage supply terminal for supplying, a drain power supply section provided on the substrate outside the integrated circuit and connected to the drain voltage supply terminal, and a drain of the FET provided on the substrate outside the integrated circuit section An impedance adjusting member for adjusting the impedance of the drain power source viewed from the electrode is provided.

The means implemented by the invention of claim 2 is as follows:
In the power amplifier described above, the impedance adjusting member is provided on a substrate outside the integrated circuit, and is connected between the drain voltage supply terminal and the drain power supply section, and a transmission line for transmitting a high frequency signal. , A capacitor mounting portion which is provided on the substrate outside the integrated circuit, is configured such that the capacitor can be mounted between the ground of the substrate and the transmission line, and the mounting portion can be changed,
The operating frequency can be changed by changing the mounting portion of the capacitor.

The measures taken by the invention of claim 3 are as follows:
In the power amplifier described, the capacitor mounting portion,
It is formed by opening a protective film of the transmission line at a plurality of points on the transmission line.

The means taken by the invention of claim 4 is as follows:
Alternatively, the power amplifier according to the third aspect is configured such that a capacitor is attached to the capacitor attaching portion.

The means taken by the invention of claim 5 is claim 1
In the power amplifier described above, the impedance adjusting member is provided on the substrate outside the integrated circuit, between the drain voltage supply terminal and the drain power supply unit, and both ends thereof are the drain voltage supply terminal and the drain power supply unit. Each of the inductors is connected to an inductor mounting portion for mounting an inductor, and the operating frequency can be changed by changing the inductance value of the inductor.

The means implemented by the invention of claim 6 is as defined in claim 5.
In the power amplifier described above, a capacitor provided between the drain voltage supply terminal and the ground of the substrate is further provided on the substrate outside the integrated circuit.

The means taken by the invention of claim 7 is claim 5
Alternatively, in the power amplifier described in 6, the inductor is attached to the inductor attachment portion.

The means taken by the invention of claim 8 is premised on a power amplifier provided with an integrated circuit in which an active element, a passive element and the like are integrally formed, and a substrate for mounting the integrated circuit. Further, the power amplifier includes at least one FE for amplifying a high frequency signal, which includes a gate electrode, a drain electrode and a source electrode provided in the integrated circuit.
T, a gate voltage supply terminal provided in the integrated circuit for supplying a voltage to the gate electrode of the FET, first and second gate power supply units provided on a substrate outside the integrated circuit, First and second resistance members are provided respectively between the gate voltage supply terminal and the first and second gate power supply units, and at least the second resistance member of the two resistance members is The variable resistor is provided on a substrate outside the integrated circuit, and the operation bias point of the FET can be changed by changing the resistance value of the variable resistor.

The means taken by the invention of claim 9 is the power amplifier according to claim 1, 2, 3, 4, 5, 6 or 7, wherein a voltage is applied to the gate electrode of the FET provided in the integrated circuit. Between the gate voltage supply terminal for supplying, the first and second gate power supply units provided on the substrate outside the integrated circuit, and the gate voltage supply terminal and the first and second gate power supply units A first resistance member and a second resistance member which are respectively interposed, and at least the second resistance member of the two resistance members is provided.
The resistance member is a variable resistor provided on the substrate outside the integrated circuit, and the F is obtained by changing the resistance value of the variable resistor.
The configuration is such that the operation bias point of ET can be changed.

According to a tenth aspect of the present invention, in the power amplifier according to the eighth or ninth aspect, the FET is composed of a front-stage FET and a rear-stage FET, and the power amplifier functions as a two-stage power amplifier. , The gate voltage supply terminal is connected to the front FET gate voltage supply terminal and the rear FE
T gate voltage supply terminal, the first gate power supply section is a front FET gate power supply section connected to the front FET gate voltage supply terminal, and the second gate power supply section is a rear FET gate voltage supply terminal. Rear stage F to be connected
The second resistance member, which is the variable resistor, is used as an ET gate power supply unit between the front-stage FET gate voltage supply terminal and the front-stage FET gate power supply unit, and the rear-stage FET gate voltage supply terminal and the rear-stage FET gate power supply unit. And the first resistance member is provided between the front-stage FET gate voltage supply terminal and the front-stage FET gate power supply unit, and the rear-stage FET gate voltage supply terminal and the rear-stage FET. It is provided on the other side of the gate power supply section.

The means taken by the invention of claim 11 is the power amplifier according to claim 10, wherein the front-stage FET gate voltage supply terminals and the rear-stage FET gate voltage supply terminals are connected via a third fixed resistor. It is connected.

According to a twelfth aspect of the present invention, in the power amplifier according to the eighth, ninth, tenth or eleventh aspect, a fixed resistor is provided between the gate electrode of the FET and the gate voltage supply terminal. It was done.

The means taken by the thirteenth aspect of the invention is based on a power amplifier provided with an integrated circuit in which active elements, passive elements and the like are integrally formed, and a substrate for mounting the integrated circuit. The power amplifier includes at least one FET provided in the integrated circuit, the gate electrode, the drain electrode, and the source electrode for amplifying a high-frequency signal.
A gate voltage supply terminal provided in the integrated circuit for supplying a voltage to a gate electrode of the FET, first and second gate power supply units provided on a substrate outside the integrated circuit, and the gate First and second resistance members provided respectively between the voltage supply terminal and the first and second gate power supply units are provided, and at least the second resistance member of the two resistance members is provided.
The resistance member is a fixed resistor attached to a resistor attachment portion provided between the gate voltage supply terminal and the second gate power supply portion on the substrate outside the integrated circuit, and the resistance of the fixed resistor is set. The operation bias point of the FET can be changed by changing the value.

According to a fourteenth aspect of the present invention, in the power amplifier according to the first, second, third, fourth, fifth, sixth or seventh aspect, a voltage is applied to the gate electrode of the FET provided in the integrated circuit. Between the gate voltage supply terminal for supplying, the first and second gate power supply units provided on the substrate outside the integrated circuit, and the gate voltage supply terminal and the first and second gate power supply units A first resistance member and a second resistance member which are respectively interposed, and at least the second resistance member of the two resistance members is provided.
The resistance member is a fixed resistor attached to a resistor attachment portion provided between the gate voltage supply terminal and the second gate power supply portion on the substrate outside the integrated circuit, and the resistance of the fixed resistor is The operation bias point of the FET can be changed by changing the value.

According to a fifteenth aspect of the present invention, in the power amplifier according to the fourteenth aspect, the FET is provided in the front stage FE.
T and a post-stage FET, the power amplifier functions as a two-stage power amplifier, and the gate voltage supply terminal is formed of a front-stage FET gate voltage supply terminal and a rear-stage FET gate voltage supply terminal, and the first gate power supply is provided. The supply unit is a front-stage FET gate power supply unit connected to the front-stage FET gate voltage supply terminal, and the second gate power supply unit is a rear-stage FET connected to the rear-stage FET gate voltage supply terminal.
A resistor mounting portion serving as a gate power source portion, to which the second resistance member is attached, is provided between the front stage FET gate voltage supply terminal and the front stage FET gate power source portion, and the rear stage FET.
The first resistance member is interposed between the gate voltage supply terminal and the second-stage FET gate power supply section,
The above-mentioned previous-stage FET gate voltage supply terminal and the above-mentioned previous-stage FE
The fixed resistor is provided between the T-gate power supply unit and the other of the latter-stage FET gate voltage supply terminal and the latter-stage FET gate power supply unit.

According to a sixteenth aspect of the present invention, in the power amplifier according to the fifteenth aspect, the front stage FET gate voltage supply terminal and the rear stage FET gate voltage supply terminal are connected via a third resistor. It is a thing.

According to a seventeenth aspect of the present invention, means is provided in the power amplifier according to the thirteenth, fourteenth, fifteenth or sixteenth aspect.
A fixed resistor is further provided between the gate electrode of the FET and the gate voltage supply terminal.

According to the eighteenth aspect of the present invention, in the power amplifier according to the eighth, ninth, tenth, eleventh, twelve, thirteenth, fourteenth, fifteenth or sixteenth aspect, the first resistor member is integrated with the integrated resistor. The second FET is provided in the circuit and includes a drain electrode connected to the gate electrode of the first FET, a gate electrode, and a source electrode connected to the gate electrode.

The means taken by the nineteenth aspect of the invention is premised on a power amplifier provided with an integrated circuit in which active elements, passive elements and the like are integrally formed, and a substrate for mounting the integrated circuit. The power amplifier includes a first electrode for amplifying at least one high-frequency signal, which includes a gate electrode, a drain electrode, and a source electrode provided in the integrated circuit.
FET and the first FET provided in the integrated circuit
Second F comprising a drain electrode connected to the gate electrode of the second electrode, a gate electrode and a source electrode connected to the gate electrode
ET and the first and second F provided in the integrated circuit.
First and second gate voltage supply terminals for supplying a voltage to the gate electrode of ET, respectively, and the second FET provided on the substrate outside the integrated circuit, the first FET being connected to the first voltage supply terminal.
A first gate power supply section connected via a first gate power supply section, a second gate power supply section provided on the substrate outside the integrated circuit, and connected to the second voltage supply terminal, and a second gate power supply section provided on the substrate outside the integrated circuit. And a resistor interposed in the path from the connection between the gate electrode of the first FET and the drain electrode of the second FET to the second gate power supply unit.

According to a twentieth aspect of the present invention, in the power amplifier according to the first, second, third, fourth, fifth, sixth or seventh aspect, the means is provided in the integrated circuit and connected to the gate electrode of the FET. A second FET for setting the gate bias of the FET and a gate electrode of the FET and the second FET which are provided in the integrated circuit and which are formed of a drain electrode, a gate electrode and a source electrode connected to the gate electrode. First and second gate voltage supply terminals for supplying voltages, respectively, and a first gate power supply section provided on the substrate outside the integrated circuit and connected to the first voltage supply terminal via the second FET. A second gate power supply unit provided on the substrate outside the integrated circuit and connected to the second voltage supply terminal; and a second gate power supply unit provided on the substrate outside the integrated circuit,
A resistor provided in the path from the connection between the gate electrode of the FET and the drain electrode of the second FET to the second gate power supply section is provided.

According to a twenty-first aspect of the invention, in the power amplifier according to the nineteenth or twentieth aspect, the high-frequency signal amplification FET is composed of a front-stage FET and a rear-stage FET,
The power amplifier is caused to function as a two-stage power amplifier, and the first gate voltage supply terminal is composed of a front stage FET gate voltage supply terminal and a rear stage FET gate voltage supply terminal, and the front stage FET gate voltage supply terminal and the rear stage F
Either one of the ET gate voltage supply terminals is connected to the second
A FET connected to the first gate power supply via the FET, and the other of the front FET gate voltage supply terminal and the rear FET gate voltage supply connected to the second gate power supply via the resistor. is there.

According to a twenty-second aspect of the present invention, in the power amplifier according to the nineteenth, twentieth or twenty-first aspect, a resistor provided between the first gate voltage supply terminal and the second power source is provided. The variable resistor is configured so that the operating bias point of the high frequency signal amplification FET can be changed by changing the resistance value of the variable resistor.

According to a twenty-third aspect of the present invention, in the power amplifier according to the nineteenth or twentieth aspect, a fixed resistor is interposed between the gate electrode of the high frequency signal amplification FET and the first gate voltage supply terminal. It was set up.

According to a twenty-fourth aspect of the present invention, in the power amplifier according to the twenty-first aspect, between the gate electrode of the preceding stage FET and the preceding stage FET gate voltage supply terminal, and the gate electrode of the following stage FET and the above. A resistor is provided between each of the latter-stage FET gate voltage supply terminals.

In order to achieve the above second object, the present invention takes measures in claims 25 to 31.

The means taken by the twenty-fifth aspect of the invention is premised on a high-frequency semiconductor device having an integrated circuit in which an active element, a passive element and the like are integrally formed on a substrate. In the high frequency semiconductor device, at least one of a gate electrode, a drain electrode and a source electrode provided in the integrated circuit is provided.
FETs, a matching circuit provided in the integrated circuit for matching a high-frequency signal passing through the FETs, a source wiring extracted in a direction substantially perpendicular to the longitudinal direction of the gate electrode of the FETs, and the source wiring And a source pad which is adjacent to both ends of the gate electrode of the FET in the longitudinal direction and is located in a region located on the side of the semiconductor substrate.

According to a twenty-sixth aspect of the present invention, in the high-frequency semiconductor device according to the twenty-fifth aspect, the source pads are provided at four or more places.

According to a twenty-seventh aspect of the present invention, in the high frequency semiconductor device according to the twenty-fifth or twenty-sixth aspects, the source electrode of the FET is grounded via the ground of the source pad.

The means taken by the twenty-eighth aspect of the invention is premised on a high-frequency semiconductor device provided with an integrated circuit in which an active element, a passive element and the like are integrally formed on a substrate. In the high frequency semiconductor device, at least one of a gate electrode, a drain electrode and a source electrode provided in the integrated circuit is provided.
Two FETs, a source wiring extending in a direction substantially perpendicular to the longitudinal direction of the gate electrode of the FET, and a source wiring connected to the FET and adjacent to both ends of the FET in the longitudinal direction and at both ends of the semiconductor substrate. And a FET provided in the integrated circuit
And a matching circuit for matching a high-frequency signal passing therethrough, and a capacitor of the matching circuit is arranged in a region adjacent to the source pad.

According to a twenty-ninth aspect of the present invention, in the high-frequency semiconductor device according to the twenty-eighth aspect, a matching circuit for matching a high-frequency signal passing through the FET is used,
The ET is arranged in a region adjacent to the FET on both sides of the gate electrode in the longitudinal direction.

According to a thirtieth aspect of the present invention, in a high frequency semiconductor device in which an active element and a matching circuit element are formed on a semiconductor substrate, the means comprises a gate electrode, a drain electrode and a source electrode provided in the integrated circuit. At least 1
Two FETs, an output pad connected to the drain electrode of the FET on one side of the semiconductor substrate, and a side of the substrate different from the side on which the output pad is disposed, An external drain pad for applying a power supply voltage is provided to the drain electrode.

The means taken by the invention of claim 31 is the high frequency semiconductor device according to claim 25, 26, 27, 28, 29 or 30, and is arranged on one side of the semiconductor substrate connected to the drain electrode of the FET. And an external drain pad for applying a power supply voltage to the drain electrode of the FET, the output pad being disposed on a side different from the side where the output pad is disposed on the substrate. It was done.

[0042]

With the above construction, the following actions are achieved in the inventions of the respective claims.

According to the first aspect of the invention, since the impedance adjusting member serving as the drain bias circuit section is formed on the mounting board, the operating frequency can be changed on the mounting board which cannot be easily performed by the conventional module and MMIC. It becomes possible and can be used at different operating frequencies. Also,
Since the drain bias circuit section is provided on the mounting substrate, the parasitic resistance of the drain bias circuit section is significantly reduced as compared with the case where the drain bias circuit is formed inside an integrated circuit such as an MMIC. Therefore, the power supply voltage is transmitted to the drain electrode of the FET without being subjected to the voltage drop due to the drain bias circuit section, the deterioration of the saturation output characteristic is suppressed, and the decrease of the gain and efficiency is suppressed as compared with the conventional integrated circuit. . Furthermore, by mounting a member that occupies a large area, such as a transmission line, a capacitor, and an inductor, on the mounting board side, it becomes possible to reduce the area that the integrated circuit occupies, and high-frequency power using an expensive compound semiconductor substrate. The cost of the amplifier will also be reduced.

According to the present invention, the impedance of the drain power source side viewed from the drain electrode of the FET changes by changing the mounting position of the capacitor in the transmission line on the mounting substrate outside the integrated circuit. . Therefore, the action of claim 1 is achieved.

According to the fifth, sixth or seventh aspect of the invention, the impedance on the drain power source side viewed from the drain electrode of the FET changes by changing the inductance value of the inductor. Therefore, the action of claim 1 is achieved.

According to the eighth aspect of the invention, when the resistance value of the second resistance member composed of the variable resistor is changed, the voltage supplied from one of the first power source and the second power source becomes the FET.
Of the FET and the other of the first power supply and the second power supply, the operating bias point of the FET is changed on the mounting substrate. By changing the operation bias point, it becomes possible to change the class A operation-class B operation or the like so as to suit the system using the integrated circuit. Further, even if there is a change in the threshold value of the FET in manufacturing, the change in the operating bias point and the accompanying change in the input and output impedances of the FET are suppressed by adjusting the resistance value of the variable resistor or the like.
The yield of integrated circuits is improved and the cost of power amplifiers is also reduced. Further, since some variation in the threshold value of the FET is allowed, it is possible to increase the design margin.

In the invention of claim 9, it is possible to change the operating frequency and the operation class, and the effects of the invention of claim 8 and the effects of the inventions of claims 1 to 7 are obtained together. To be

According to the tenth aspect of the invention, the operation of the eighth or ninth aspect of the invention can be obtained while ensuring a high gain by the two-stage power amplifier. In that case, although the first and second power supplies are fixed power supplies, by changing the resistance value of the second resistance member, the operation bias points of the front-stage FET and the rear-stage FET can be changed, so that the configuration is simplified. .

According to the eleventh aspect of the present invention, it is possible to change the operation bias point between the pre-stage FET and the post-stage FET by, for example, setting each FET in a different operation class.

According to the twelfth aspect of the present invention, since the fixed resistor provided in the integrated circuit blocks the transmission of the high frequency signal in the integrated circuit to the outside, the integration is performed by changing the resistance value of the second resistance member. The influence on the matching condition in the circuit is suppressed.

According to the inventions of claims 13, 14, 15, 16 and 17, by changing the resistance value of the fixed resistor mounted on the resistor mounting portion, the above-mentioned claims 8, 9, 10 and 1 respectively.
The same effects as those of the inventions 1 and 12 can be obtained.

In the eighteenth aspect of the present invention, when the idle current fluctuates due to variations in the threshold of the high frequency signal amplifying FET, the idle current of the second FET formed in the same integrated circuit as the FET also changes accordingly. Therefore, it is possible to control so as to automatically reduce the variation in the idle current of the high-frequency signal amplification FET by utilizing the change in the idle current of the second FET.

In the nineteenth aspect of the present invention, when the idle current of the first FET, which is a high-frequency FET, increases due to the variation in the threshold value, the idle current of the second FET also increases at the same time. When the second power supply current flows from the first power supply, a voltage drop occurs in the resistor, and the gate potential of the first FET connected downstream of the resistor drops. Therefore, the idle current of the first FET is automatically controlled to decrease. Also, due to the variation in threshold,
When the idle current of the FET becomes excessively small, the idle current of the first FET is automatically controlled to increase by the action opposite to the above action. That is, the variation in the idle current of the first FET caused by the variation in the process is suppressed.

According to a twentieth aspect of the present invention, the above first to seventh aspects are provided.
The function of the invention of (1) and the function of the invention of (19) are obtained together.

According to the twenty-first aspect of the invention, variations in the idle current of both the front-stage FET and the rear-stage FET of the two-stage power amplifier are suppressed.

In the twenty-second aspect of the present invention, the nineteenth to twenty-first aspects are provided.
In addition to the effect of the invention of (1), the operation class can be changed by changing the operation bias point of the high frequency signal amplifying FET using the variable resistor. In particular, by adjusting the resistance value of the variable resistance resistor, variations in the idle current due to fluctuations in the threshold value are suppressed, so variations in the idle current due to variations in the manufacturing process, etc. can be suppressed to an extremely small value. Become.

In the twenty-third and twenty-fourth aspects of the present invention, since the fixed resistor provided in the integrated circuit blocks the transmission of the high frequency signal in the integrated circuit to the outside, the resistance value of the second resistance member is changed. The influence on the matching condition in the integrated circuit due to is suppressed.

In the twenty-fifth aspect of the invention, since the source pad occupying a large area is arranged in the regions located at both ends of the gate electrode of the FET in the longitudinal direction and at the sides of the semiconductor substrate, the central portion of the semiconductor substrate is provided. It is possible to create a large space in the area. That is, even if the area of the semiconductor substrate is reduced, a space for arranging a matching circuit composed of a larger inductor is secured, so that it can be used for an expensive compound semiconductor substrate such as a semi-insulating GaAs substrate used in a high frequency semiconductor device. The cost spent is reduced.
Further, since the connection length between the wire and the wire used for grounding the source is shortened, the source inductor is reduced and the FET characteristics are improved.

According to the twenty-sixth aspect of the present invention, since the source pads are arranged at different locations, the space on the semiconductor substrate can be utilized more effectively.

According to the twenty-seventh aspect of the invention, the ground for the source pad and the ground for the source electrode are shared, so that the space on the semiconductor substrate can be used more effectively.

In the twenty-eighth aspect of the present invention, since the capacitor of the matching circuit connected to the ground of the semiconductor substrate is arranged in the region adjacent to the source pad, the high frequency signal of the matching circuit is released to the ground via the source pad. It will be possible. Therefore, it is not necessary to provide a separate ground for the capacitor, and space is saved.

According to the twenty-ninth aspect of the invention, since the matching circuit is arranged in the space between the source pads, the space on the semiconductor substrate is effectively utilized.

According to the thirtieth or thirty-first aspect of the invention, since the external drain pad is arranged separately from the output pad, the high frequency signal does not drop to the drain through the inductor and the capacitor. Will be applied.

[0064]

EXAMPLES Examples of the present invention will be described below.

(First Embodiment) First, a two-stage power amplifier according to the first embodiment will be described with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of the two-stage power amplifier according to the first embodiment. As shown in the figure, the two-stage power amplifier according to the present embodiment has M mounted on the mounting substrate 100.
The MIC 110 is mounted, and the drain bias circuit unit 101 and the gate bias circuit unit 102 are further mounted on the mounting substrate 1.
It is formed by being mounted on 00. This is a feature of this embodiment.

In the MMIC 110, the input matching circuit section 111, the pre-stage FET 112, the inter-stage matching circuit section 113, the post-stage FET 114, the output matching circuit 115, the pre-stage FET gate bias resistor 116 and the post-stage FET gate bias resistor 117. Is provided. Originally, all of these elements and circuit parts contribute to matching and become a part of the matching circuit part, but here, in order to clearly explain the effect, they are called as described above. Also, each code 12
1, 122, 123, 124, 125, 126, 127
Are the front-stage FET drain voltage supply terminal, the rear-stage FET drain voltage supply terminal, and the front-stage FET of the MMIC 110, respectively.
Gate voltage supply terminal, post-stage FET gate voltage supply terminal,
The ground terminal, signal input terminal, and signal output terminal are shown.

Here, the configuration of each matching circuit is as shown in FIGS. 6A, 6B and 6C, as described later.

In the conventional module and MMIC, it is difficult to adjust the operating frequency and the operating bias point from the outside because all of these elements and circuit parts are integrated in the package. However, the structure of this embodiment is used. Now you can do that easily, as explained below.

For example, the impedance of the drain bias circuit section 101 is a factor that affects the load impedance or source impedance of the FET. Therefore, the operating frequency can be changed by changing the impedance of the drain bias circuit unit 101.

On the other hand, if such a process is performed on a single FET that does not have a matching circuit, the matching condition may change, and thus the entire matching circuit may need to be changed.
However, in this embodiment, the drain bias circuit unit 101
Since the matching circuit sections 111, 113, 115 are designed at three locations in consideration of the amount of impedance change of the above, it is possible to easily use the matching circuit sections 111, 113, 115 at different frequencies simply by changing the impedance of the drain bias circuit section 101. .

An example of the configuration for setting the impedance to satisfy the matching condition according to the selection of the operating frequency will be described below.

2A and 2B are diagrams showing an example of the configuration of the drain bias circuit section 101 of this embodiment.

In the example shown in FIG. 2A, the strip line 20 which is a transmission line configured to be capable of transmitting a high frequency signal.
1, 203 and the bypass capacitors 202 and 204 constitute the drain bias circuit 101. One end of each of the strip lines 201 and 203 has a drain power source Vd.
FE connected to the other end and the other end of the front and rear FEs of the MMIC 110
The T drain voltage supply terminals 121 and 122 are respectively connected. The strip line 201 is provided with a capacitor mounting portion which is exposed without being covered with a skin serving as a protective film in advance, and the bypass capacitors 202, 2 are provided depending on the operating frequency when the MMIC 110 is used.
The mounting position of 04 is determined, and the mounting position of 04 is mounted on a portion satisfying the matching condition. Specifically, the impedance of the drain bias circuit 101 is MMIC1.
It is determined by the strip line lengths L1 and L2 from 10 to the bypass capacitors 202 and 204 (see FIG. 2A), and these can be easily changed by changing the installation positions of the bypass capacitors 202 and 204.

In the example shown in FIG. 2B, the chip inductors 205 and 207 and the bypass capacitor 2 are respectively provided.
The drain bias circuit 101 is configured by arranging 06 and 208 one by one. Each chip inductor 20
5, 207 are configured such that one end is connected to the drain power supply Vdd and the other end is connected to the front-stage or rear-stage FET drain voltage supply terminals 121 and 122 of the MMIC 110. Furthermore, the chip inductor 205,
An inductor mounting portion for mounting the bypass capacitors 206 and 208 is provided between the drain power source side end of 207 and the ground. In this example, the impedance of the drain bias circuit 101 is the chip inductor 20.
Since it is determined by the inductance value of 5,207,
The matching condition can be satisfied by mounting a chip inductor having an inductance value that matches the operating frequency when the MMIC 110 is used.

The bypass capacitor 2 used here is used.
Reference numerals 06 and 208 are inserted so that the impedance of the drain power source Vdd or its variation does not affect the FET inside the MMIC 110.
It is possible to omit the bypass capacitors 206 and 208 by designing the MMIC 110 so that the influence on the FET is within an allowable range in consideration of the impedance of dd and its variation.

As described above, in the present embodiment, the drain bias circuit 101 is formed not inside the MMIC 110 but inside the mounting substrate 100, so that the following effects can be obtained.

First, the process of changing the operating frequency, which was difficult to integrate in the MMIC 110, can be easily performed by forming the drain bias circuit section 101 on the mounting substrate 100.

Further, the drain bias circuit section 101 is set to M
By moving the inside of the MIC 110 onto the mounting substrate 100, the chip area of the MMIC 110 using an expensive GaAs substrate can be reduced, and the cost of the MMIC 110 itself can be reduced.

Further, the parasitic resistance of the drain bias circuit section 101 is the same as that of the drain bias circuit section 101 in the MMIC.
The power supply voltage is applied to the drain electrode of the FET without receiving a voltage drop due to the drain bias circuit 101 because the power supply voltage is significantly reduced as compared with the case where it is formed inside 110. Therefore, the deterioration of the saturated output characteristic is suppressed, and the decrease in gain and efficiency is suppressed as compared with the conventional MMIC.
The characteristics are improved on average, and the yield of the MMIC 110 is also improved.

In this embodiment, the drain bias circuit 101 of each stage of the two-stage power amplifier is formed on the mounting substrate 100, but the present invention is not limited to this embodiment, and at least one of them is used. Need only be formed on the mounting substrate 100. With an amplifier having one or three or more amplification stages, the same effect can be obtained even if any one or several places are formed on the mounting substrate.

Similar effects can be obtained by combining a drain bias circuit consisting of a strip line and a bypass capacitor with a chip inductor and a bypass capacitor consisting of a bypass capacitor or a chip inductor in an amplifier having two or more stages.

The gate bias circuit 102 shown in FIG. 1 affects the matching condition similarly to the drain bias circuit section 101, but high frequency adjustment is performed not only in the drain bias circuit section 101 but also in the gate bias circuit section 102. On the other hand, it is necessary to perform the processing, but on the other hand, there is a possibility that the processing may be complicated. Therefore, in the present embodiment, the gate bias circuit unit 102 is only adjusted by direct current, and the gate bias resistors 116 and 117 are formed and arranged inside the MMIC so as not to affect in high frequency, and are separated in high frequency. By doing so, the effect can be ignored. In the configuration shown in FIG. 1, the gate bias resistor 11
Although 6 and 117 are connected to the gate electrodes of the FETs 112 and 114, if they are not directly connected to the gate electrodes but are connected to inductors or resistors connected to the gate electrodes,
The effect of transmitting direct current and separating high frequencies is naturally obtained.

On the other hand, in the two-stage power amplifier having such a configuration, the FET gate voltage supply terminal 12 of each stage is
The operating bias point can be changed by applying a desired voltage to 3,124. However, it may be complicated to prepare a variable voltage source only for adjusting the gate bias, and particularly to adjust the two adjusting points individually as in the first embodiment. Therefore, next, by adjusting the resistance value at one location and the voltage source that supplies a fixed voltage, the F at two locations is adjusted.
The configuration of the gate bias circuit capable of simultaneously adjusting the ET operation bias point will be described below.

FIG. 3 is an electric circuit diagram of the gate bias circuit section 102 shown in FIG. As shown in the figure, the fixed resistors 301 and 302 and the variable resistor 303 are arranged in series between the ground and the gate power supply Vgg, and the resistance division potential of this potential difference is the gate voltage supply terminal 1 of the MMIC 110.
23 and 124 are provided. Here, the gate power source Vgg is the second gate power source unit according to claim 8, the variable resistor 303 is the second resistance member, the ground is the first gate power source unit, and the fixed resistor 301 (or 302). ) Corresponds to the first resistance member.

Next, in the present embodiment, the following effects can be obtained by forming the gate bias circuit 102 in the mounting substrate 100, not in the MMIC 110.

For example, when the FET in the MMIC 110 is a depletion type FET and the gate power supply Vgg supplies a negative potential, when the threshold value of the FET varies to the negative side, the variable resistor 303 is used. The drain current when there is no signal input (hereinafter referred to as idle current) by decreasing the value of and setting the gate bias potential to the negative side.
Can be constant. The effect on yield by making the idle current constant will be described later.

Further, even for FETs having the same threshold value, the bias point can be easily changed by the variable resistor 303. For example, class A operation (50% Idss bias) or B
Class operation (0% Idss bias), front stage FET, rear stage F
It is also possible to set ET individually. This means can be realized by a variable resistor.
It is difficult to form it inside, and it can be realized only by mounting it on a mounting board as in this embodiment.

In this embodiment, the variable resistor 303 is arranged in the gate bias circuit section 102, but the present invention is not limited to this embodiment, and the variable resistance value 3 is used.
03 is arranged as a resistor mounting part, and MMIC
When the 110 is mounted on the mounting substrate 100, a fixed resistor having a resistance value suitable for the operating frequency to be used may be attached. With such a configuration, the same effect as that of the present embodiment can be obtained, but this can be realized only by mounting the gate bias circuit section 102 on the mounting substrate 100.

In this embodiment, the matching circuit sections 111, 113 and 115 at three locations are designed in consideration of the amount of change in the impedance of the FET due to the change in the gate bias, so that they can be easily used under different gate bias conditions. It is possible.

Regarding the gate bias circuit which applies the gate potential by resistance division, the same effect can be obtained in a power amplifier having one or three or more amplification stages. In addition, it is not necessary to form and mount all the circuit elements forming the gate bias circuit section on the mounting board, and at least the mounting portion of the variable resistor or the fixed resistor is formed and mounted on the mounting board. MMI element
The same effect can be obtained even if the structure is formed on C. Further, in a power amplifier having a multi-stage configuration, the same effect can be obtained by providing gate bias circuit units for arbitrary gate bias terminals at several places.

Next, the effect of this embodiment will be described with reference to FIGS.

FIG. 4 is a frequency characteristic diagram showing the operating frequency variability when the strip line length of the preceding stage drain bias circuit is changed. In FIG. 4, the horizontal axis represents frequency (GH
z) and the vertical axis represent the forward gain S21 (dB), respectively.
The input power is about 0 dBm. As shown in FIG. 4, when the strip line length of the front stage drain bias circuit 101 is 18 mm, the maximum point of the forward gain S21 is 1.8.
What was 6 GHz, but the maximum point of forward gain S21 was 2.10 by changing the strip line length to 2 mm.
It turns out that it moves to GHz. This effect is the same in the latter stage drain bias circuit. Therefore,
Since the high frequency characteristics of the power amplifier can be adjusted on the mounting board by using the power amplifier of the present invention, the operating frequency can be changed without changing the mounting board or the MMIC. In other words, the high frequency can be adjusted after the MMIC and the mounting board are completed.
Even if there is a problem due to a deviation from 0Ω or insufficient grounding, it is possible to quickly respond. In addition, the design margin of the MMIC and the mounting board when designing the power amplifier increases,
It can be put to practical use in a short period of time.

In FIG. 5, the variable resistor 303 is used for the MMIC having 23 samples, and the sum of the idle currents of the front stage FET 112 and the rear stage FET 114 is constant (150 m).
It is a figure which shows the dispersion | variation in the operating current of a power amplifier when it adjusts so that it may become A), and the dispersion | variation in the operating current of a power amplifier when this process is not performed. The output power is 22 dBm. As shown in FIG. 5, by adjusting one position of the variable resistor 303 of the gate bias circuit 102, the variation is alleviated, the yield of the MMIC and the power amplifier is improved, and the cost thereof is reduced. Needless to say, the operation class of the FET can be easily changed.

As described above, each effect can be obtained by providing the drain bias circuit section 101 and the gate bias circuit section 102 on the mounting substrate, but by having both of them, a new effect can be obtained. Occurs. For example, in a Japanese digital cordless telephone system called PHS used in the 1.9 GHz band, since the waveform distortion becomes a problem, the FET is used in an operation close to class A. On the other hand, in the system of the digital cordless telephone used in Europe called DECT used at 1.88 GHz to 1.9 GHz, the waveform distortion is not so problematic, and the waveform distortion is used in a highly efficient operation close to class B. Therefore, if both the drain bias circuit section and the gate bias circuit section are provided on the mounting substrate, it is possible to support both systems having different operating frequencies and operating classes.

As described above in detail, the effect of the power amplifier of this embodiment is that the frequency can be adjusted on the mounting substrate, the characteristic deterioration due to the voltage drop is improved, the MMIC chip area is reduced, and the power consumption is reduced. FE improves the yield of amplifier
The operation bias point of T is changed to increase the margin in designing the mounting board. Table 1 shows a comparison with the case of using the conventional MMIC and module.

[0097]

[Table 1] Here, the conventional module refers to a module having a substrate in which a pattern for mounting individual components such as chip components and FETs is formed inside the package.

The same effect can be obtained by using an FET other than GaAs MESFET.

Here, the voltage of the power source used in this embodiment, the mounting substrate, the drain bias circuit section, the gate bias circuit section, the element values and characteristics of each element constituting the MMIC are summarized below.

The voltage Vdd of the drain power supply shown in FIG. 2 is 3.5V. The voltage Vg of the gate power supply shown in FIG.
g is -4.7V.

The mounting substrate 100 shown in FIG. 1 has a relative dielectric constant of 2.
6. A Teflon substrate having a thickness of 1 mm.

Bypass capacitors 202 and 2 shown in FIG.
Reference numerals 04, 206 and 208 are 100 pF chip capacitors, and strip lines 201 and 203 have a line width of 0.5.
and the chip inductors 206 and 208 are 1.
A 6 mm × 0.8 mm type chip inductor was used.

The fixed resistors 301 and 302 shown in FIG. 3 are chip resistors of 2.2 kΩ and 150 Ω, respectively, and the variable range of the variable resistor 303 is 300 Ω to 5 kΩ.

The front FET 112 and the rear FE shown in FIG.
T is a GaAs MESFET, and its threshold value is −
3.0V, gate width is 1mm in front FET, rear FE
At T, it is 4 mm. The gate bias resistor 116 of the front FET 112 is 1 kΩ, and the gate bias resistor 117 of the rear FET 114 is 2 kΩ.

Details of the input matching circuit section 111, the interstage matching circuit section 113, and the output matching circuit section 115 shown in FIG.
A, FIG. 6B, and FIG. 6C, respectively, between the signal input terminal 126 and the front FET gate electrode 611, and between the front FET drain electrode 612 and the rear FET gate electrode 6, respectively.
13, the FET drain electrode of the latter stage and the signal output terminal 127
The capacitor 601 is 1 pF, the inductor 602 is 6 nH, the capacitors 603 and 604 are 3 pF and 6 pF, the inductor 605 is 5 nH, the inductor 606 is 3 nH, and the capacitor 607 is 2 pF.

Although not shown because they do not contribute to matching, an input coupling capacitor and an output coupling capacitor of 100 pF are mounted on the mounting board, respectively, and are not shown in FIGS.
Was measured.

(Second Embodiment) Next, a second embodiment will be described.

FIG. 7 is an M for explaining the arrangement of the source pads of the MMIC which is the high frequency semiconductor device used in the present invention.
FIG. 8 is a plan view of the MIC700, and FIG.
3 illustrates details of the ESFET 702. A pre-stage FET that is two MESFETs on a semi-insulating GaAs substrate
701 and a post-stage FET 702 are provided, and an input matching circuit 703 is provided between the pre-stage FET and the input pad 706. The pre-stage FET 701 and the post-stage FET 7 are provided.
An interstage matching circuit 704 is provided between the second stage and the second stage
An output matching circuit 705 is arranged between the ET 702 and the output pad 707.

Gate bias pads 711, 721, drain pads 712, 722, and source pads 713, 723 are attached to the FETs 701, 702, respectively. In addition, each matching circuit 703, 704, 7
05 are spiral inductors 731 and 74, respectively
1, 751, MIM capacitors 732, 742, 74
3,752 and so on.

Here, as a feature of this embodiment, the latter-stage FE is used.
The source pad 723 of T702 is arranged at two positions at both ends of the post-stage FET 702 and both ends of the semi-insulating GaAs substrate after the source wiring is drawn out in a direction substantially perpendicular to the longitudinal direction of the gate electrode. By arranging in this manner, the wire bonding work can be performed smoothly, the grounding can be surely performed, and the source inductance is reduced by shortening the connection length of the wire and the wire used for the grounding. Therefore, FET70
The characteristics of No. 2 can be improved. Further, by disposing the source pad 723 in the vicinity of the corner of the semi-insulating GaAs substrate, the inductor having a large occupying area can be made into the semi-insulating GaA
s It is possible to create a margin for arranging inside the board,
The area can be reduced by effectively using the semi-insulating GaAs substrate.

Further, each capacitor 732, 742, 74
By connecting 3, 752 to the source pads 713, 723, respectively, space can be saved.

Further, since the drain pad 722 for taking out the output from the drain to the outside is removed from the path from the drain of the post-stage FET 702 to the output pad 127, the power supply voltage is reduced without causing a voltage drop due to passing through the inductor 751. There is an advantage that a decrease in the level of the voltage applied to the drain electrode and input to the drain electrode can be suppressed as much as possible.

As shown in the detailed structure of FIG. 8, the post-stage FET 702 includes a source electrode 7 on the gate electrode 725.
26, and a drain electrode 727 is further stacked thereon, but the gate electrode 725 and the source electrode 726 have the same extraction direction. By thus pulling out the gate electrode 725 to the source side, deterioration of characteristics due to an increase in capacitance between the gate and the drain is avoided.

(Third Embodiment) Next, a two-stage power amplifier according to the third embodiment will be described.

FIG. 9 is an electric circuit diagram showing the configuration of the two-stage power amplifier of this embodiment. The gate bias setting FET 91 is provided in the MMIC 110 according to the first embodiment shown in FIG.
1 is added, and the gate terminal 921, the source terminal 922, and the drain terminal 923 are further provided, and the mounting substrate 10
The structure of the gate bias circuit section 902 is changed and the structure of the formed gate bias circuit section 902 is changed. Here, the elements and circuit parts denoted by the same reference numerals as those shown in FIG. 1 in the figure are the same as the above-mentioned elements and circuit parts, and have the same configurations and functions.

F for gate bias setting in the present embodiment
The ET902 is composed of the front FET 112 and the rear FET 114.
Since they are formed on the same chip under the same diffusion conditions as above, they have the same variations as the variations in the idle currents of the front-stage FET 112 and the rear-stage FET 114 due to variations in threshold value, mutual conductance (gm), and the like. Also, the temperature dependence is similar. That is, the former FE
When the idle currents of T112 and the post-stage FET 114 are larger than the set target value, the gate bias setting FET 90
The idle current of 2 is also large, and conversely, when the idle currents of the front FET 112 and the rear FET 114 are smaller than the set target value, the idle current of the gate bias setting FET 911 also becomes small. That is, using this correlation,
As described below, in addition to the effects described in the first embodiment, variations in the idle current of the front-stage FET 112 and the rear-stage FET 114 due to threshold variations and temperature are suppressed.

FIG. 10 shows the structure of the gate bias circuit section 902 shown in FIG. 9, the gate bias circuit section 902, and the MMI.
It is an electric circuit diagram which shows the connection relation with FET911 for gate bias setting in C110. Gate terminal 921 and source terminal 92 of FET 911 for setting gate bias
2 is connected to the negative power source Vgg, and the drain terminal 923 is grounded via the fixed resistor 1002 and the variable resistor 1001. Also, the previous stage FET gate voltage supply terminal 1
Reference numeral 23 is connected to the drain terminal 923 of the gate bias setting FET 911, and the rear FET drain voltage supply terminal 124 is connected to the signal line between the fixed resistor 1002 and the variable resistor 1001. Here, the gate power source Vgg is the first gate power source portion according to claim 8, the gate bias setting FET 911 is the first resistance member (see claim 18), and the ground is the second gate power source portion. The variable resistor 1001 corresponds to the second resistance member.

With this structure, the front-stage FET1
When the idle current of the FET 12 and the post-stage FET 114 is excessive, a large amount of the drain current of the gate bias setting FET 911 also flows, so that the voltage drop due to the fixed resistor 1002 and the variable resistor 1001 increases, and the gate voltage of the front-stage FET 112 and the post-stage FET 114 increases. As a result, each idle current decreases. Therefore, variations in idle current can be suppressed. On the other hand, even when the idle current is too small, the reverse action increases the idle current, so that the variation of the idle current can be suppressed.

The effect of suppressing the variation of the idle current as described above is specifically, the gate bias setting FET 9
This can be achieved by appropriately setting the values of the drain current of 11, the fixed resistor 1002 and the variable resistor 1001.

The front-stage FET 112 and the rear-stage FET 11
In order to apply the gate voltage of 4 individually, the fixed resistor 100
Although 2 is inserted, the fixed resistor 1002 may be omitted if the idle current is set with the same gate voltage. Further, if the operation class is not changed, the variable resistor 1001 may be a fixed resistor.

Further, the gate bias setting FET 9
11, the front-stage FET gate voltage supply terminal 123, and the rear-stage F
The arrangement relationship with the ET gate voltage supply terminal 124 is shown in FIG.
It is not limited to the arrangement relationship shown in FIG.
The source / drain of the gate bias setting FET 911 is connected between the gate voltage supply terminal 124 and the second gate power supply unit (that is, the FET 911 is provided), and the preceding stage FET voltage supply terminal 123 is provided via a variable resistor. You may connect to a 2nd gate power supply part.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG.

As shown in FIG. 11, the structure of the MMIC 110 of the two-stage power amplifier according to this embodiment is the same as that of the MMIC 110 of the third embodiment. In this embodiment, in the gate bias circuit section, in addition to the same structure as the third embodiment, the gate bias setting FET 911 is used.
The fixed resistor 1101 is inserted in the source of the.

Generally, there is an upper limit to the current value that can be passed through the negative power supply Vgg, but if the gate width of the gate bias setting FET 911 is set too large, the third value shown in FIG.
In the configuration of the gate bias circuit unit in the embodiment, there is a possibility that a current exceeding the upper limit value may flow into the negative power supply Vgg.

However, in the structure shown in FIG. 11 of the present embodiment, the source voltage of the gate bias setting FET 911 can be made higher than the gate voltage by utilizing the voltage drop due to the fixed resistor 1101. Therefore, the drain current can be reduced, and the current flowing to the negative power source Vgg can be reduced, thus ensuring reliability.

Further, in the basic configuration shown in FIG. 9, the gate terminal 921, the source terminal 922 and the drain terminal 923 of the gate bias setting FET 911 and the preceding stage FET.
Since the gate voltage supply terminal 123 and the post-stage FET gate voltage supply terminal 124 are all formed on the mounting substrate 100 outside the MMIC 110, the gate bias circuit unit 902 can form an arbitrary circuit. Since the current value of the gate bias setting FET and the resistance value of each resistor can be set while checking the operation of
This will increase the design margin of the MMIC.

By the way, in mobile communication equipment, there are many cases in which it is desired to reduce the number of parts on the mounting substrate for downsizing. In such a case, FIGS. 12 and 1 described below will be used.
3, the configuration of the fifth, sixth and seventh embodiments shown in FIG. 14 may be adopted.

(Fifth Embodiment) FIG. 12 is an electric circuit diagram showing the structure of a part of the MMIC 110 and the gate bias circuit portion according to the fifth embodiment. In the present embodiment, the arranged member is one in which the gate electrode and the source electrode of the gate bias setting FET 911 are connected inside the MMIC 110 in the configuration of the circuit shown in FIG. 10 of the fourth embodiment. With this configuration, the work for connecting them on the mounting substrate 100 becomes unnecessary, and the MMIC 11
Since the number of pads on 0 is reduced by one, the chip size of MMIC 110 can be reduced.

(Sixth Embodiment) FIG. 13 is an electric circuit diagram showing the structure of a part of the MMIC 110 and the gate bias circuit section according to the sixth embodiment. In the present embodiment, the fixed resistor 1002 mounted on the mounting substrate 100 in the circuit shown in FIG.
The T gate voltage supply terminal and the post-stage FET gate voltage supply terminal are integrated in the MMIC 110. With this configuration, it is not necessary to mount and connect them on the mounting substrate 100, and the number of pads on the MMIC 110 can be further reduced to two.

(Seventh Embodiment) FIG. 14 is an electric circuit diagram showing the structure of a part of the MMIC 110 and the gate bias circuit section according to the seventh embodiment. In the present embodiment, the fixed resistors 1002 and 1101 mounted on the mounting substrate 100 in the circuit shown in FIG. 11 are integrated on the MMIC, and the pre-stage FET gate voltage supply terminal and the post-stage FET gate voltage supply terminal are arranged in the MMIC. It is a collection. This configuration eliminates the need for mounting and connecting them on the mounting board.
It is possible to reduce three pads on the MMIC as compared with the configuration of FIG.

The variable resistor 1001 needs to be mounted on the mounting substrate 100 in order to change the operation class of the FET. For example, in the fourth to seventh embodiments described above, the idle resistor with respect to variations in idle current is idle. If the operation class is not changed because it has the effect of suppressing the current fluctuation, it may be configured with a fixed resistor and mounted on the mounting substrate 100, or may be integrated on the MMIC 110.

(Eighth Embodiment) FIG. 15 is an electric circuit diagram showing the structure of a two-stage power amplifier according to the eighth embodiment. In this embodiment, the gate bias circuit section is integrated in the MMIC 110. That is, since it is premised that the operation class is not changed, no variable resistor is provided. Then, two fixed resistors 1201, 1 are provided between the drain of the gate bias setting FET 911 and the ground terminal 125.
202, and fixed resistors 1201 and 1202
It has a configuration in which the latter stage FET gate voltage supply terminal is connected to the signal line between them.

In this embodiment, the gate bias circuit section is incorporated into the MMIC 110 as a standard specification, and the drain bias circuit section 101 is configured to be changeable as in the first embodiment. Since only the part needs to be mounted on the mounting substrate 100, there is an advantage that a simple configuration is sufficient.

(Ninth Embodiment) FIG. 16 is an electric circuit diagram showing the structure of a two-stage power amplifier according to the ninth embodiment. In this embodiment, the gate bias circuit section is integrated in the MMIC 110 as in the eighth embodiment, and a fixed resistor is connected to the source of the gate bias setting FET 911 as in the configuration shown in FIG. 11 of the fourth embodiment. The container 1101 is inserted. Therefore, the present embodiment has an advantage that the variation of the idle current can be suppressed more reliably with a simple configuration.

Incidentally, in the above third to ninth embodiments,
The chip size is 1 mm × 2 mm. The gate width of the FET for setting the date bias is 50 μm and 5 μm.

[0136]

According to the present invention, in the power amplifier, since the impedance adjusting member serving as the drain bias circuit section is formed on the mounting substrate, the operating frequency is changed on the mounting substrate, and the drain bias. It is possible to suppress the deterioration of the saturation output characteristic, the gain, and the efficiency by reducing the parasitic resistance of the circuit portion, and to reduce the cost of the high frequency power amplifier.

According to the invention of claims 8 to 17, the gate bias of the high-frequency signal amplifying FET in the power amplifier is applied by resistance division of the power supply voltage, and the variable resistor or the resistor mounting device mounted on the mounting substrate is further applied. Since the operation bias point of the FET is changed by changing the resistance value of the resistor to the part, the operation class is changed and the yield of the integrated circuit is improved by suppressing the change of the operation bias point and the input / output impedance. It is possible to increase the design margin.

According to the eighteenth to twenty-fourth aspects of the present invention, the fluctuation of the idle current of the high frequency signal amplifying FET can be automatically adjusted through the FET, the resistor and the negative power source. It is possible to reduce the variation of the characteristics due to the variation of the above as much as possible and to stabilize the characteristics.

According to the twenty-fifth to thirty-first inventions, the MMI
By devising the arrangement of each member in C, it is possible to reduce the cost spent on an expensive compound semiconductor substrate such as a semi-insulating GaAs substrate used for a high frequency semiconductor device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a power amplifier in a first embodiment.

FIG. 2 is an electric circuit diagram of a drain bias circuit section in the first embodiment.

FIG. 3 is an electric circuit diagram of a gate bias circuit unit in the first embodiment. .

FIG. 4 is a frequency characteristic diagram showing operating frequency variability in the first embodiment.

FIG. 5 is a characteristic distribution diagram showing a yield improvement property in the first embodiment.

FIG. 6 is an electric circuit diagram of an input matching circuit section, an inter-stage matching circuit section, and an output matching circuit section in the first embodiment.

FIG. 7 is a plan view of an MMIC in the second embodiment.

FIG. 8 is an MES included in the MMIC in the second embodiment.
It is a top view of FET.

FIG. 9 is a block diagram showing a configuration of a power amplifier according to a third embodiment.

FIG. 10 is an electric circuit diagram of a gate bias circuit section in the third embodiment.

FIG. 11 is an electric circuit diagram of a gate bias circuit unit in the fourth embodiment.

FIG. 12 is an electric circuit diagram of a gate bias circuit unit in the fifth embodiment.

FIG. 13 is an electric circuit diagram of a gate bias circuit unit in the sixth embodiment.

FIG. 14 is an electric circuit diagram of a gate bias circuit unit in the seventh embodiment.

FIG. 15 is a block diagram showing a configuration of a power amplifier according to an eighth embodiment.

FIG. 16 is a block diagram showing a configuration of a power amplifier according to a ninth embodiment.

[Explanation of symbols]

 100 mounting substrate 101 drain bias circuit section 102 gate bias circuit section 110 MMIC 111 input matching circuit section 112 front stage FET 113 inter-stage matching circuit section 114 rear stage FET 115 output matching circuit section 116 gate bias resistor 117 gate bias resistor 121 front stage FET Drain voltage supply terminal 122 Rear stage FET drain voltage supply terminal 123 Front stage FET gate voltage supply terminal 124 Rear stage FET gate voltage supply terminal 125 Ground terminal 126 Signal input terminal 127 Signal output terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Osamu Ishikawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (31)

[Claims] 1. A power amplifier comprising an integrated circuit integrally formed with an active element, a passive element and the like, and a substrate for mounting the integrated circuit, comprising: a gate electrode and a drain provided in the integrated circuit. At least one FET comprising an electrode and a source electrode for amplifying a high frequency signal; a drain voltage supply terminal provided in the integrated circuit for supplying a voltage to the drain electrode of the FET; and a substrate outside the integrated circuit A drain power supply section provided on the upper side and connected to the drain voltage supply terminal, and an impedance adjustment provided on the substrate outside the integrated circuit section for adjusting the impedance of the drain power supply side viewed from the drain electrode of the FET. A power amplifier, comprising: 2. The power amplifier according to claim 1, wherein the impedance adjusting member is provided on a substrate outside the integrated circuit and is connected between the drain voltage supply terminal and the drain power supply unit. A transmission line for transmitting a capacitor, and a capacitor mounting portion which is provided on the substrate outside the integrated circuit and is configured such that a capacitor can be mounted between the ground of the substrate and the transmission line and the mounting portion can be changed. The power amplifier is characterized in that the operating frequency can be changed by changing the mounting portion of the capacitor. 3. The power amplifier according to claim 2, wherein the capacitor mounting portion is formed by opening a protective film of the transmission line at a plurality of points on the transmission line. 4. The power amplifier according to claim 2 or 3, wherein a capacitor is attached to the capacitor attaching portion. 5. The power amplifier according to claim 1, wherein the impedance adjusting member is provided on the substrate outside the integrated circuit, between the drain voltage supply terminal and the drain power supply unit, and both ends of the impedance adjusting member are provided. A power amplifier comprising an inductor mounting portion for mounting an inductor connected to each of a drain voltage supply terminal and a drain power source portion, wherein the operating frequency can be changed by changing the inductance value of the inductor. 6. The power amplifier according to claim 5, further comprising a capacitor provided on the substrate outside the integrated circuit, between the drain voltage supply terminal and the ground of the substrate. Power amplifier. 7. The power amplifier according to claim 5, wherein an inductor is attached to the inductor attaching portion. 8. A power amplifier including an integrated circuit integrally formed with an active element, a passive element, and the like, and a substrate for mounting the integrated circuit, comprising: a gate electrode and a drain provided in the integrated circuit. At least one FET including an electrode and a source electrode for amplifying a high frequency signal; a gate voltage supply terminal provided in the integrated circuit for supplying a voltage to a gate electrode of the FET; and a substrate outside the integrated circuit A first and a second gate power supply unit provided above, and a first and a second resistance member respectively interposed between the gate voltage supply terminal and the first and second gate power supply units, At least the second resistance member of the two resistance members is a variable resistor provided on a substrate outside the integrated circuit, and the operation via of the FET is changed by changing the resistance value of the variable resistor. Power amplifier, wherein a variable point configured to be. 9. The power amplifier according to claim 1, 2, 3, 4, 5, 6 or 7, further comprising: a gate voltage supply terminal provided in the integrated circuit for supplying a voltage to a gate electrode of the FET. , First and second gate power supply units provided on the substrate outside the integrated circuit, and first and second gate power supply units interposed between the gate voltage supply terminal and the first and second gate power supply units, respectively. Two resistance members, at least the second resistance member of the two resistance members is a variable resistor provided on a substrate outside the integrated circuit, and the variable resistor has a resistance value changed to change the resistance value. A power amplifier characterized in that the operation bias point of the FET can be changed. 10. The power amplifier according to claim 8 or 9, wherein the FET comprises a front-stage FET and a rear-stage FET, the power amplifier functions as a two-stage power amplifier, and the gate voltage supply terminal is a front-stage FET gate. A first-stage FET gate power supply unit connected to the first-stage FET gate voltage supply terminal, wherein the first-gate power supply unit is a voltage supply terminal and a second-stage FET gate voltage supply terminal.
The second gate power supply unit is a second-stage FET gate power supply unit connected to the second-stage FET gate voltage supply terminal, and the second resistance member, which is the variable resistor, is the first-stage FET.
Between the gate voltage supply terminal and the front-stage FET gate power supply section, and between the rear-stage FET gate voltage supply terminal and the rear-stage F
The first resistance member is interposed between the ET gate power supply section and the ET gate power supply section, and the first resistance member is provided between the pre-stage FET gate voltage supply terminal and the pre-stage FET gate power supply section and the post-stage FET gate voltage. A power amplifier, which is a fixed resistor interposed between the supply terminal and the second-stage FET gate power supply section. 11. The power amplifier according to claim 10, wherein the front-stage FET gate voltage supply terminal and the rear-stage FET gate voltage supply terminal are connected via a third fixed resistor. amplifier. 12. The power amplifier according to claim 8, 9, or 11, wherein a fixed resistor is provided between the gate electrode of the FET and the gate voltage supply terminal. Power amplifier. 13. A power amplifier comprising an integrated circuit integrally formed with an active element, a passive element and the like, and a substrate for mounting the integrated circuit, comprising a gate electrode and a drain electrode provided in the integrated circuit. And at least one FET for amplifying a high frequency signal composed of a source electrode, a gate voltage supply terminal provided in the integrated circuit for supplying a voltage to a gate electrode of the FET, and on a substrate outside the integrated circuit. And a first and a second resistance member provided between the gate voltage supply terminal and the first and the second gate power supply unit, respectively. At least the second resistance member of the two resistance members is attached to a resistor mounting portion provided between the gate voltage supply terminal and the second gate power supply portion on the substrate outside the integrated circuit. It was a fixed resistor, a power amplifier, characterized in that the change of the operating bias point of the FET by changing the resistance value of the fixed resistor is configured to be. 14. The method of claim 1, 2, 3, 4, 5, 6 or 7.
The power amplifier according to claim 1, wherein a gate voltage supply terminal provided in the integrated circuit for supplying a voltage to a gate electrode of the FET, and first and second gate power supply units provided on a substrate outside the integrated circuit And first and second resistance members respectively interposed between the gate voltage supply terminal and the first and second gate power supply units, and at least the second resistance member of the two resistance members. Is a fixed resistor attached to a resistor attachment portion provided between the gate voltage supply terminal and the second gate power source portion on the substrate outside the integrated circuit, and the resistance value of the fixed resistor is A power amplifier characterized in that the operation bias point of the FET can be changed by changing the above. 15. The power amplifier according to claim 14, wherein the FET comprises a front-stage FET and a rear-stage FET, the power amplifier functions as a two-stage power amplifier, and the gate voltage supply terminal is a front-stage FET gate voltage supply. And a first-stage FET gate voltage supply terminal, wherein the first gate power supply unit is a front-stage FET gate power supply unit connected to the front-stage FET gate voltage supply terminal,
The second gate power supply unit is a rear-stage FET gate power supply unit connected to the rear-stage FET gate voltage supply terminal, and the resistor mounting portion to which the second resistance member is mounted is the front-stage FET gate voltage supply terminal and the front-stage FET gate voltage supply terminal. The first resistance member is provided between the FET gate power supply unit and between the latter-stage FET gate voltage supply terminal and the latter-stage FET gate power supply unit, and the first resistance member is the former-stage FET gate voltage. Electric power, which is a fixed resistor interposed between a supply terminal and the preceding-stage FET gate power supply unit and between the latter-stage FET gate voltage supply terminal and the latter-stage FET gate power supply unit. amplifier. 16. The power amplifier according to claim 15, wherein the front stage FET gate voltage supply terminal and the rear stage FET gate voltage supply terminal are connected via a third resistor. . 17. The power amplifier according to claim 13, 14, 15 or 16, further comprising a fixed resistor interposed between the gate electrode of the FET and the gate voltage supply terminal. Power amplifier. 18. The method according to claim 8, 9, 10, 11, 12, 1.
3, 14, 15, 16 or 17, wherein the first resistance member is provided in the integrated circuit, and is connected to the gate electrode of the first FET, the drain electrode, the gate electrode and the gate electrode. A power amplifier comprising a second FET including a source electrode connected thereto. 19. A power amplifier comprising an integrated circuit integrally formed with an active element, a passive element and the like, and a substrate for mounting the integrated circuit, comprising: a gate electrode and a drain provided in the integrated circuit. A first FET including an electrode and a source electrode for amplifying at least one high-frequency signal; a drain electrode provided in the integrated circuit, connected to the gate electrode of the first FET, a gate electrode, and connected to the gate electrode A second FET including a source electrode, and first and second gate voltage supply terminals which are provided in the integrated circuit and supply voltages to the gate electrodes of the first and second FETs, respectively, and external to the integrated circuit. A first gate power supply unit provided on the substrate and connected to the first voltage supply terminal via the second FET; and provided on the substrate outside the integrated circuit. A second gate power supply section connected to the second voltage supply terminal, and a second gate power supply section provided on a substrate outside the integrated circuit, from a connection section between the gate electrode of the first FET and the drain electrode of the second FET. A power amplifier, comprising: a resistor interposed in a path leading to the unit. 20. Claims 1, 2, 3, 4, 5, 6 or 7
The power amplifier according to claim 1, which is provided in the integrated circuit and includes a drain electrode connected to a gate electrode of the FET, a gate electrode, and a source electrode connected to the gate electrode, for setting a gate bias of the FET. A second FET, the FET and the second FET provided in the integrated circuit
First and second gate voltage supply terminals for supplying a voltage to the respective gate electrodes, and a first voltage supply terminal connected to the first voltage supply terminal via the second FET. 1 gate power supply unit, a second gate power supply unit provided on the substrate outside the integrated circuit and connected to the second voltage supply terminal, and a second gate power supply unit provided on the substrate outside the integrated circuit, the gate of the first FET A power amplifier, comprising: a resistor provided in a path from a connection between the electrode and the drain electrode of the second FET to the second gate power supply unit. 21. The power amplifier according to claim 19 or 20, wherein the high frequency signal amplifying FET is a front stage FET and a rear stage FET.
The power amplifier functions as a two-stage power amplifier, and the first gate voltage supply terminal includes a front-stage FET gate voltage supply terminal and a rear-stage FET gate voltage supply terminal, and the front-stage FET gate voltage supply terminal And one of the rear-stage FET gate voltage supply terminal is connected to the first gate power supply unit via the second FET, and the other of the front-stage FET gate voltage supply terminal and the rear-stage FET gate voltage supply terminal is the resistor. A power amplifier, which is connected to the second gate power supply section via a power supply. 22. The power amplifier according to claim 19, 20 or 21, wherein the resistor interposed between the first gate voltage supply terminal and the second power supply is a variable resistor. A power amplifier characterized in that the operation bias point of the high-frequency signal amplification FET can be changed by changing the resistance value of the container. 23. The power amplifier according to claim 19 or 20, wherein a fixed resistor is provided between the gate electrode of the high-frequency signal amplification FET and the first gate voltage supply terminal. Power amplifier. 24. The power amplifier according to claim 21, between the gate electrode of the front stage FET and the front stage FET gate voltage supply terminal, and between the gate electrode of the rear stage FET and the rear stage FET gate voltage supply terminal. A power amplifier characterized in that a resistor is provided in each of the. 25. A high frequency semiconductor device comprising an integrated circuit in which an active element, a passive element and the like are integrally formed on a substrate, wherein at least one of a gate electrode, a drain electrode and a source electrode is provided in the integrated circuit. Two FETs, a matching circuit provided in the integrated circuit for matching a high frequency signal passing through the FETs, a source wiring extracted in a direction substantially perpendicular to the longitudinal direction of the gate electrode of the FETs, and the source wiring And a source pad that is disposed in a region located adjacent to both ends of the gate electrode of the FET in the longitudinal direction and located on a side portion of the semiconductor substrate. 26. The high frequency semiconductor device according to claim 25, wherein the source pad is provided at four or more places. 27. The high-frequency semiconductor device according to claim 25, wherein the source electrode of the FET is grounded via the ground of the source pad. 28. A high-frequency semiconductor device comprising an integrated circuit in which an active element, a passive element and the like are integrally formed on a substrate, wherein at least a gate electrode, a drain electrode and a source electrode are provided in the integrated circuit. One FET, a source wiring extending in a direction substantially perpendicular to the longitudinal direction of the gate electrode of the FET, connected to the source wiring, adjacent to both ends of the FET in the longitudinal direction, and at both ends of the semiconductor substrate. A matching circuit for matching a high-frequency signal that passes through the FET and is provided in the integrated circuit is provided in the source pad, and the capacitor of the matching circuit is adjacent to the source pad. A high-frequency semiconductor device arranged in a region. 29. The high-frequency semiconductor device according to claim 28, wherein matching circuits for matching high-frequency signals passing through the FET are arranged in regions adjacent to the FET on both sides of the gate electrode of the FET in the longitudinal direction. A high-frequency semiconductor device characterized by being provided. 30. In a high frequency semiconductor device having an active element and a matching circuit element formed on a semiconductor substrate, at least one FET formed of a gate electrode, a drain electrode and a source electrode in the integrated circuit, and the FET A power supply voltage is applied to the drain electrode of the FET, which is connected to the drain electrode and is disposed on one side of the semiconductor substrate and on a side different from the side of the substrate on which the output pad is disposed. A high-frequency semiconductor device, comprising: 31. 25, 26, 27, 28, 29
31. The high frequency semiconductor device according to item 30, wherein the output pad connected to the drain electrode of the FET and arranged on one side of the semiconductor substrate and the side of the substrate different from the side on which the output pad is arranged. And a drain pad for external attachment for applying a power supply voltage to the drain electrode of the FET, the high-frequency semiconductor device.