KR102128404B1 - Bias circuit for tuneable impedance matching of MMIC amplifiers - Google Patents

Abstract

The present invention relates to a bias circuit used in circuit design of an amplifier, and is characterized by mixing a low frequency band pass filter with a general bias circuit.
The low-frequency bandpass filter consists of a parallel capacitor and a series inductor, and uses the parallel capacitor by separating the number according to the capacitance, and by using a bonding wire for connection to the ground used for the parallel capacitor, the impedance of the bias circuit is arbitrarily adjusted. It is characterized by adjusting the input/output impedance of the amplifier by adjusting, and it is possible to improve the performance and linearity of the amplifier using this method.
Accordingly, the number of product developments of the MMIC amplifier can be reduced, and there is an advantage that the research cost and the development period required for product development can be reduced.

Description

Bias circuit for tuneable impedance matching of MMIC amplifiers

The present invention relates to a bias circuit for applying DC power to an amplifier used as a component of a mobile communication system, and it is possible to adjust the impedance of the bias circuit of the amplifier to improve the performance of the amplifier. It relates to the bias circuit of the amplifier.

The bias circuit of the amplifier is a circuit that allows direct current (DC) power to be supplied to the main transistor so that the amplifier can be driven.

Transistors are widely used as semiconductor active elements for the operation of amplifiers and other circuits for mobile communication or various applications, and are classified according to characteristics of materials and structures used in the manufacture of transistors.

First, depending on the material used, a single crystal semiconductor composed of only a covalent bond of a group 4 element such as silicon (Si) and germanium (Ge), and a compound consisting of a covalent bond of a group 3 and 5 element such as GaAs and InP It is divided into semiconductors, etc. Among them, a transistor manufactured using a compound semiconductor such as GaAs is used in mobile communication using a radio frequency (RF) and an ultra-high frequency (Microwave) band.

In addition, according to the characteristics of the fabrication structure, bipolar junction transistors (bipolar junction transistors) and field effect transistors (field effect transistors) are classified. FIG. 1 shows the circuit symbols of transistors according to each structural feature. FIG. 1(a) shows a bipolar junction transistor, and FIG. 1(b) shows a field effect transistor.

Each transistor consists of three terminals. First, the bipolar junction transistor of FIG. 1(a) is composed of an emitter (E, 11), a base (base, B, 12) and a collector (collector, C, 13), and the like. The field effect transistor is composed of terminals such as a source (source, S, 14), a gate (gate, G, 15), and a drain (drain, D, 16).

In order for these transistors to be used as amplifiers, DC power must be applied to B and G corresponding to the input of each transistor and C and D corresponding to the output. Generally, it is configured to apply a higher voltage or current to the output than the input. For example, when the DC voltage is 5V and the operating current is 50mA, while applying 5V to the output, the transistor is operated by applying a low voltage or current so that the current becomes 50mA to the input. 2 shows an example of a DC voltage applied according to the structure of each transistor.

The mobile communication amplifier is a hybrid integrated circuit (HIC) that uses active and passive components as separate components on a printed circuit board (PCB) or a monolithic MMIC (monolithic) that is implemented by using a batch process on a single semiconductor-based substrate. microwave integrated circuit). In the HIC and MMIC type amplifiers, the DC power source of the output uses the given voltage as it is, and the input uses a lower voltage or current than the output as shown above. Therefore, a specific circuit is required to drop the voltage applied to the output, which is called a bias circuit. The bias circuit of the HIC type amplifier uses passive and active elements as independent components, so it is easy to modify the desired value, whereas the MMIC type amplifier cannot modify the bias circuit implemented as a design value on one semiconductor substrate. . Therefore, the HIC type amplifier has an advantage of easy to modify the circuit value, but when it is used as a component due to its large size, there is a disadvantage that the volume of the system increases. The MMIC type amplifier has a disadvantage of not being able to modify the circuit value, but since it can be implemented in a small size to reduce the volume of the mobile communication system, the MMIC type amplifier is generally used.

Meanwhile, there are various types of bias circuits currently used.

3 is a resistive bias circuit, which has the advantage of being able to be implemented in the simplest structure, but has a large change in performance with respect to operating temperature and a large change in current and gain depending on the input RF input level. Because of its drawbacks, it is rarely used today.

4 is an active bias circuit using a resistor 41 and an emitter follower, and the performance change according to the temperature change is slightly insensitive compared to the resistive bias circuit, depending on the RF input level. It has the advantage of little change, but the performance change is large compared to other bias circuits to be listed below, and like resistive bias circuits, it is rarely used at present.

5 is a current mirror bias circuit. Compared to the bias circuits mentioned above, there is an advantage in that the current change and the performance change are small in a wide temperature range. However, since the impedance of the bias circuit is too low, it greatly affects the output impedance of the main circuit of the amplifier, and there is a risk of reducing the linearity of the amplifier circuit.

The linearity of the amplifier is one of the important performances that determine the quality of the signal. The linearity of the amplifier is represented by 3rd intermodulation distortion (IMD3) and 3rd intercept point (IP3). The linearity of these amplifiers depends on the performance of the main circuit and the impedance matching of the input and output. In particular, since the impedance matching of the input and output is affected by the impedance of the bias circuit itself, the circuit must be designed in consideration of the bias circuit. The above-described bias circuits of FIGS. 3 to 5 have low self-impedance, and may be one element that makes it difficult to match input/output impedance.

Therefore, a bias circuit has been developed to compensate for the shortcomings of the bias circuit and increase the linearity of the amplifier by increasing the impedance. FIG. 6 is a modified active bias circuit, by adding a resistor R2 to the conventional active bias circuit shown in FIG. 4 to adjust the low impedance of the active bias circuit to a resistance, thereby showing The impedance is increased to facilitate matching the input/output impedance of the entire amplifier. However, there is a disadvantage in that the output of the bias circuit is sensitive to temperature changes, thereby making the performance change depending on the temperature of the entire amplifier sensitive.

7 is the first modified form of the current mirror bias circuit (modified current mirror 1), and the three resistors R1 (71), R2 (72), and R3 (73) added to the circuit adjust the bias impedance and temperature compensation function. This is possible. It has the advantage of temperature compensation of the conventional current mirror circuit (FIG. 5), and is a structure that allows the impedance control of the circuit to be controlled. With the resistor R2 (72) fixed, by adjusting the resistors R1 (71) and R3 (73), it is possible to maximize the linearity of the amplifier without changing the current.

8 is a second modified form of the current mirror bias circuit (modified current mirror 2), which is a structure that facilitates adjustment of the impedance by adding the inductor 81 to the conventional current mirror circuit (FIG. 5). However, since the inductor 81 occupies a large portion of the chip size in the MMIC, it is a technique that is rarely used in the MMIC design.

9 is a circuit using a modified passive circuit (modified passive circuit) and an improved current mirror circuit (modified current mirror circuit) ([Patent Document 1] Bias network for high efficiency RF linear power amplifier, US 6,313,705 B1, 2001.11 .06.). This circuit has an advantage of having excellent temperature compensation performance and high variability, and excellent linearity of the circuit, compared to a conventional circuit. However, since it is more complicated than the conventional circuit and the chip size of a large area needs to be allocated to the bias circuit, there is a disadvantage in that the chip size requires a larger size than the conventional circuit.

In addition, the MMIC amplifier uses the values of the active and passive elements used in the design during the manufacturing process, and there is no way to change or adjust the values after manufacturing. Therefore, in design, after the impedance determined by the device values applied to the bias circuit was fixed to one, there was a problem that correction or adjustment was impossible. As shown in FIG. 10, in the MMIC amplifier development process, after the MMIC amplifier design, it is developed through a wafer process and a package step. Between the wafer process and the package, pre-measurement in the wafer state (pre- test). Pre-measurement is the process of verifying the performance of the designed MMIC amplifier after wafer fabrication and before proceeding to the package process.How to measure using a probe station and an open package consisting only of the lead frame of the package ( open package). When developing the MMIC amplifier, if the desired performance does not come out during the pre-measurement stage after wafer processing, or if the design result and the measurement result show a lot of difference after the wafer process, the redesign and wafer re-manufacturing must be performed again. There was a problem that cost and time are required for redesign and wafer remanufacturing.

[Patent Document 1] US Patent Publication US 6,313,705 B1 (2001.11.06.)

Therefore, the present invention is to solve the above problems, in the design of the MMIC amplifier circuit, a low pass band filter (LPF) is inserted into the bias circuit of the conventional configuration to adjust the impedance of the bias circuit, and the semiconductor MMIC By using wire bonding technology in the manufacturing process of the amplifier, it is possible to arbitrarily modify and adjust the impedance of the bias circuit, thereby improving the linearity of the amplifier and reducing the manufacturing process of the MMIC amplifier that can be repeated many times during product development. The objective is to provide a bias circuit of an MMIC amplifier with adjustable impedance, which can reduce development cost and reduce time.

In order to achieve the above object, the bias circuit of the MMIC amplifier capable of adjusting impedance according to an embodiment of the present invention includes a series inductor and a plurality of parallel capacitors for impedance adjustment, and one end of the series inductor is connected to a collector of the bias transistor. Connected, the other end of the series inductor is connected to one end of the plurality of parallel capacitors and the power supply terminal, the other end of the plurality of parallel capacitors is connected to the ground terminal through a bonding wire, each between the plurality of parallel capacitors and the ground terminal The bonding wire connection line of can be selectively connected or disconnected.

In the bias circuit of the MMIC amplifier capable of adjusting impedance according to another embodiment of the present invention, the impedance of the bias circuit may be determined by the total capacitance value of the parallel capacitor connected to the ground terminal by a bonding wire.

In the bias circuit of the MMIC amplifier capable of adjusting impedance according to another embodiment of the present invention, the length of the bonding wire may be adjustable.

Each of the plurality of capacitors is selectively wire-bonded, and the impedance of the entire bias circuit can be controlled by adjusting the parallel capacitance by controlling the number of parallel capacitors used in the LPF according to whether the wire bonding is connected.

By adjusting the impedance of the LPF so that the impedance of the entire bias circuit can be adjusted, the linearity of the amplifier can be increased.

Other specific matters of the present invention are included in the detailed description and drawings.

According to the bias circuit of the MMIC amplifier capable of adjusting the impedance according to the present invention, LPF is used in the bias circuit, and the ground connection of the parallel capacitor used in the LPF is not a backside via hole. By adjusting the impedance of the LPF using wire bonding, the impedance of the entire bias circuit can be adjusted, thereby increasing the linearity of the amplifier and reducing the number of developments. Also, if LPF is applied to an amplifier that requires an output of 0.5W or more, high linearity can be expected.

In the bias circuit of the impedance-adjustable MMIC amplifier according to the present invention, in order to induce the linearity improvement of the amplifier in the pre-measurement process before the package, by using a wire bonding method, the ground connection of the parallel capacitor of the LPF in the bias circuit , It is possible to adjust the impedance of the bias circuit, improve the linearity of the amplifier in this way, and then proceed with the package under the same conditions to reduce the number of developments of high-performance MMIC amplifiers. It has the effect of reducing the time required.

In addition, the technology according to the present invention can be applied to all conventional bias circuits, and in design, according to a mask layout technology, there is an effect that can be implemented in a small size without increasing the chip size of the MMIC much.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 shows a circuit symbol of a transistor according to a conventional structure, FIG. 1(a) is a symbol of a bipolar junction transistor (BJT), and FIG. 1(b) is a field effect transistor (FET) ).
2 is a circuit diagram of an example in which the DC power of the transistor is applied, FIG. 2(a) is an example of applying the DC power of the BJT, and FIG. 2(b) is an example of applying the DC power of the FET.
3 is a resistive bias circuit according to a conventional example.
4 is an active bias circuit according to another conventional example.
5 is a current mirror bias circuit according to another example of the related art.
6 is a modified active bias circuit according to another example of the related art.
7 is the first modified form of the current mirror bias circuit (modified current mirror 1).
8 is a second modified form of the current mirror bias circuit (modified current mirror 2).
9 is a circuit using a mixture of an improved passive circuit (modified passive circuit) and an improved current mirror circuit (modified current mirror circuit).
10 is a flowchart of the development of the MMIC amplifier of the present invention.
11 is a circuit diagram of a low pass filter (LPF) inserted in a bias circuit.
FIG. 12 illustrates a method of grounding a parallel capacitor, and FIG. 12(a) is a rear via hole grounding method, and FIG. 12(b) is a wire bonding grounding method.
13 is a circuit diagram showing an example of applying a temperature compensation circuit and an LPF to the improved active bias circuit of FIG. 6 as a bias circuit of an MMIC amplifier capable of adjusting impedance according to an embodiment of the present invention.
14 is an example showing the impedance change of the bias circuit according to the presence or absence of LPF in the bias circuit according to an embodiment of the present invention, and FIG. 14(a) shows the input/output reflection coefficient and impedance of the bias circuit in the absence of LPF. 14(b) shows the input/output reflection coefficient and impedance of the bias circuit in the case of LPF.
FIG. 15 shows the change of the S parameter of the amplifier according to the presence or absence of LPF in the amplifier to which the bias circuit of FIG. 13 is applied, and FIG. 15(a) shows the S parameter in the absence of LPF, and FIG. 15( b) shows the S parameter in the presence of LPF.
FIG. 16 shows a change in the reflection coefficient and impedance of the amplifier according to the presence or absence of LPF in the amplifier to which the bias circuit of FIG. 13 is applied, and FIG. 16(a) is a case where there is no LPF, and FIG. to be.
FIG. 17 shows a bias circuit in which the parallel capacitor of the LPF of FIG. 13 is divided into three and connected to ground by wire bonding.
FIG. 18 shows input/output reflection coefficient and impedance change according to an example in which the parallel capacitor of LPF of FIG. 17 is divided, and FIG. 18(a) is a case where 0 parallel capacitors are connected to ground, and FIG. 18(b) is 1 18 parallel capacitors are connected to ground, FIG. 18(c) is a case where two parallel capacitors are connected to ground, and FIG. 18(d) is a case where three parallel capacitors are connected to ground.
FIG. 19 shows a change in the S parameter of an amplifier according to the number of ground connections in an amplifier to which a bias circuit using LPF with the parallel capacitor separated in FIG. 17 is applied, and FIG. 19(a) shows that 0 parallel capacitors are connected to ground. When connected, FIG. 19(b) is when one parallel capacitor is connected to ground, FIG. 19(c) is when two parallel capacitors are connected to ground, and FIG. 19(d) is when three parallel capacitors are connected to ground. Is connected to.
20 is a circuit diagram showing a wire connected to the ground in FIG. 17 with an inductor.
FIG. 21 shows the change of the S parameter due to the effect of inductance along the length of the wire using all three parallel capacitors in FIG. 17, and FIG. 21(a) is a case where the inductance of the wire is 0.5 nH, and FIG. b) is when the inductance of the wire is 1nH, and FIG. 21(c) is when the inductance of the wire is 2nH.

Advantages and features of the present invention, and a method of achieving them will be clarified with reference to embodiments described below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and are common in the art to which the present invention pertains. It is provided to fully inform the skilled person of the scope of the present invention, and the present invention is only defined by the claims.

The terminology used herein is for describing the embodiments, and is not intended to limit the present invention. In the present specification, the singular form also includes the plural form unless otherwise specified. As used herein, "includes." And/or “comprising” does not exclude the presence or addition of one or more other components other than the components mentioned. Throughout the specification, the same reference numerals refer to the same components, and “and/or” includes each and every combination of one or more of the components mentioned.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a sense that can be commonly understood by those skilled in the art to which the present invention pertains. In addition, terms that are defined in a commonly used dictionary are not ideally or excessively interpreted unless explicitly defined.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

11 shows a circuit of LPF inserted into a bias circuit, and is composed of a series inductor 101 and a parallel capacitor 102. The series inductor 101 is connected in series to the input and output of the LPF, and the parallel capacitor 102 is connected in parallel between the input and output of the LPF and between ground. In general, the ground connection of the parallel capacitor in the LPF uses a back via hole connected through the wafer, but in the case of the present invention it is connected to ground using wire bonding.

12 is a view showing a connection method of the parallel capacitor 111 and the lead frame 112 used as ground.

12(a) is a connection method through a rear via hole, and a capacitor used in a semiconductor having a metal-insulator-metal (MIM) structure includes an upper metal electrode 113 and a lower metal electrode 114. It consists of a sandwich structure in which a dielectric 115 is interposed, and forms a via hole 117 on the substrate 116 under the lower metal electrode 114 outside the region of the parallel capacitor 111 indicated by a dotted line, and also grounds. It is a method of forming the electrode 118 and directly connecting it to the lead frame 112 using a conductive solder (119).

12(b) is a connection method by wire bonding, without forming via holes in the substrate under the extended lower metal electrode 114 as described above, and connecting to the lead frame 112 using the bonding wire 120. Is how to do it.

In the present invention, by using a ground connection method using wire bonding without using a rear via hole, the impedance of the LPF can be adjusted, and the impedance of the bias circuit can be adjusted to increase the linearity of the amplifier.

13 shows an impedance matching adjustable DC power supply circuit of an amplifier according to an embodiment of the present invention, and shows an example of applying a temperature compensation circuit and LPF to the improved active bias circuit of FIG. 6. In order for the improved active bias circuit of FIG. 6 to be applied to the bias circuit of the MMIC amplifier, all DC power applied to the bias circuit must be connected to the output voltage of the main transistor to reduce the bias terminal of the package. In addition, for temperature compensation, a temperature compensation diode 122 and a bias resistor may be used as shown in the drawing in a portion where the input voltage of the bias transistor 121 is applied. The bias resistor is used as a voltage distribution form of the upper bias resistor 123 and the lower bias resistor 124, thereby controlling the input voltage or current of the bias transistor 121.

The LPF for impedance adjustment of the bias circuit is a basic LPF applied to FIG. 11, consisting of a series inductor 125 and a parallel capacitor 126, one end of the series inductor connected to the collector of the bias transistor 121, and the other end in parallel One end of the capacitor is connected to the power supply terminal In, and the other end of the parallel capacitor is connected to ground through a bonding wire. The power supply terminal In connected to one end of the series inductor is also connected to the output of the main transistor of the amplifier. In the MMIC, the method used for ground connection is generally such that it is connected using the rear via hole of FIG. 11(a), and the inductance generated in the via hole is neglected to a very low value.

14 is an example showing an impedance change of the bias circuit according to the presence or absence of LPF in the bias circuit. A circuit with 20 nH of series inductance of LPF and 6 pF of parallel capacitance was applied. 14(a) shows the input/output reflection coefficient and impedance of the bias circuit in the absence of LPF. 14(b) shows the input/output reflection coefficient and impedance of the bias circuit in the case of LPF. And Table 1 shows the change in the reflection coefficient and impedance of the bias circuit at 2.14 GHz with and without LPF as a numerical value on the complex plane.

division characteristic LPF presence classification Nothing Existence input Reflection coefficient (S11) 0.36-j0.80 0.39-j0.72 Impedance (Zin) Z0* (0.22-j1.53) Z0* (0.38-j1.62) Print Reflection coefficient (S22) 0.86-j0.38 0.76-j0.48 Impedance (Zout) Z0* (0.69-j4.66) Z0* (0.061-j0.29)

14 and Table 1 show an example in which the impedance of the bias circuit changes depending on the presence or absence of LPF.

The impedance change of the bias circuit according to the presence or absence of the LPF has a significant influence on the impedance of the amplifier.

15 and 16 show the change of the S parameter (parameter) of the amplifier with or without LPF in the amplifier to which the bias circuit of FIG. 13 is applied. 15(a) shows the S parameter in the absence of LPF, and FIG. 15(b) shows the S parameter in the presence of LPF in dB values, and FIGS. 16(a) and 16(b) show the presence or absence of LPF. It shows the change of the reflection coefficient and impedance according to. And Table 2 represents the S parameter value of the amplifier to which the bias circuit is applied at 2.14 GHz with or without LPF.

Item S parameter value (LPF presence/absence, @ 2.14GHz) [dB] Nothing Existence S11 -8.9 -21.0 S21 15.3 18.6 S22 -2.3 -24.1

15 and 16 and Table 2, in order to confirm the effect of only the LPF of FIG. 13, only the presence or absence of applying the LPF of the bias circuit was compared, and the matching of the input and output impedances of the amplifier is the same.

By modifying the input/output impedance matching of the amplifier depending on whether LPF is applied, the opposite result or the same result can be obtained, but the performance of output power and linearity is similar even if the S parameter values in Table 2 are similar depending on the result of impedance matching. It may have different results. Therefore, in order to enable matching of the input/output impedance of the amplifier capable of improving the performance of the amplifier, a method of finely adjusting the impedance of the bias circuit is needed.

The embodiment of FIG. 13 is for confirming only the influence of the input/output impedance of the amplifier by the impedance of the bias circuit according to the presence or absence of LPF, and whether LPF is applied to the bias circuit can change the impedance of the bias circuit, which is an amplifier. It was confirmed that it could affect the overall impedance. However, in the case of FIG. 13, since it is assumed that the ground of the parallel capacitor of the LPF is a case using the rear via hole method, the method capable of changing the impedance of the bias circuit is limited to the use of LPF only. Therefore, in order to optimize output power and linearity, it is necessary to adjust the input/output impedance of the amplifier or to optimize the bias circuit impedance.

However, since the rear via hole method is used for the ground connection of the parallel capacitor of the LPF in FIG. 13, the impedance of the bias circuit is fixed by the value of the component of the bias circuit during design. In order to extract the optimum performance of the MMIC amplifier, the input/output impedance matching method alone has limitations only by adjusting the input/output impedance of the amplifier due to limitations such as device values used for matching and length of input/output transmission lines on the PCB. However, it is possible to adjust the impedance of the bias circuit, and if it is used together with matching the input/output impedance of the amplifier, the limit of optimization is further increased, and if it is used for product development, the number of development attempts may be reduced.

17 is a case in which a plurality of parallel capacitors of the LPF used in FIG. 13 are used to adjust the impedance of the bias circuit according to the present invention. The separation and use of multiple parallel capacitors is to enable finer adjustment of the impedance matching of the MMIC amplifier bias circuit according to the number of small-value parallel capacitors connected to the ground with a bonding wire. To this end, the ground connection method of the separated plurality of parallel capacitors should use the wire bonding method of FIG. 12(b). Because, the present invention is a form of controlling the impedance of the bias circuit by adjusting the capacitance of the LPF according to the presence and number of bonding wires for ground connection in each capacitor by separating a plurality of parallel capacitors. In this case, all the capacitors are connected to the ground, and as shown in FIG. 13, it becomes the same as the case where one capacitor is used, so it is impossible to adjust the capacitance. In addition, since MMIC's products cannot change the value of individual devices after they are manufactured, the capacitors can be used separately at the design stage, optimizing the performance of the amplifier during pre-measurement and packaging after wafer fabrication. It is for sake.

For example, the 6FF parallel capacitor 126 is used for the LPF of FIG. 13, and FIG. 17 is a case where the parallel capacitor is divided into three (161, 162, 163) of 2pF. This is a method of adjusting the impedance of the bias circuit by adjusting the number of parallel capacitors used in the LPF and adjusting the parallel capacitance depending on whether wire bonding is connected. Thereby, the input/output impedance of the whole amplifier circuit can be adjusted. FIG. 18 shows a change in impedance of the bias circuit according to the number of connections of the parallel capacitor and ground in FIG. 17. 18(a) to (d) show the case where 0 to 3 capacitors are connected. 0 is for a series inductor only.

If the capacitance of the parallel capacitor of the LPF is set to a smaller value, the number of separations can be increased and finer impedance adjustment is possible, but there is a disadvantage in that the chip size increases.

The amplifier to which the bias circuit of FIG. 17 is applied adjusts the impedance of the bias circuit according to the number of parallel capacitor connections, thereby making it possible to adjust the impedance of the entire circuit of the amplifier. 19 shows the change of the S parameter of the amplifier according to the number of connections of the parallel capacitor, and Table 3 shows the S parameter value at 2.14 GHz for each case. When the number of parallel capacitors is 0, only the series inductor is present in the LPF. The results in FIG. 19 and Table 3 are for confirming the change in impedance of the entire amplifier according to the connection of the parallel capacitors, and the input and output impedances of the amplifier are all the same values. For each case, changing the impedance matching of the amplifier can produce different results.

Item S parameter value according to the number of parallel capacitor connections (@ 2.14 GHz) [dB] 0 One 2 Three S11 -9.8 -12.2 -18.3 -21.0 S21 15.0 16.7 18.1 18.6 S22 -2.5 -4.4 -9.3 -24.1

In addition, the bonding wire used for connection to ground can be represented by an inductor having a metal internal resistance and inductance. Since the internal resistance of the metal has a value that is too small, it can be ignored, but when the frequency increases because the inductance changes with the length of the wire, the reactance becomes a value that cannot be ignored. FIG. 20 is a circuit diagram showing the wire used for the connection of the parallel capacitor and ground of FIG. 17 as an inductor, having an inductance of about 1 nH when the length is 1 mm, and the inductance increases linearly as the length increases. By adjusting the length used for the connection of the parallel capacitor and ground, the impedance of the bias circuit can be adjusted, and the impedance of the amplifier can also be adjusted.

FIG. 21 shows the effect of inductance according to the length of the wire using all three parallel capacitors (total capacitance: 6 pF) in FIG. 19, and of the amplifier when the inductance according to the length of the wire is 0.5, 1 and 2 nH It shows the change of S parameter. Also in this case, the inductance according to the length of the wire is for confirming the influence of the impedance of the amplifier, and the input and output impedance matching of the amplifier is the same, and in each case, changing the impedance matching can lead to different results. .

As described above, by adjusting the impedance of the circuit of the bias using LPF using a combination of the number of parallel capacitors and the length of the bonding wire, fine adjustment of the input/output impedance of the amplifier circuit is possible, thereby increasing the performance and linearity of the amplifier. .

Table 4 shows the design results of an amplifier using a bias circuit to which an LPF and an impedance control circuit according to the present invention are applied to an amplifier of 0.5 W class, using the parallel capacitors of FIGS. 17 and 19 separately and using a wire bonding method It shows the optimization result of the amplifier with the ground connected bias circuit, and the output power (P1dB) and linearity (with the input and output impedance of the amplifier adjusted under conditions that have almost the same circuit gain and reflection coefficient for each condition) OIP3).

Circuit conditions Amplifier performance Ground connection
Count wire
Inductance (nH) S21 [dB] S11 [dB] S22 [dB] P1dB [dBm] OIP3 [dBm] One 0.5 18.6 -20 -18 26.8 32.5 One 18.5 -19 -21 26.9 31.0 2 18.6 -18 -23 26.7 30.7 2 0.5 18.7 -21 -20 26.9 39.3 One 18.5 -22 -19 27.0 38.8 2 18.6 -20 -22 26.8 38.3 3 0.5 18.6 -20 -22 27.1 42.3 One 18.7 -21 -24 27.3 41 2 18.5 -18 -20 27.4 39.5

Using this method, before performing the pre-measurement before the package, and finally proceeding with the package, there is an advantage of reducing the number of product developments, reducing research investment required for development, and reducing costs and shortening the development period.

The embodiments illustrated in the present specification and the configuration illustrated in the drawings are related to preferred embodiments of the present invention, and do not cover all technical spirits of the invention, and thus various equivalents that can replace them at the time of filing It should be understood that there may be variations. Therefore, the present invention is not limited to the above embodiments, and without departing from the gist of the present invention as claimed in the claims, various modifications can be made to any person skilled in the art to which the present invention pertains. And such changes are within the scope of the claims of the present invention.

11: emitter (E) 12: base (B)
13: collector (C) 14: source (S)
15: gate (G) 16: drain (D)
41: resistance 71: resistance 1 (R 1)
72: resistance 2 (R 2) 73: resistance 3 (R 3)
81: inductor 101: series inductor
102: parallel capacitor 111: parallel capacitor
112: lead frame 113: upper metal electrode
114: lower metal electrode 115: dielectric
116: substrate 117: via hole
118: ground electrode 119: conductive solder
120: bonding wire 121: bias transistor
122: temperature compensation diode 123: upper bias resistor
124: lower bias resistance 125: series inductor
126: parallel capacitor 161: parallel capacitor 1
162: parallel capacitor 2 163: parallel capacitor 3
164: ground 165: bonding wire 1
166: bonding wire 2 167: bonding wire 3
191: Wire inductance 1 192: Wire inductance 2
193: wire inductance 3

Claims (5)

In the bias circuit of the MMIC amplifier with adjustable impedance,
Includes a series inductor and a plurality of parallel capacitors for impedance adjustment,
One end of the series inductor is connected to the collector of the bias transistor,
The other end of the series inductor is connected to one end and a power terminal of a plurality of parallel capacitors,
The other end of the plurality of parallel capacitors is connected to a ground terminal through a bonding wire,
Each of the bonding wire connection line between the plurality of parallel capacitors and the ground terminal is selectively connected or disconnected, the bias circuit of the adjustable impedance MMIC amplifier. The method according to claim 1,
The impedance of the bias circuit of the MMIC amplifier is determined by the total capacitance value of a parallel capacitor selectively connected to the ground terminal by the bonding wire, the bias circuit of the impedance adjustable MMIC amplifier. The method according to claim 1,
The length of the bonding wire is characterized in that the adjustable, bias circuit of the MMIC amplifier is adjustable impedance. In the manufacturing method of the MMIC amplifier built-in bias circuit of the MMIC amplifier capable of adjusting the impedance of claim 1,
And selectively connecting or disconnecting each connection line between the plurality of parallel capacitors and the ground terminal to adjust a total capacitance value of the plurality of parallel capacitors. The method according to claim 4,
And adjusting the impedance of the bias circuit by adjusting the length of the bonding wire.

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