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JPH0729855A - Expanding method of semiconductor wafer - Google Patents

Expanding method of semiconductor wafer

Info

Publication number
JPH0729855A
JPH0729855A JP17138193A JP17138193A JPH0729855A JP H0729855 A JPH0729855 A JP H0729855A JP 17138193 A JP17138193 A JP 17138193A JP 17138193 A JP17138193 A JP 17138193A JP H0729855 A JPH0729855 A JP H0729855A
Authority
JP
Japan
Prior art keywords
sheet
semiconductor wafer
expanding
wafer
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17138193A
Other languages
Japanese (ja)
Inventor
Noboru Goto
登 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP17138193A priority Critical patent/JPH0729855A/en
Publication of JPH0729855A publication Critical patent/JPH0729855A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dicing (AREA)

Abstract

PURPOSE:To obtain an expanding method which can expand the interval between semiconductor chips with good accuracy and simply in the manufacture of a semiconductor integrated circuit. CONSTITUTION:In an expanding method in the manufacture of a semiconductor integrated circuit, a semiconductor wafer 1 which has been fixed and bonded to an elastic sheet 2 is cut along dicing lines 6,...6, and each interval between semiconductor wafer chips 1',...1' which have been 'diced is then expanded by stretching the sheet 2. The expanding method is featured in such a way that the sheet is stretched until the diced semiconductor chips 1',1' on both rnds reach a prescribed interval 7, and the wafer ships l', 1' on both ends are measured by an optical sensor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路の製造に
際し、半導体ウエハチップの間隔を精度良く、簡単に拡
げることのできるエキスパンデイング方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an expanding method capable of accurately and easily expanding the distance between semiconductor wafer chips when manufacturing a semiconductor integrated circuit.

【0002】[0002]

【従来の技術】ダイシングされたICあるいはFET等
の半導体ウエハチップをリ−ドフレ−ムやパッケ−ジに
搬送して半田、金あるいは樹脂等の接合材により装着す
る半導体集積回路の製造に先立って、弾性を有するテー
プ上に固着された半導体ウエハをダイシングし、前記テ
ープを引き伸ばしてダイシングされたウエハチップの間
隔を所定の大きさにすることが必要である。
2. Description of the Prior Art Prior to manufacturing a semiconductor integrated circuit, a semiconductor wafer chip such as a diced IC or FET is transferred to a lead frame or package and mounted by a bonding material such as solder, gold or resin. It is necessary to dice a semiconductor wafer fixed on a tape having elasticity and to stretch the tape so that the distance between the diced wafer chips becomes a predetermined size.

【0003】図3は従来のエキスパンデイング方法を説
明するための図面であり、同図(a)はエキスパンデイ
ング前の縦断面図、同図(b)はエキスパンデイング後
の断面図である。リング3には弾性を有するシ−ト2が
固定され、このシ−ト2の上に固着されたウエハ1がダ
イシングライン6・・・6に従って縦及び横方向に切断
される。リング3は内接して配置された円筒管4の軸方
向に引っ張ることによって同図(b)のように切断され
たウエハチップ1′・・・1′はシ−ト上で左右、前後
に間隔7・・・7があけられる。間隔7・・・7は引っ
張られたリング3の距離によって決められ、リング3の
位置は円筒管4の外周に照射されたレ−ザ光5によって
光学的に制御している。
3A and 3B are views for explaining a conventional expanding method. FIG. 3A is a vertical sectional view before expanding, and FIG. 3B is a sectional view after expanding. is there. An elastic sheet 2 is fixed to the ring 3, and the wafer 1 fixed on the sheet 2 is cut in the vertical and horizontal directions according to the dicing lines 6 ... The ring 3 is pulled in the axial direction of the cylindrical tube 4 arranged inscribed therein, and the wafer chips 1 ′ ... 1 ′ cut as shown in FIG. 7 ... 7 is opened. The intervals 7 ... 7 are determined by the distance of the pulled ring 3, and the position of the ring 3 is optically controlled by the laser light 5 irradiated on the outer circumference of the cylindrical tube 4.

【0004】[0004]

【発明が解決しようとする課題】ダイシングされるウエ
ハチップ1′・・・1′の大きさはFETの場合は小さ
く、LSIの場合は大きくなる。これを従来の方法によ
ってエキスパンデイングすると、ウエハチップが小さく
ダイシングライン6・・・6の数が多い場合は間隔7・
・・7は狭くなり、反対にウエハチップが大きい場合は
間隔7・・・7は広くなる。即ち、従来の方法ではエキ
スパンデイングして得られる間隔7・・・7は切断され
るダイシングライン6・・・6の数によって変化するの
で、一旦エキスパンデイングした後に調整をする必要が
あり、その数に影響されず一定にすることが困難であっ
た。そこで本発明は、かかる問題点を解決した半導体ウ
エハのエキスパンデイング方法を提供することを目的と
する。
The size of wafer chips 1 '... 1'to be diced is small in the case of FET and large in the case of LSI. When this is expanded by the conventional method, when the wafer chip is small and the number of dicing lines 6 ...
········································· 7 becomes narrower, on the contrary, when the wafer chip is large, the interval 7 ... That is, in the conventional method, the intervals 7 ... 7 obtained by expanding change depending on the number of dicing lines 6 ... 6 to be cut, so it is necessary to adjust after expanding once. It was difficult to make it constant regardless of the number. Therefore, an object of the present invention is to provide a method for expanding a semiconductor wafer that solves the above problems.

【0005】[0005]

【課題を解決するための手段】本発明に係わる半導体ウ
エハのエキスパンデイング方法は、半導体集積回路の製
造に際し、弾性を有するシ−ト上に固着された半導体ウ
エハをダイシングし、その後、前記シ−トを引き伸ばし
てダイシングされた半導体ウエハチップの間隔を拡げる
エキスパンデイング方法であって、ダイシングされた両
端のウエハチップが所定の間隔になるまで前記シ−トを
引き伸ばすことを特徴とし、両端のウエハチップは光セ
ンサによって測定される。
According to a method of expanding a semiconductor wafer according to the present invention, a semiconductor wafer fixed on an elastic sheet is diced at the time of manufacturing a semiconductor integrated circuit, and then the above-mentioned wafer is diced. -An expanding method of expanding the distance between the diced semiconductor wafer chips by stretching the sheet, characterized in that the sheet is expanded until the wafer chips at the both ends of the diced have a predetermined distance, The wafer chip is measured by the optical sensor.

【0006】上記の方法は弾性を有するシートを引き伸
ばし、その上に固着された半導体ウエハチップの間隔を
広げるに際し、周囲温度をほぼ65℃に保持することが
好ましい。
In the above method, it is preferable to keep the ambient temperature at about 65 ° C. when the elastic sheet is stretched and the distance between the semiconductor wafer chips fixed thereon is widened.

【0007】[0007]

【作用】ダイシングラインの数及び相隣る間隔が解れば
エキスパンデイング後の両端のウエハチップの位置が決
定されるので、上記の構成のように両端のウエハチップ
の間隔を測定しながらシ−トを引き伸ばすことによって
一義的に間隔を決定することができる。即ち、レ−ザ光
によって直接ウエハチップの位置を測定するので従来よ
り間隔を精度良く決定することができる。また、周囲温
度をほぼ65℃ に保持してシートをエキスパンデイン
グするので、半導体ウエハチップの間隔はシート間ある
いはシート内の位置によるばらつきを極力押さえること
ができる。
If the number of dicing lines and the distance between adjacent dicing lines are known, the positions of the wafer chips at both ends after expansion are determined. The distance can be uniquely determined by stretching the pitch. That is, since the position of the wafer chip is directly measured by the laser light, the interval can be determined more accurately than before. Further, since the sheet is expanded while the ambient temperature is maintained at about 65 ° C., it is possible to suppress variations in the intervals of the semiconductor wafer chips due to the positions between the sheets or within the sheet as much as possible.

【0008】[0008]

【実施例】以下、図1、図2を参照して本発明の実施例
を説明する。図1は本発明に係わる実施例の構成を示す
図面であり、同図(a)はエキスパンデイング前の縦断
面図、同図(b)はエキスパンデイング後の縦断面図で
ある。なお、図3と同一要素には同一符号を付し、重複
する説明を省略する。図1において、図示していない検
知装置から所定の間隔をおいてレ−ザ光5、5をシ−ト
2の上面へ照射し、反射光が戻ってくる時間を測定して
いる。図2(b)のようにシ−ト上の両端のウエハチッ
プ1′、1′が両側へ引っ張られてレ−ザ光5、5に照
射されると反射光が戻ってくる時間はその厚さ分だけ短
くなるので両端のウエハチップ1′、1′が所定の間隔
まで移動したことを光センサによって測定することがで
きる。シ−ト2は日東電工製の塩化ビニルからなるV−
8−Mを用いた。
Embodiments of the present invention will be described below with reference to FIGS. 1A and 1B are views showing a configuration of an embodiment according to the present invention. FIG. 1A is a vertical sectional view before expanding and FIG. 1B is a vertical sectional view after expanding. Note that the same elements as those in FIG. 3 are denoted by the same reference numerals, and redundant description will be omitted. In FIG. 1, the upper surface of the sheet 2 is irradiated with laser light 5 and 5 at a predetermined interval from a detection device (not shown), and the time when the reflected light returns is measured. As shown in FIG. 2B, when the wafer chips 1 ', 1'at both ends on the sheet are pulled to both sides and irradiated with the laser light 5, 5, the time during which the reflected light returns is the thickness thereof. Since it is shortened by that amount, it can be measured by the optical sensor that the wafer chips 1 ', 1'at both ends have moved to a predetermined interval. Sheet 2 is a vinyl chloride V-made by Nitto Denko.
8-M was used.

【0009】図2は本発明の実施例を説明するための図
面であり、同図(a)はエキスパンデイング前の平面
図、同図(b)はエキスパンデイング後の平面図であ
る。シ−ト2に固着した直径3インチ(76mmφ)の
GaAsウエハ1を縦及び横方向のダイシングライン6
・・・6に沿って切断し、内径150mmのリング3を
引下げながらシ−ト2を150%拡張した。両端のウエ
ハチップ1′a、1′bが1″a、1″bまでエキスパ
ンデイングするには図1で説明した光センサ方式によっ
て行なった。エキスパンデイングの精度を高めるために
縦方向の両端ウエハチップ1″c、1″dについても同
様の測定を行なった。
2A and 2B are views for explaining an embodiment of the present invention. FIG. 2A is a plan view before expanding and FIG. 2B is a plan view after expanding. A GaAs wafer 1 having a diameter of 3 inches (76 mmφ) fixed to the sheet 2 is laid along a vertical and horizontal dicing line 6
... 6 was cut and the sheet 2 was expanded by 150% while pulling down the ring 3 having an inner diameter of 150 mm. To expand the wafer chips 1'a and 1'b on both ends to 1 "a and 1" b, the optical sensor method described in FIG. 1 was used. In order to improve the accuracy of expanding, the same measurement was performed on the wafer chips 1 ″ c and 1 ″ d on both ends in the vertical direction.

【0010】また、シート2は周囲温度によって引き伸
ばされる寸法が変化、シート間あるいはシート内の位置
によってばらつくことがある。そこで、エキスパンデイ
ングは65±2℃の範囲で行った。その結果、1mm×
1mmのウエハチップ1″・・・1″の間隔7・・・7
は0.5mmとなり、ダイボンデイング工程において図
示していないコレットによってウエハチップ1″・・・
1″をリ−ドフレ−ムあるいはパッケ−ジに搬送するた
めの間隔を確保することができた。
Further, the dimension of the sheet 2 that is stretched may change depending on the ambient temperature, and the sheet 2 may vary depending on the position between sheets or within the sheet. Therefore, expanding was performed in the range of 65 ± 2 ° C. As a result, 1mm x
1 mm wafer chip 1 "... 1" spacing 7 ... 7
Is 0.5 mm, and the wafer chip 1 ″ ... By a collet (not shown) in the die bonding process.
It was possible to secure a space for transporting 1 "to the lead frame or the package.

【0011】[0011]

【発明の効果】以上説明したように、本発明はダイシン
グラインの数及び相隣る間隔が解ればエキスパンデイン
グ後の両端のウエハチップの位置が決定されるので、両
端のウエハチップの間隔を測定しながらシ−トを引き伸
ばすことによって一義的に間隔を決定することができ
る。また、レ−ザ光によって直接ウエハチップの位置を
測定すること、そして周囲温度をほぼ65℃に保持して
シートをエキスパンデイングするので、従来より間隔を
精度良く決定することができる。
As described above, according to the present invention, the positions of the wafer chips at both ends after expanding are determined if the number of dicing lines and the adjacent intervals are known. The distance can be uniquely determined by stretching the sheet while measuring. Further, since the position of the wafer chip is directly measured by the laser light and the sheet is expanded while keeping the ambient temperature at about 65 [deg.] C., the interval can be determined more accurately than before.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係わる実施例の構成を示す図面であ
り、同図(a)はエキスパンデイング前の縦断面図、同
図(b)はエキスパンデイング後の縦断面図である。
1A and 1B are views showing a configuration of an embodiment according to the present invention, in which FIG. 1A is a vertical sectional view before expanding and FIG. 1B is a vertical sectional view after expanding.

【図2】本発明の実施例を説明するための図面であり、
同図(a)はエキスパンデイング前の平面図、同図
(b)はエキスパンデイング後の平面図である。
FIG. 2 is a diagram for explaining an embodiment of the present invention,
FIG. 7A is a plan view before expanding, and FIG. 7B is a plan view after expanding.

【図3】従来のエキスパンデイング方法を説明するため
の図面であり、同図(a)はエキスパンデイング前の縦
断面図、同図(b)はエキスパンデイング後の断面図で
ある。
3A and 3B are views for explaining a conventional expanding method, wherein FIG. 3A is a vertical sectional view before expanding and FIG. 3B is a sectional view after expanding.

【符号の説明】[Explanation of symbols]

1:ウエハ 1′、1″:ウエハチップ 2:シ−ト 3:リング 4:円筒管 5:レ−ザ光 6:ダイシングライン 7:間隔 1: Wafer 1 ′, 1 ″: Wafer chip 2: Sheet 3: Ring 4: Cylindrical tube 5: Laser light 6: Dicing line 7: Interval

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路の製造に際し、弾性を有
するシ−ト上に固着され半導体ウエハをダイシングし、
その後、前記シートを引き伸ばしてダイシングされた半
導体ウエハチップの間隔を拡げるエキスパンデイング方
法であって、 ダイシングされた両端のウエハチップが所定の間隔にな
るまで前記シ−トを引き伸ばすことを特徴とする半導体
ウエハのエキスパンデイング方法。
1. When manufacturing a semiconductor integrated circuit, a semiconductor wafer fixed on an elastic sheet is diced,
Thereafter, the sheet is stretched to expand the distance between the diced semiconductor wafer chips, and the sheet is stretched until the diced wafer chips at both ends have a predetermined distance. Semiconductor wafer expanding method.
【請求項2】 両端のウエハチップの間隔を光センサに
よって測定することを特徴とする請求項1記載の半導体
ウエハのエキスパンデイング方法。
2. The method of expanding a semiconductor wafer according to claim 1, wherein the distance between the wafer chips at both ends is measured by an optical sensor.
【請求項3】 弾性を有するシートを引き伸ばし、その
上に固着された半導体ウエハチップの間隔を広げるに際
し、周囲温度をほぼ65℃に保持することを特徴とする
請求項1記載の半導体ウエハのエキスパンデイング方
法。
3. The semiconductor wafer extract according to claim 1, wherein the ambient temperature is maintained at about 65 ° C. when the elastic sheet is stretched and the interval between the semiconductor wafer chips fixed thereon is widened. How to pan.
JP17138193A 1993-07-12 1993-07-12 Expanding method of semiconductor wafer Pending JPH0729855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17138193A JPH0729855A (en) 1993-07-12 1993-07-12 Expanding method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17138193A JPH0729855A (en) 1993-07-12 1993-07-12 Expanding method of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH0729855A true JPH0729855A (en) 1995-01-31

Family

ID=15922129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17138193A Pending JPH0729855A (en) 1993-07-12 1993-07-12 Expanding method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH0729855A (en)

Cited By (8)

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US8865566B2 (en) 2002-12-03 2014-10-21 Hamamatsu Photonics K.K. Method of cutting semiconductor substrate
US8889525B2 (en) 2002-03-12 2014-11-18 Hamamatsu Photonics K.K. Substrate dividing method
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US6642165B2 (en) 2000-08-21 2003-11-04 Kabushiki Kaisha Toshiba Wear resistant member for electronic equipment, and bearing and spindle motor therewith
US8946592B2 (en) 2000-09-13 2015-02-03 Hamamatsu Photonics K.K. Laser processing method and laser processing apparatus
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US9837315B2 (en) 2000-09-13 2017-12-05 Hamamatsu Photonics K.K. Laser processing method and laser processing apparatus
US8946591B2 (en) 2000-09-13 2015-02-03 Hamamatsu Photonics K.K. Method of manufacturing a semiconductor device formed using a substrate cutting method
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US8889525B2 (en) 2002-03-12 2014-11-18 Hamamatsu Photonics K.K. Substrate dividing method
US9543256B2 (en) 2002-03-12 2017-01-10 Hamamatsu Photonics K.K. Substrate dividing method
US9548246B2 (en) 2002-03-12 2017-01-17 Hamamatsu Photonics K.K. Substrate dividing method
US9553023B2 (en) 2002-03-12 2017-01-24 Hamamatsu Photonics K.K. Substrate dividing method
US9711405B2 (en) 2002-03-12 2017-07-18 Hamamatsu Photonics K.K. Substrate dividing method
US10622255B2 (en) 2002-03-12 2020-04-14 Hamamatsu Photonics K.K. Substrate dividing method
US8865566B2 (en) 2002-12-03 2014-10-21 Hamamatsu Photonics K.K. Method of cutting semiconductor substrate
WO2007040032A1 (en) * 2005-10-04 2007-04-12 Lintec Corporation Transfer device and transfer method
JP2014143313A (en) * 2013-01-24 2014-08-07 Disco Abrasive Syst Ltd Extension device and extension method
CN104916594A (en) * 2014-03-14 2015-09-16 株式会社东芝 Semiconductor manufacturing device and manufacturing method of semiconductor device
CN108933085A (en) * 2017-05-29 2018-12-04 琳得科株式会社 Separator and separation method
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