JPH07230698A - Semiconductor device and its test device - Google Patents

Abstract

PURPOSE:To increase a rate in which a device provided with a redundant circuit is manufactured as a perfect good product and to improve throughput by storing address information corresponding to a defective memory cell in a non-volatile element. CONSTITUTION:When a defective memory cell is confirmed in a test device, a defective row address corresponding to a row in a memory cell array 1 is generated. This address is supplied to a control circuit 17 for redundancy, and stored in an address decoder for redundancy. When a row address corresponding to a defective row in the array 11 is supplied to a row address buffer/decoder 13 at the time of use, a row line for redundancy of the cell row 12 is selected by a row address decoder for redundancy of a redundant memory cell row 12 based on an internal address signal generated in the decoder 13 at the time. Further, selecting operation of the row line by the decoder 13 is prohibited by the circuit 17. Therefore, a defective row in the array 11 is substituted with the redundant memory cell of the cell row 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DRAM, SRAM.
Etc. and a semiconductor device having a redundant circuit for controlling replacement of a defective memory cell and a redundant memory cell in the memory circuit, and whether or not to inspect the semiconductor device and use the redundant circuit The present invention relates to a semiconductor inspection device that performs such setting.

[0002]

2. Description of the Related Art With the increase in capacity and miniaturization of semiconductor devices,
It is expected that the number of circuit components will increase and the process steps will become complicated, and it will be more difficult to obtain a good semiconductor device in the future. In such a situation, in order to obtain a completely good semiconductor device, it is general to use a redundant circuit and replace the defective circuit portion with the redundant circuit portion. Particularly in the field of memory ICs (memory integrated circuits), defective memory cells in a memory cell array are replaced with spare memory cells for redundancy in row units or column units to improve the yield rate. In this case, in order to replace the defective memory cell with the spare memory cell, a redundant address decode circuit using a fuse circuit is used.

FIG. 5 shows the configuration of a conventional redundant address decode circuit. This address decoding circuit is provided with fuse circuits 51 of a number corresponding to the number of bits of the address signals A0, A1, A2, A3, ... An. One end of each of these fuse circuits 51 is connected to a node of the power supply voltage Vcc via a load circuit 52. The other end of the fuse circuit 51 has its gate connected to the above-mentioned address signals A0-A.
n (or their inverted signals / A0 to / An) are respectively connected to the respective drains of the MOS transistors 53. The sources of these MOS transistors 53 are connected to the ground voltage node. In addition,
The signal after decoding is amplified by the amplifier circuit 54, and the output of the amplifier circuit 54 is supplied to the row line or column select line of the spare memory cell for redundancy, so that the defective memory cell in the memory cell array becomes spare. The memory cells can be replaced in units of rows or columns.

In order to replace such a memory cell, it is necessary to selectively make the fuse circuit 51 non-conductive. As a method for that, the energy of a laser or the like is externally applied to fuse the fuse circuit to blow it out. There are two methods: electrically non-conducting and electrically non-conducting by passing a current through the fuse circuit. A redundancy device is used to blow the fuse circuit. To blow a fuse circuit, first, a memory chip is subjected to a probe test in a wafer state, a defective chip in which a defective memory cell exists is identified, and if the defective memory cell in this defective chip can be relieved, The X and Y coordinates of the memory chip on the wafer and the repair fuse blowing data are stored in the storage device. After that, the stored data is transferred to the redundancy device for repair. As another method, if a defective memory cell in a defective chip can be repaired by a probe test, X, Y on the wafer of the memory chip can be repaired.
Coordinates and repair fuse blowout data are stored in a storage device. After the probe test is completed for all the memory chips on the wafer, the fuse information is set to RS-232C, GP.
Data is transferred to a redundancy device via an information medium such as an IB, the fuse circuit of each memory chip is blown based on this information, and the redundancy memory cell is replaced for relief.

[0005]

By the way, as the miniaturization of semiconductor devices and the integration technology in the three-dimensional direction progress in the future, the processing accuracy of the fuse circuit for redundancy will become more and more severe. Along with this, various problems occur when the fuse circuit is blown. For example, consider a case where this fuse circuit is blown by applying energy such as a laser. In a semiconductor device, the fuse circuit is usually composed of a polycrystalline silicon layer, and its film thickness varies from wafer to wafer or from chip to chip due to problems in the manufacturing process. When the laser beam is scanned, the positional accuracy deteriorates due to the change in the reflectance of the laser and the size of the beam diameter. As a result, when the fuse circuit is not blown, or when the blown fuse circuit material is splashed, a contact failure or the like occurs in the lower portion of the fuse circuit. Further, in the current process method, there is a possibility that the material may become poor in laser reflection due to problems such as yield, and in the conventional semiconductor device having the redundant circuit, the percentage of non-defective products does not increase. There is.

Further, in order to obtain information on which fuse circuit is blown, a semiconductor device is electrically tested by using a function inspection device, and row or column address information of defective memory cells is obtained for each chip. It has gained. Then, this information is given to the laser applying device of the redundancy device, and the fuse circuit at the corresponding position is irradiated with the laser beam to blow it. At this time, the position of the fuse circuit corresponding to the address information on the chip is recognized, and the fuse circuit at the recognized position is blown. However, once the fuse is blown, the test cannot be performed again to relieve it. Therefore, it is necessary to be careful in specifying the fuse circuit position. Therefore, the accuracy of the irradiation position of the laser beam and the accuracy of the beam diameter are becoming stricter.

On the other hand, in order to supply the address information to the redundancy device, there is usually a method in which a floppy disk is used as a medium or the stored information is used by using a communication line such as RS-232C and GPIB. In either case, the order of wafers in each lot is manually checked. For example, when using a floppy disk, the disk number is checked, and then the floppy disks are set in the redundancy device in the order corresponding to the wafer. In this case, an error occurs due to an error in the setting order of the floppy disks, disappearance of information, destruction, etc. In order to prevent the occurrence of such mistakes, the number of checks performed manually must be increased, and the operating rate of the device will be reduced. On the other hand,
When address information is supplied to a redundancy device using a communication line, the information is unlikely to be erased or destroyed, but the information corresponding to the wafer is manually specified. However, in this case, a repair error occurs when a mistake is made in setting the wafer order, a file name of the repair information, or the like. Further, when the redundancy device itself has a small storage capacity of the relief information, it takes time to transfer the data after the probe test is completed, and the efficiency of the probe test is lowered.

[0008]

As described above, the conventional semiconductor device provided with the redundant circuit has a drawback that the rate of non-defective products does not increase as miniaturization and integration technology in the three-dimensional direction progress. Further, the conventional semiconductor inspection apparatus has a drawback that throughput is lowered because the function inspection apparatus and the laser application apparatus are different.

The present invention has been made in consideration of the above circumstances, and a first object of the present invention is to provide a semiconductor device having a redundant circuit capable of increasing the rate of non-defective products. It is in.

A second object of the present invention is to provide a semiconductor inspection device capable of improving throughput. According to another aspect of the present invention, a semiconductor device includes a memory cell array having a plurality of memory cells, a redundant memory cell used by replacing the defective memory cell in the memory cell array, and the redundant memory cell including the defective memory cell. A redundant control circuit for performing replacement control with a cell, wherein the redundant control circuit includes an electrically rewritable nonvolatile element in which address information corresponding to the defective memory cell is stored. The redundancy address decoding means and the control means for holding the address information for writing in the nonvolatile element and controlling the writing of this address information in the nonvolatile element.

Further, the semiconductor inspecting apparatus of the present invention includes an inspecting means for inspecting a plurality of semiconductor devices and generating address information corresponding to the defective memory cell when the defective memory cell exists in the memory cell array. Address information storage means for storing the address information generated by the inspection means, and a plurality of the above-mentioned semiconductors by generating a writing voltage used when writing the address information by the nonvolatile elements in the plurality of semiconductor devices. Write voltage generating means to be supplied to the device in parallel; address information output control means for controlling the output of the address information stored in the address information storage means to the corresponding semiconductor device; Control signal supply means for selectively supplying a write control signal for address information and a transfer control signal for address information to It is constructed from.

[0012]

In the semiconductor device of the present invention, the address information corresponding to the defective memory cell is stored in the nonvolatile element. The address information stored in the nonvolatile element is held by the address information holding / writing control means, and the address information is written in the nonvolatile element under the control of the address information holding / writing control means.

In the semiconductor inspection device of the present invention, the inspection means inspects the plurality of semiconductor devices, and when there is a defective memory cell in the memory cell array, the address information corresponding to the defective memory cell is generated. This address information is stored in the address information storage means. Further, the write voltage generating means generates a write voltage used when writing the address information in the nonvolatile element, and supplies the write voltage to the plurality of semiconductor devices in parallel. Also,
The address information stored in the address information storage means is output to the corresponding semiconductor device by the address information output control means. Further, the control signal supply means selectively supplies the address information write control signal and the address information transfer control signal to the plurality of semiconductor devices.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a semiconductor device according to the present invention as a memory I.
It is a block diagram which shows the whole structure when it implements in C. This memory IC is provided with a memory cell array 11, a redundant memory cell row 12, a row address buffer / decoder 13, a sense circuit 14, an I / O circuit 15, a column address buffer / decoder 16 and a redundancy control circuit 17. .

In the memory cell array 11, memory cells such as DRAM cells and SRAM cells are arranged in a matrix. These memory cells are commonly connected to one of a plurality of row lines in a row unit and commonly connected to one of a plurality of column lines in a column unit. A redundant memory cell row 12 is provided with a redundant memory cell which is used by replacing the defective memory cell in the memory cell array 11 with the defective memory cell in a row unit. These redundant memory cells are commonly connected to the redundant row line. Usually, a plurality of redundant row lines are provided. The row address buffer / decoder 13 generates an internal row address signal based on the row address signal, and selects a row line of the memory cell array 11 according to the internal row address signal. The sense circuit 14 detects data stored in one row of memory cells in the memory cell array 11 selected by the row address buffer / decoder 13. The data detected by the sense circuit 14 is supplied to the I / O circuit 15. The column address buffer / decoder 15 generates an internal column address signal based on the column address signal. Activation control of the I / O circuit 15 is performed according to the internal column address signal. The redundancy control circuit 17 has a function of storing a defective row address corresponding to the defective memory cell when the defective memory cell is generated in the memory cell array 11 at the time of inspection, and the defect at the time of actual use after the inspection. Redundancy having a function of replacing one memory cell in the memory cell array 11 in which the defective memory cell exists when the internal row address signal corresponding to the row address is supplied with the memory cell in the redundant memory cell row 12 on a row-by-row basis. A row address decoder is provided.

In the memory IC having such a structure, an inspection device (not shown) inspects whether a memory cell in the memory cell array 11 has a defect. This inspection is performed as follows, for example. First, predetermined data is stored in each memory cell in the memory cell array 11, and then these stored data are read out. Then, the read data is compared with the original data, and if they do not match, it is determined that the memory cell is defective. If it is confirmed that the defective memory cell is generated, the inspection device generates a defective row address corresponding to the row in the memory cell array 11 in which the defective memory cell exists. This defective row address is supplied to the redundancy control circuit 17 and stored in the redundancy row address decoder.

At the time of actual use after the above inspection is completed, the memory cell in the memory cell array 11 is selected according to the row address signal and the column address signal, and further the I / O circuit 15 is selected.
Data is read or written via. When the row address buffer / decoder 13 is supplied with the row address signal corresponding to the defective row in the memory cell array 11, at this time, the row address buffer / decoder 13
The redundant row address decoder of the redundant control circuit 17 selects the redundant row line of the redundant memory cell row 12 based on the internal row address signal generated at. Further redundant control circuit
The row address buffer / decoder 13 inhibits the row line selection operation by 17. Therefore, in this case, the defective row in the memory cell array 11 is replaced with the redundant memory cell of the redundant memory cell row 12.

FIG. 2 shows a detailed configuration including the redundancy row address decoder in the redundancy control circuit 17 and its control circuit. This redundant row address decoder has
As an element for storing the defective row address, an EPROM cell 21 capable of erasing data by irradiation of ultraviolet rays
Are provided in plural. These EPROM cells 21 have a source, a drain, a control gate and a floating gate.
One end of the current path between the drains is commonly connected to a node 22 which obtains a decode signal. The node 22 is provided with an amplifier circuit 23 for amplifying the signal of the node and driving the redundant row line with a sufficient amplitude. Further, a load circuit is provided between the node 22 and a node to which a power supply voltage Vcc or a high voltage VPG for writing described later is applied.
24 are connected. At the other end of the current path between the source and drain of each of the EPROM cells 21, a decoding MO is provided.
The S-transistor 25 is connected to the ground voltage node via each source and drain. The control gate of each EPROM cell 21 has a defective address holding / writing control circuit 26 for controlling the redundant row address decoder.
It is connected to the.

Each MOS transistor 25 for decoding
The gates of the internal row address signals A0, A1, A2, ...
n (or their inverted signals / A0, / A1, / A
2, ... / An) are supplied. In addition, each of the above EPROMs
At the node where the other end of the current path between the source and drain of the cell 21 and the source and drain of each of the decoding MOS transistors 25 are connected, an M for write control is connected.
One end of each current path between the source and drain of the OS transistor 27 is connected. These MOS transistors 27
Is controlled to be turned on when data is written to the EPROM cell 21, its gates are connected in common, and this common gate is connected to the defective address holding / writing control circuit 26. Has been done.

Defect address holding / writing control circuit
The reference numeral 26 temporarily holds a defective row address corresponding to a defective memory cell in the memory cell array 11 when the memory IC of this embodiment is inspected.
The defective row address is controlled to be written in the PROM cell 21, and the data DATA-IN corresponding to the defective row address, the write control signal W, the high voltage VPG for writing, and the clock signal CK synchronized with the data.
Is supplied. The clock signal CK is also supplied to the flag register 28, and the flag register 28 outputs a signal SIG indicating that the clock signal CK has been supplied.

In the circuit having such a structure, when a defect occurs in the memory cell in the memory cell array in the corresponding memory IC, the data corresponding to the defective row address is sent to the defective address holding / writing control circuit 26. DAT
A-IN is supplied as serial data, and the write control signal W, the high voltage VPG for writing, and the clock signal CK are also supplied. In the defective address holding / writing control circuit 26, the data DATA-IN is temporarily held in the internal register in synchronization with the clock signal CK. Then, based on the data held in the register, each E
The high voltage VPG for writing is selectively supplied to the control gate of the PROM cell 21. At this time, each of the MOS transistors 27 holds the defective address /
It is turned on by the output from the write control circuit 26, and the high voltage VPG is supplied to the load circuit 24.
As a result, the EPROM cell 21 whose control gate is supplied with the high voltage VPG is turned on, and the EPROM cell 21 is turned on.
A current flows between the drains, and the electrons generated thereby are attracted to the floating gates and accumulated there, so that the threshold voltage rises and data is written. On the other hand, the EPROM cell 21 to which the high voltage VPG is not supplied to the control gate is turned off, and its threshold voltage is kept low. Then, the EPROM cell 21 having the increased threshold voltage is in a high resistance state between the source and the drain, which causes a state similar to that of a conventional blown fuse circuit.

When a row address signal corresponding to a defective row in the memory cell array 11 is supplied during actual use, an internal row address signal generated by the row address buffer / decoder 13 at this time is supplied to the MOS transistor 25. Supplied to each gate. At this time, the power supply voltage Vcc is supplied to the load circuit 24. By supplying the internal row address signal corresponding to the defective row, the node 22 becomes the ground level, and this ground level is supplied to the redundancy row line through the amplifier circuit 23, thereby providing the redundancy memory cell. The redundant row line of row 12 is selected. In addition, the row address buffer / decoder 13 is output by an output from a circuit portion not shown.
The row line selection operation by is prohibited.

On the other hand, when the clock signal CK is supplied, the output signal SIG of the flag register 28 is activated, for example, set to a high level. Therefore, by detecting that the signal SIG is set to the high level, it can be confirmed that the redundancy function is used in this memory IC.

FIG. 3 is a block diagram showing the configuration of a memory IC inspection apparatus according to an embodiment of the semiconductor inspection apparatus of the present invention for inspecting the memory IC of the above embodiment in a wafer state. The memory IC inspection device 30 includes an inspection unit 31 that performs control for functional inspection of the memory IC and address data DATA-OUT necessary for using the redundant function of each memory IC in each memory IC, and writing. Control signal W, high voltage VPG for writing and clock signal CK
And a redundant control unit 32 for generating

The inspection section 31 is composed of a CPU and the like, and a control circuit 33 for controlling the entire inspection and inputting / outputting data.
A timing / pattern generation circuit 34 that generates a timing signal for timing control and a pattern for inspection, and various input signal currents and voltages to be supplied to the memory IC at the time of inspection, and an output signal current and voltage from the memory IC. It is composed of a test current / voltage supply measuring circuit 35 for measuring the temperature, a memory circuit 36 for storing an inspection program, and the like.
The inspection unit 31 performs a function inspection by applying a predetermined pattern data or a current or voltage having a predetermined value to a memory IC to be inspected and detecting an output signal from the memory IC, and also performs a current / voltage characteristic. To measure. Further, the inspection unit 31 detects whether or not there is a defective memory cell in the memory cell array of the memory IC by the function inspection. When it is confirmed that the defective memory cell exists, the wafer lot number of the memory IC, the X and Y coordinates on the wafer where the memory IC is located, and the row address of the position where the defective memory cell exists. Data such as (defective row address) is generated. These data are supplied to the redundancy control unit 32 as repair data.

The redundancy control section 32 has a storage device 37 for storing the rescue data supplied from the inspection section 31 and output terminals of the number corresponding to the number of memory ICs on the wafer. A data register circuit 38 which outputs serial data corresponding to the defective row address from each output terminal in parallel as DATA-OUT1 to DATA-OUTn when the defective memory cell exists in the IC, and each corresponds to the number of memory ICs on the wafer. A write control / clock signal generation circuit 39 which outputs the write control signal W and the clock signal CK, a high voltage generation circuit 40 which generates the high voltage VPG for writing, and a redundancy control section.
32 and a control circuit 41 for controlling the overall operation.

The data DATA-OUT1 to DATA
-OUTn is the data DATA- as shown in FIG.
A plurality of the memory ICs as IN1 to DATA-INn
And the write control signal W and the clock signal CK are also independently supplied to the plurality of memory ICs. The high voltage VPG is commonly supplied to a plurality of memory ICs.

In the inspection device having such a structure, the inspection unit 31 inspects the memory IC on the wafer. As a result, if there is a defective memory cell, the relief device stored in the storage device 37 is used. Address data of
It is supplied to the data register circuit 38, and thereafter, data DATA-OUT1 to DA
The write control / clock signal CK is output from the write control / clock signal generating circuit 39 and the high voltage VPG for writing is output from the high voltage generating circuit 40 to the corresponding memory IC as TA-OUTn.
Is output to. By outputting such signals and voltages, write control of defective row addresses corresponding to defective memory cells as described above is performed in parallel in a plurality of memory ICs.

After writing the defective row address, the functional test is performed again. In this case, all of the functional test items may be performed, or only the functional test items regarding whether or not there is a defective memory cell may be performed. If the wafer is judged to be non-defective in this test, the wafer is divided into individual IC chips, housed in a package, and shipped as a product. On the other hand, when a defective memory cell is found in the function test again, the EPRs in the memory IC are previously stored.
The data written in the OM cell is erased and rewritten. Data erasing in the EPROM cell is performed by selectively irradiating the memory IC at a corresponding position on the wafer with ultraviolet rays, or by irradiating the entire wafer with ultraviolet rays. When selectively irradiating ultraviolet rays, the functional test may be performed only on the memory ICs that have been irradiated with ultraviolet rays. When the entire wafer is irradiated with ultraviolet rays, the functional test may be performed again on all the memory ICs on the wafer. To do. Such a retest is performed based on the inspection program stored in the memory circuit 36, and the number of times the retest is performed can be freely set. It is good in terms of reliability and equipment usage efficiency.

As described above, in the memory IC of the above embodiment, the redundancy address is the EPROM which is a non-volatile storage element.
The memory IC inspection device generates a redundant address and supplies the redundant address to the memory IC. Therefore, the processing accuracy due to the problem of the redundant fuse circuit that has been conventionally used is caused. The redundant address can be replaced without being affected by the film quality which is easily influenced by the manufacturing process. Further, in the prior art, if a fuse circuit fuse failure occurs, the memory IC cannot be repaired. However, according to the above embodiment, the redundancy address is stored in the non-volatile storage element, and the erase operation is performed. Since rewriting is possible, the address can be written again even if a write error occurs. As a result, it is possible to increase the proportion of the memory IC of the above-described embodiment that is a non-defective product.

Further, in the conventional inspection apparatus, a redundancy device including a laser device, for example, is required for fusing the fuse circuit for address replacement, but this is unnecessary in the memory IC inspection apparatus of the above-mentioned embodiment, so that the capital investment is not required. It is possible to reduce the number of workers, improve space efficiency, and remove personnel because maintenance of the laser device is unnecessary.
In addition, since a redundancy device is not required and the address is electrically replaced, the throughput can be improved.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the memory IC of the above-mentioned embodiment, when a defective memory cell is generated in the memory cell array, it is replaced with the memory cell in the redundant memory cell row in row units. However, this is replaced by the redundant memory cell row instead of the redundant memory cell row. Of course, a cell column may be provided, and when a defective memory cell is generated, the defective memory cell may be replaced with the memory cell in the redundant memory cell column on a column-by-column basis. The control circuit will store the column address corresponding to the defective memory cell, and the memory I of FIG.
The C inspection device will generate a defective column address.

Further, in the above embodiment, the case where the EPROM cell is used as the non-volatile element for storing the defective address has been described, but it is also possible to use the EEPROM cell which can electrically erase the data. This EE
When the PROM cell is used, the ultraviolet ray erasing step like that of the EPROM cell is not necessary and the ultraviolet ray irradiation device is also unnecessary. Further, it goes without saying that it can be applied to a memory embedded CPU and the like.

[0034]

As described above, according to the present invention,
It is possible to provide a semiconductor device provided with a redundant circuit capable of increasing the rate of non-defective products, and a semiconductor inspection device capable of improving throughput.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration when a semiconductor device of the present invention is applied to a memory IC.

FIG. 2 is a circuit diagram showing a detailed configuration of a partial circuit of the apparatus of the above-described embodiment.

FIG. 3 is a block diagram showing an overall configuration when a semiconductor inspection device of the present invention is applied to a memory IC inspection device.

FIG. 4 is a circuit diagram showing a connection state between the memory IC inspection apparatus of FIG. 3 and the plurality of memory ICs of FIG.

FIG. 5 is a circuit diagram showing a configuration of a conventional redundant address decode circuit.

[Explanation of symbols]

11 ... Memory cell array, 12 ... Redundant memory cell row, 13 ... Row address buffer / decoder, 14 ... Sense circuit, 15 ... I
/ O circuit, 16 ... Column address buffer / decoder, 17 ... Redundant control circuit, 21 ... EPROM cell, 23 ... Amplifier circuit, 24
… Load circuit, 25… Decoding MOS transistor, 26
... defective address holding / writing control circuit, 27 ... writing control MOS transistor, 28 ... flag register,
30 ... Memory IC inspection device, 31 ... Inspection unit, 32 ... Redundancy control unit, 33 ... Control circuit, 34 ... Timing / pattern generation circuit, 35 ... Test current / voltage supply measurement circuit, 36 ... Storage circuit,
37 ... Storage device, 38 ... Data register circuit, 39 ... Write control / clock signal generation circuit, 40 ... High voltage generation circuit, 41
... control circuit.

Claims (3)

[Claims] 1. A memory cell array having a plurality of memory cells, a redundant memory cell used in place of the defective memory cell in the memory cell array, and the defective memory cell being the redundant memory cell. A redundancy control circuit for performing replacement control, wherein the redundancy control circuit includes a redundancy element including an electrically rewritable nonvolatile element in which address information corresponding to the defective memory cell is stored. A semiconductor characterized by comprising address decoding means and control means for holding address information for writing to the non-volatile element and controlling the writing of this address information to the non-volatile element. apparatus. 2. The redundancy control circuit generates a signal indicating that the address information has been written to the nonvolatile element and the defective memory cell has been replaced with the redundancy memory cell. The semiconductor device according to claim 1, further comprising a circuit. 3. A memory cell array provided with a plurality of memory cells, a redundant memory cell used in place of the defective memory cell in the memory cell array, and an electrical circuit storing address information corresponding to the defective memory cell. A testing device for a semiconductor device, comprising: a redundant control circuit for controlling replacement of the defective memory cell with the redundant memory cell, including a nonvolatile element capable of rewriting data, Inspection means for inspecting the semiconductor device and generating address information corresponding to the defective memory cell when there is a defective memory cell in the memory cell array, and address information storage means for storing the address information generated by the inspection means And a writing voltage used when writing address information with a plurality of nonvolatile elements in the semiconductor device. Write voltage generating means for generating a pressure and supplying the same in parallel to the plurality of semiconductor devices, and address information output control for controlling output of the address information stored in the address information storage means to a corresponding semiconductor device. A semiconductor inspection apparatus comprising: means and a control signal supply means for selectively supplying a write control signal for address information and a transfer control signal for address information to a plurality of the semiconductor devices.