JP3603045B2 - Semiconductor storage device, inspection jig thereof, and inspection method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated device, and more particularly to a semiconductor memory device having a built-in self-diagnosis function and a test method therefor.
[0002]
[Prior art]
In an LSI product having a built-in electrically rewritable nonvolatile memory element, the test time for writing and erasing is extremely long, and there is a problem that the test time is increased. In particular, the number of test vectors increases with an increase in the bit capacity and with higher performance and higher functionality of the product, resulting in a further increase in inspection cost. For these reasons, in an LSI product having a built-in nonvolatile memory element, it is essential to reduce the inspection time using the self-diagnosis function built in the LSI in order to reduce the manufacturing cost.
[0003]
As a typical self-diagnosis function, there is a built-in self-test (hereinafter abbreviated as “BIST”). The BIST is characterized by having a test pattern generating means and a test result evaluating means in the LSI and performing a self test.
[0004]
FIG. 19 is a block diagram showing a configuration example of a conventional semiconductor memory device having a built-in BIST circuit. In FIG. 19, 1 is a nonvolatile memory device, 2 is a nonvolatile memory cell array including a user use area 4 and a redundant area 5, and 3 is a decoder and a sense amplifier for controlling read / write of the nonvolatile memory cell array 2. , A memory peripheral circuit including a control circuit, etc., 6 is a BIST circuit including a mode generation circuit, an address generation circuit, a data generation circuit, an output result comparison circuit, etc., and 7 is an output of an output result comparison circuit included in the BIST circuit 6. A BIST result storage memory 8 stores a BIST activation terminal for activating the BIST circuit.
[0005]
In the semiconductor memory device configured as described above, when a signal for activating the BIST circuit is applied to the BIST activation terminal 8, the BIST circuit 6 is activated. The mode generation circuit of the BIST circuit 6 supplies the signal to the memory peripheral circuit 3, and sets each mode of erasing, writing, and reading. Next, an address suitable for the mode is generated from the address generation circuit. Further, when the operation is completed, the output result comparison circuit compares the result output from the data terminal with the result output from the data generation circuit, and stores the result in the BIST result storage memory 7. In this procedure, self-diagnosis is repeated for all areas of the memory.
[0006]
As another conventional example, FIG. 20 is a block diagram showing a configuration example of a semiconductor memory device including a conventional BIST circuit, a CPU, a RAM, and the like. Reference numeral 10 denotes a semiconductor memory device having a CPU, a RAM, and the like mounted thereon, reference numeral 2 denotes a nonvolatile memory cell array including a user use area 4 and a redundant area 5, reference numeral 3 denotes a decoder for controlling read / write of the nonvolatile memory cell array 2, A memory peripheral circuit including a sense amplifier, a control circuit, and the like, a BIST circuit including a ROM 14 and the like for causing the CPU to perform mode generation, address generation, data generation, output result comparison, and the like; 12, a CPU; Reference numeral 7 denotes a BIST result storage memory for storing the output result comparison contents of the CPU 12, and reference numeral 8 denotes a BIST activation terminal for activating the BIST circuit.
[0007]
In the semiconductor memory device configured as described above, when a signal for starting the BIST circuit is applied to the BIST start terminal 8, the BIST circuit 11 starts. The CPU 12 generates a mode, generates an address, and generates data in accordance with the output code of the ROM 14 of the BIST circuit 11 and supplies the mode to the memory peripheral circuit 3. The output result is compared with the operation result and the expected value, and the output result comparison content is stored in the BIST result storage memory 7. In this procedure, self-diagnosis is repeated for all areas of the memory.
[0008]
Further, a conventional wafer inspection method for a semiconductor memory device having a BIST circuit as described above is described.
[0009]
FIG. 21 is a schematic diagram of a configuration for implementing a conventional wafer inspection method for a semiconductor memory device having a built-in BIST circuit. Reference numeral 20 denotes a wafer, reference numeral 21 denotes a chip to be inspected (DUT: device under test), reference numeral 22 denotes a jig for connecting the chip 21 on the wafer 20 to the semiconductor inspection device (hereinafter, referred to as a “probe card”), Reference numeral 23 denotes a probe group for connecting to pads on the chip 21, and reference numeral 24 denotes a semiconductor inspection device (hereinafter, referred to as an "LSI tester").
[0010]
In the configuration for implementing the above-described wafer inspection method for a semiconductor memory device, a BIST activation signal is applied from an LSI tester 24 via a probe 23 to a DUT 21 which is a semiconductor memory device having a built-in BIST circuit. Particularly, in order to inspect the wafer 20 at one time, the probe card 22 is provided with probes 23 for all chips. Each chip performs a self-diagnosis in response to the BIST activation signal, and stores the result in each BIST result storage memory. The LSI tester 24 reads this result and discriminates a non-defective / defective product. With such a configuration, there is an advantage that the wafer inspection can be performed at a time using the BIST function.
[0011]
Further, a proposal for a wafer inspection method as shown in FIG. 22 has been made. In FIG. 22, 20 is a wafer, 21 is a DUT, 25 is a power supply terminal common to each chip, and 26 is a power supply line common to each chip.
[0012]
In the configuration for implementing the wafer inspection method for a semiconductor memory device as described above, each DUT 21 which is a nonvolatile memory device having a built-in BIST circuit uses a power-on from a power supply terminal 25 as a BIST activation signal, and each chip performs its own operation. The diagnosis is performed, and the result is stored in each BIST result storage memory. With such a configuration, there is an advantage that an LSI tester or a probe card in which probes are provided for all chips are not required when performing self-diagnosis.
[0013]
[Problems to be solved by the invention]
However, in the conventional semiconductor memory device having a built-in BIST circuit, a circuit dedicated to the BIST including a mode generation circuit, an address generation circuit, a data generation circuit, an output result comparison circuit, and the like as shown in FIG. 19 is required for the BIST. This causes an increase in the chip area of the semiconductor memory device. Further, since the inspection is performed by the BIST circuit, there is a problem that a margin test as performed by an LSI tester cannot be performed.
[0014]
Also, in a conventional semiconductor memory device having a BIST circuit, a CPU, a RAM, and the like, a ROM as shown in FIG. 20 is required for the BIST operation. Must be provided in the chip, which further increases the chip area. In addition, since the portion for storing the command data for the BIST operation is the built-in ROM, it is necessary to perform various types of BISTs (for example, burn-in tests and shipping inspections at the manufacturer side, set inspections at customer sites, etc.). In addition, there is a problem that a ROM capacity for the inspection is required, which leads to an increase in chip area and an increase in manufacturing cost.
[0015]
Further, in a wafer inspection of a semiconductor memory device having a built-in BIST circuit, as shown in FIG. 21, a probe card or an LSI tester provided with probes for all chips is required, which causes an increase in inspection cost. In the wafer inspection provided with a common power supply line for each chip as shown in FIG. 22 for the purpose of not requiring these devices, when one chip has a DC inspection failure, the other chips are adversely affected. In addition, there is a problem that the function test cannot be performed. This problem has a similar adverse effect on an apparatus for probing all chips as shown in FIG. Further, in the configuration shown in FIG. 22, since there are wires on the scribe lane, particles may be generated at the time of chip cutting, which may cause a defect.
[0016]
In addition, since a DC inspection cannot be performed in these wafer inspections, a wafer inspection must be performed once with an LSI tester in order to remove a DC defect, so that the inspection with the LSI tester is completely eliminated. It is not possible.
[0017]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the circuit area required for a BIST as much as possible and to suppress an increase in manufacturing cost, and to significantly increase the inspection time. It is an object of the present invention to provide a method of inspecting a semiconductor memory device, which is shortened.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, a first semiconductor memory device according to the present invention is a semiconductor memory device having a self-diagnosis function, comprising a user use area and a mask ROM cell storing self-diagnosis instruction data. A self-diagnosis instruction data transferred from the mask ROM cell in response to an external self-diagnosis start signal; a non-volatile memory cell array based on the self-diagnosis instruction data transferred from the RAM; And a CPU for performing self-diagnosis of a user use area of the volatile memory cell array on the same chip.
[0019]
According to this configuration, the BIST operation can be realized by only slightly increasing the cell area of the mask ROM without requiring a special BIST circuit.
[0020]
In order to achieve the above object, a second semiconductor memory device according to the present invention is a semiconductor memory device having a self-diagnosis function, comprising a user-usable area and a rewritable nonvolatile memory storing self-diagnosis instruction data. A non-volatile memory cell array having memory cells, a RAM in which self-diagnosis instruction data is transferred from a rewritable non-volatile memory cell in response to an external self-diagnosis activation signal, and a self-diagnosis transferred from the RAM CPU for self-diagnosing a user use area of the nonvolatile memory cell array based on instruction data for use on the same chip.
[0021]
According to this configuration, in addition to the advantage of the first semiconductor memory device, the instruction data for the BIST operation is stored in the rewritable nonvolatile memory cell. Therefore, by rewriting the contents, many types of BIST (for example, It is possible to perform a burn-in test and a shipping inspection on a maker side, a set inspection at a customer site, and the like, thereby preventing an increase in chip area and an increase in manufacturing cost.
[0024]
To achieve the above object, the present invention 3 Is a semiconductor memory device having a self-diagnosis function for a plurality of built-in nonvolatile memory cell arrays, wherein each of the plurality of nonvolatile memory cell arrays has a user use area and a rewritable nonvolatile memory cell. A specific non-volatile memory cell array having a rewritable non-volatile memory cell storing instruction data for self-diagnosis, and a specific non-volatile memory cell array in response to an external self-diagnosis start signal And a CPU for self-diagnosing a user use area of another non-volatile memory cell array based on the self-diagnosis instruction data transferred from the non-volatile memory cell.
[0025]
According to this configuration, 1st and 2nd In addition to the advantages of the semiconductor memory device described above, the BIST operation command data is stored in the rewritable nonvolatile memory cell. Inspection, set inspection at the customer site, etc.), an increase in chip area can be prevented, and an increase in manufacturing cost can be suppressed.
[0026]
1st to 1st 3 The semiconductor memory device may include: means for generating a plurality of test reference voltages based on a control signal from a CPU; and means for testing a nonvolatile memory cell array with a voltage generated from the test reference voltages. preferable.
[0027]
According to this configuration, it is possible to generate a plurality of inspection voltages in addition to the internal voltage used for normal operation with a single power supply from outside the semiconductor memory device, and realize a voltage margin inspection by performing a self-diagnosis of the nonvolatile memory cell array. it can.
[0028]
Also, from the first to the 3 The semiconductor memory device preferably includes: means for generating a plurality of test frequencies based on a control signal from the CPU; and means for testing the nonvolatile memory cell array with a boosted power source generated from the test frequencies. .
[0029]
According to this configuration, a plurality of test frequencies can be generated in addition to the frequency used for the normal boosting operation, and the current capability margin test of the booster circuit can be realized by self-diagnosis of the nonvolatile memory cell array.
[0030]
Also, from the first to the 3 Means for selecting, based on a control signal from a CPU, a plurality of inspection determination levels for inspecting a threshold voltage distribution of the nonvolatile memory cell array after normal writing and after erasing, It is preferable to include means for inspecting the nonvolatile memory cell array based on the determined inspection determination level.
[0031]
According to this configuration, in addition to the determination level used for the normal read operation, a test determination level that can inspect the threshold voltage Vt distribution after normal writing and erasing can be selected, and the read operation can be performed by the self-diagnosis of the nonvolatile memory cell array. Vt margin inspection can be realized.
[0032]
Also, from the first to the 3 Means for selecting a plurality of function test determination levels for testing a rewriting function of a nonvolatile memory cell array based on a slight change in a threshold voltage of the nonvolatile memory cell array based on a control signal from a CPU. And means for inspecting the nonvolatile memory cell array based on the selected inspection determination level.
[0033]
According to this configuration, in addition to the judgment level used for the normal read operation, a judgment level for function inspection that can check the rewriting function can be selected. Can be inspected in a short time.
[0034]
Also, from the first to the 3 The semiconductor memory device includes means for writing the result of the self-diagnosis performed by the CPU to the information storage area in the nonvolatile memory cell array, and rank selection data according to the characteristics based on the result of the self-diagnosis read from the information storage area. And a means for outputting the calculation to the outside.
[0035]
According to this configuration, it is possible not only to judge a good / defective product by the self-diagnosis, but also to implement a sorting shipment according to various electrical characteristics based on the rank sorting data output outside the semiconductor memory device.
[0036]
Also, from the first to the 3 The semiconductor memory device according to the present invention has a means for writing the result of the self-diagnosis performed by the CPU to the first information storage area in the non-volatile memory cell array and a characteristic corresponding to the characteristic based on the self-diagnosis result read from the first information storage area. Means for calculating and outputting rank selection data to the outside; redundancy switching of the nonvolatile memory cell array based on the rank selection data and the selection shipping information stored in advance in the second information storage area in the nonvolatile memory cell array And a means for controlling
[0037]
According to this configuration, not only the sorting and shipping according to each electrical characteristic by the self-diagnosis can be performed, but also the redundancy remedy can be performed depending on the rank of the defective product, and the remedy rate can be improved.
[0038]
Also, from the first to the 3 The semiconductor memory device according to the first aspect has a means for writing power-off information based on a test result performed by an external tester (LSI tester) to an information storage area in a nonvolatile memory cell array, and a power-off information read from the information storage area. And a switch circuit for disconnecting the power supply line.
[0039]
According to this configuration, when the result of the DC test inspected by the LSI tester is defective, the power supply line is cut off, and the self-diagnosis is realized without the DC defect having an adverse effect on the good chip in the wafer batch inspection. be able to.
[0040]
In order to achieve the above object, a semiconductor memory device inspection jig according to the present invention includes first to 3 A jig for inspecting a wafer on which a plurality of semiconductor memory devices are mounted, wherein the first jig is provided at the center and electrically connected to all pads of the semiconductor memory device to be probe-tested. A probe, and a plurality of second probes provided on the left and right of the first probe for electrically connecting to a self-diagnosis pad of a semiconductor memory device to be subjected to a self-diagnosis test. .
[0041]
In order to achieve the above object, a method for inspecting a semiconductor storage device according to the present invention is an inspection method using the inspection jig according to the present invention, wherein the first probe of the inspection jig connected to the semiconductor inspection device is provided. A self-diagnosis test is performed on the semiconductor memory device to which the second probe is connected while a probe test is performed on the semiconductor memory device to which the second probe is connected.
[0042]
Also, from the first to the 3 The semiconductor memory device includes means for writing the test progress of the self-diagnosis performed by the CPU to the information storage area in the nonvolatile memory cell array, means for reading the test progress from the information storage area and outputting the test progress to the outside, It is preferable to include means for determining an inspection to be performed first when the inspection is restarted based on the progress.
[0043]
According to the above configuration, while the LSI tester is performing the DC test or the BIST test of the chip to be probe-tested, it is possible to perform the BIST test on the adjacent chip, thereby reducing the test time. Significant shortening can be achieved.
[0044]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0045]
(1st Embodiment)
FIG. 1 is a block diagram showing a configuration example of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, reference numeral 100 denotes a semiconductor memory device having a CPU, RAM, etc. mounted thereon, 2 denotes a nonvolatile memory cell array including a user use area 4 and a mask ROM cell 110 for storing test sequence data for BIST, A memory peripheral circuit including a decoder, a sense amplifier, a control circuit, and the like for controlling read / write of the nonvolatile memory cell array, 8 a BIST start terminal for starting a BIST operation, 12 a CPU, 13 a RAM, and 113 a RAM A BIST data transfer signal from the mask ROM cell 110, 114 is a CPU control signal line for BIST data, and 115 is a rewrite control signal line for the CPU 12.
[0046]
Next, the operation of the semiconductor memory device thus configured will be described. When power and CLK are supplied to the semiconductor memory device 100 and a signal for activating the BIST operation is applied to the BIST activation terminal 8, the RAM 13 is transferred from the mask ROM cell 110 to the RAM 13 via the BIST data transfer signal line 113. Then, test sequence data for BIST is transferred. Next, the RAM 13 outputs the internal test sequence data to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test of the user use area 4 in the nonvolatile memory cell array 2 via the rewrite control signal line 115.
[0047]
According to the above operation, the BIST operation can be realized by only slightly increasing the cell area of the mask ROM without requiring a special BIST circuit.
[0048]
(Second embodiment)
FIG. 2 is a block diagram showing a configuration example of the semiconductor memory device according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that a mask ROM cell 110 for storing test sequence data for BIST in the nonvolatile memory cell array 2 according to the first embodiment is replaced with a rewritable nonvolatile memory cell. (For example, a flash memory cell) 120.
[0049]
The operation of the semiconductor memory device configured as described above is the same as that described in the first embodiment, does not require a special BIST circuit, and increases the BIST by slightly increasing only the cell area of the rewritable nonvolatile memory. Operation can be realized.
[0050]
Further, since the instruction data for the BIST operation is stored in the rewritable nonvolatile memory, the contents of the BIST operation can be rewritten so that various types of BIST (for example, a burn-in test at a manufacturer, a shipping inspection, a set inspection at a customer site, etc.). ) Can be performed, an increase in chip area can be prevented, and an increase in manufacturing cost can be suppressed.
[0051]
(Third embodiment)
FIG. 3 is a block diagram showing a configuration example of the semiconductor memory device according to the third embodiment of the present invention. In FIG. 3, reference numeral 100 denotes a semiconductor memory device having a multi-bank configuration on which a CPU, a RAM and the like are mounted, and reference numeral 2 denotes a nonvolatile memory including a user use area 4 and mask ROM cells 130 and 131 for storing test sequence data for BIST. 3, a memory peripheral circuit including a decoder for controlling read / write of the nonvolatile memory cell arrays 130 and 131, a sense amplifier, a control circuit, and the like; 8, a BIST activation terminal for activating a BIST operation; Reference numeral 12 denotes a CPU, 114 denotes a CPU control signal line for BIST data, 115 denotes a rewrite control signal line by the CPU 12, 132 denotes a bank 0 side memory block including a nonvolatile memory cell array 2 and a memory peripheral circuit 3, and 133 denotes a nonvolatile memory. A cell comprising the cell array 2 and the memory peripheral circuit 3 Click 1 side memory block.
[0052]
Next, the operation of the semiconductor memory device thus configured will be described. When power, CLK, and the like are supplied to the semiconductor memory device and a signal for activating the BIST operation is applied to the BIST activation terminal 8, the test sequence data is transmitted from the mask ROM cell 131 of the memory block 133 on the bank 1 side. It is output to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test on the user use area 4 of the bank 0 side memory block 132 via the rewrite control signal line 115.
[0053]
With the above operation, a special BIST circuit or a RAM for the BIST operation is not required, and the BIST operation can be realized with a slight increase in only the cell area of the mask ROM. Since the present embodiment does not require a RAM for the BIST operation, it can be effective in a product that cannot control the CPU using the RAM.
[0054]
In the present embodiment, the case of a memory block having a two-bank configuration has been described. However, even if the number of banks increases, a certain bank can perform a self-diagnosis test on a plurality of other banks. Also, an example has been described in which the self-diagnosis test is performed on the memory block on the bank 0 side with the memory block on the bank 1 side.
[0055]
(Fourth embodiment)
FIG. 4 is a block diagram showing a configuration example of the semiconductor memory device according to the fourth embodiment of the present invention. The fourth embodiment is different from the third embodiment in that the mask ROM cell 130 for storing the BIST test sequence data of the memory block 132 on the bank 0 side of the third embodiment is replaced with a rewritable nonvolatile memory cell. The point that the mask ROM cell 131 for storing the test sequence data for the BIST of the bank 0 side memory block 133 is replaced with a rewritable nonvolatile memory (for example, a flash memory cell) 141 in the (for example, a flash memory cell) 140 is there.
[0056]
The operation of the semiconductor memory device thus configured is also the same as that described in the third embodiment, and does not require a special BIST circuit or BIST operation RAM, and is a cell area of a rewritable nonvolatile memory. The BIST operation can be realized with only a slight increase. Further, since the instruction data for the BIST operation is stored in the rewritable nonvolatile memory, the contents of the BIST operation can be rewritten so that various types of BIST (for example, a burn-in test at a manufacturer, a shipping inspection, a set inspection at a customer site, etc.). ) Can be performed, an increase in chip area can be prevented, and an increase in manufacturing cost can be suppressed.
[0057]
(Fifth embodiment)
FIG. 5 is a block diagram showing a configuration example of the semiconductor memory device according to the fifth embodiment of the present invention. Reference numeral 100 denotes a semiconductor memory device having a CPU, a RAM, and the like mounted thereon. 2 denotes a nonvolatile memory cell array including a user use area 4 and a memory area 150 (mask ROM or flash memory cell) for storing BIST test sequence data; Is a memory peripheral circuit including a decoder, a sense amplifier, a control circuit, and the like for controlling read / write of the nonvolatile memory cell array, 8 is a BIST start terminal for starting a BIST operation, 12 is a CPU, 13 is a RAM, Reference numeral 113 denotes a BIST data transfer signal line from the memory area 150 for storing BIST test sequence data, 114 denotes a CPU control signal line based on the BIST data, 115 denotes a rewrite control signal line by the CPU 12, and 151 denotes a reference voltage switching by the CPU 12. Signal line, 152 Reference voltage generating circuit for testing, the read-write voltage generation circuit 153, 154 is a power supply line for reading and rewriting.
[0058]
Next, the operation of the semiconductor memory device thus configured will be described. When power, CLK, and the like are supplied to the above-described semiconductor memory device and a signal for activating the BIST operation is applied to the BIST activation terminal 8, the test sequence data is transmitted from the memory area 150 to the BIST data transfer signal line 113. Via the RAM 13. Next, the RAM 13 outputs the internal test sequence data to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test of the user use area 4 in the nonvolatile memory cell array 2 via the rewrite control signal line 115.
[0059]
In the self-diagnosis test, the CPU 12 outputs a signal to the reference voltage switching signal line 151, and in accordance with the content, the test reference voltage generation circuit 152 performs a proper voltage margin test for performing a voltage margin test other than the normally used voltage. Generate a reference voltage for inspection. Using this test reference voltage, a test voltage is generated by a read / write voltage generation circuit 153, and the test voltage is applied to each control circuit via a power supply line 154 to perform a voltage margin self-diagnosis test.
[0060]
With the above operation, it is possible to generate a plurality of inspection voltages in addition to the internal voltage used for normal operation with a single power supply from outside the semiconductor memory device, and it is possible to realize a voltage margin inspection by self-diagnosis of the nonvolatile memory cell array. become.
[0061]
(Sixth embodiment)
FIG. 6 is a block diagram showing a configuration example of the semiconductor memory device according to the sixth embodiment of the present invention. The sixth embodiment is different from the fifth embodiment in that a test frequency control circuit 162 to which a frequency switching signal 161 from the CPU 12 is supplied and a booster circuit 163 are used instead of the test reference voltage generation circuit 152. It is in the point provided.
[0062]
Next, the operation of the semiconductor memory device thus configured will be described. In the self-diagnosis test, the CPU 12 outputs a frequency switching signal 161, and according to the content of the signal, the test frequency control circuit 162 determines an appropriate current capability margin test for the booster circuit 163 in addition to the frequency normally used. Generate test frequency. A rewrite voltage is generated by the booster circuit 163 using the test frequency, and the rewrite voltage is applied to each control circuit via the power supply line 154 to perform a current capability margin self-diagnosis test.
[0063]
By the above operation, normally, a plurality of test frequencies can be generated in addition to the frequency used for the boost operation, and the current capability margin test of the boost circuit can be realized by the self-diagnosis of the nonvolatile memory cell array.
[0064]
(Seventh embodiment)
FIG. 7 is a block diagram showing a configuration example of the semiconductor memory device according to the seventh embodiment of the present invention. In FIG. 7, reference numeral 100 denotes a semiconductor storage device having a CPU, a RAM, and the like mounted thereon, and reference numeral 2 denotes a nonvolatile memory including a user use area 4 and a memory area (mask ROM or flash memory) 150 for storing BIST test sequence data. The cell array 3, a memory peripheral circuit including a decoder, a sense amplifier, a control circuit, and the like for controlling reading and rewriting of the nonvolatile memory cell array 2, a BIST start terminal 8 for starting a BIST operation, a CPU 12 13 is a RAM, 113 is a BIST data transfer signal line from the memory area 150 for storing BIST test sequence data, 114 is a CPU control signal line for BIST data, 115 is a rewrite control signal line for the CPU 12, 171 is a CPU 12 Read judgment level by Rikae signal lines, inspection determination level control circuit 172, 173 is determined level control signal line, 174 is a sense amplifier having a plurality of test determination level.
[0065]
FIG. 8 is a diagram illustrating the relationship between the inspection determination level and the threshold voltage Vt distribution in the present embodiment.
[0066]
Next, the operation of the semiconductor memory device thus configured will be described. When a power supply, CLK or the like is applied to the semiconductor memory device 100 and a signal for activating the BIST operation is supplied to the BIST activation terminal 8, the BIST test sequence data is transmitted from the memory area 150 to the BIST data transfer signal. The data is transferred to the RAM 13 via the line 113. Next, the RAM 13 outputs the internal test sequence data to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test of the user use area 4 in the nonvolatile memory cell array 2 via the rewrite control signal line 115.
[0067]
In the self-diagnosis test, the CPU 12 outputs a signal via the read determination level switching signal line 171, and according to the content thereof, the test determination level control circuit 172 generates a threshold voltage Vt distribution after normal writing (FIG. 8). Vt margin self-test based on appropriate determination levels (test level LA and test level LB in FIG. 8) that can test the distribution A) in FIG. 8 and the threshold voltage Vt distribution (distribution B in FIG. 8) after erasing. Perform a diagnostic test.
[0068]
By the above operation, in addition to the judgment level (LR in FIG. 8) used for the normal read operation, the inspection judgment level (LA, LB in FIG. 8) for checking the Vt distribution after normal writing and normal erasing. ) Can be selected, and the Vt margin inspection of the read operation can be realized by the self-diagnosis of the nonvolatile memory cell array.
[0069]
(Eighth embodiment)
FIG. 9 is a block diagram showing a configuration example of the semiconductor memory device according to the eighth embodiment of the present invention. In FIG. 9, reference numeral 100 denotes a semiconductor memory device having a CPU, a RAM, etc. mounted thereon, reference numeral 2 denotes a nonvolatile memory cell array including a user use area 4 and a memory area 150 for storing BIST test sequence data, and reference numeral 3 denotes a nonvolatile memory cell array. A memory peripheral circuit including a decoder, a sense amplifier, a control circuit, and the like for controlling read / write of the memory cell array 2, a BIST start terminal 8 for starting a BIST operation, 12 a CPU, 13 a RAM, 113 a BIST BIST data transfer signal line from the memory area 150 that stores the test sequence data for BIST, 114 is a CPU control signal line for BIST data, 115 is a rewrite control signal line for the CPU 12, and 191 is a decision level switch for rewrite function check by the CPU 12. Signal line, 192 is written Recombinant functional check determination level control circuit, 193 is determined level control signal line, 194 is a sense amplifier having a plurality of rewrite function check determination level.
[0070]
FIG. 10 is a diagram showing the relationship between the write check determination level and the threshold voltage Vt distribution in the present embodiment.
[0071]
Next, the operation of the semiconductor memory device thus configured will be described. When a power supply, CLK or the like is applied to the semiconductor memory device 100 and a signal for activating the BIST operation is supplied to the BIST activation terminal 8, the BIST test sequence data is transmitted from the memory area 150 to the BIST data transfer signal. The data is transferred to the RAM 13 via the line 113. Next, the RAM 13 outputs the internal test sequence data to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test of the user use area 4 in the nonvolatile memory cell array 2 via the rewrite control signal line 115.
[0072]
In the self-diagnosis test, the CPU 12 outputs a signal to the judgment level switching signal line 191 for rewriting function check, and in accordance with the content thereof, the judgment level control circuit 192 for rewriting function check sets the threshold voltage after writing for function check. Appropriate judgment levels (write function check level LC and erase function check level LD in FIG. 10) that can inspect the Vt distribution (distribution C in FIG. 10) and the threshold voltage Vt distribution after erase (distribution D in FIG. 10). , A slight change in Vt is checked.
[0073]
With the above operation, a function test determination level (LC, LD in FIG. 10) capable of testing the rewrite function can be selected in addition to the determination level (LR in FIG. 10) used for the normal read operation. In the self-diagnosis described above, the rewriting function is inspected by using a small change in Vt, as compared with the case where the rewriting function is inspected by a normal change in Vt, so that the inspection time can be greatly reduced.
[0074]
(Ninth embodiment)
FIG. 11 is a block diagram showing a configuration example of the semiconductor memory device according to the ninth embodiment of the present invention. In FIG. 11, reference numeral 100 denotes a semiconductor storage device having a CPU, a RAM, and the like, 2 denotes a user use area 4, a rewritable nonvolatile memory 120 for storing BIST test sequence data, and a self-diagnosis test result. A nonvolatile memory cell array including a rewritable nonvolatile memory 210 to be stored; 3, a memory peripheral circuit including a decoder, a sense amplifier, and a control circuit for controlling reading / writing of the nonvolatile memory cell array 2; BIST activation terminal for activating a BIST operation, 12 is a CPU, 13 is a RAM, 113 is a BIST data transfer signal line from the nonvolatile memory 120, 114 is a CPU control signal line with BIST data, and 115 is rewriting by the CPU 12. Control signal line 211 is self-diagnosis by CPU 12 Test result write signal line, 212 self-diagnosis results readout signal line 213 is rank selection data calculating circuit according to the diagnostic results, 214 is a rank selection data output terminal.
[0075]
Next, the operation of the semiconductor memory device thus configured will be described. When a power supply, a CLK or the like is applied to the semiconductor memory device 100 and a signal for activating the BIST operation is supplied to the BIST activation terminal 8, the BIST test sequence data is transmitted from the rewritable nonvolatile memory 120. The data is transferred to the RAM 13 via the BIST data transfer signal line 113. Next, the RAM 13 outputs the internal test sequence data to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test of the user use area 4 in the nonvolatile memory cell array 2 via the rewrite control signal line 115.
[0076]
In the self-diagnosis test, the CPU 12 outputs a signal to the test result write signal line 211, and the signal is stored in the rewritable nonvolatile memory 210. After the inspection, the information stored in the rewritable nonvolatile memory 210 is read out via the self-diagnosis result readout signal line 212, and the rank selection data calculation circuit 213 calculates rank selection data according to the characteristics from the diagnosis result. Then, the data is output to the rank selection data output terminal 214.
[0077]
By the above operation, the semiconductor memory device can not only judge good / defective products by self-diagnosis, but also according to various electrical characteristics such as access speed and rewriting time by rank selection data output outside the semiconductor memory device. Sorting shipment becomes feasible.
[0078]
(Tenth embodiment)
FIG. 12 is a block diagram showing a configuration example of the semiconductor memory device according to the tenth embodiment of the present invention. In FIG. 12, reference numeral 100 denotes a semiconductor storage device having a CPU, a RAM, and the like mounted thereon, 2 denotes a user use area 4, a redundant area 5, a rewritable nonvolatile memory 120 for storing BIST test sequence data, The non-volatile memory cell array 3 includes a rewritable non-volatile memory 210 for storing a diagnostic test result and a rewritable non-volatile memory 220 for storing sorted shipping information. A memory peripheral circuit including a decoder, a sense amplifier, a control circuit, and the like for controlling, 8 a BIST activation terminal for activating a BIST operation, 12 a CPU, 13 a RAM, 113 a BIST data from the nonvolatile memory 120 A transfer signal line 114 is a CPU control signal line for BIST data, 5 is a rewrite control signal line by the CPU 12, 212 is a self-diagnosis result read signal line, 221 is a sorted shipment information read signal line, 213 is a rank selection data operation circuit based on the diagnosis result, 223 is a redundancy switching control signal line, and 224 is redundancy control. The circuit 214 is a rank selection data output terminal.
[0079]
Next, the operation of the semiconductor memory device thus configured will be described. When power and CLK are applied to the semiconductor memory device 100 and a signal for activating a BIST operation is supplied to the BIST activation terminal 8, the BIST test sequence data is transferred from the nonvolatile memory 120 to the BIST data transfer. The data is transferred to the RAM 13 via the signal line 113. Next, the RAM 13 outputs the internal test sequence data to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test of the user use area 4 in the nonvolatile memory cell array 2 via the rewrite control signal line 115.
[0080]
After the completion of the self-diagnosis test, the test result in the test result storage area 210 is read out, the rank selection data calculation circuit 213 calculates rank selection data according to the characteristic from the diagnosis result, and the result and the classification shipping information already written. Based on the sorted shipping information in the storage area 220, the redundancy control circuit 224 performs redundancy switching according to the characteristics.
[0081]
By the above operation, not only the sorting and shipping according to each electrical characteristic by the self-diagnosis becomes possible, but also the redundancy remedy can be performed by the defective product rank such as the access speed and the rewriting time, and the remedy rate can be improved. it can.
[0082]
(Eleventh embodiment)
FIG. 13 is a block diagram showing an example of a configuration for performing the semiconductor memory device inspection method according to the eleventh embodiment of the present invention. In FIG. 13, reference numeral 100 denotes a semiconductor memory device having a CPU, a RAM, and the like, 2 denotes a user use area 4, a rewritable nonvolatile memory 120 for storing BIST test sequence data, and power line disconnection information. A nonvolatile memory cell array composed of a rewritable nonvolatile memory 230 to be read, a memory peripheral circuit composed of a decoder, a sense amplifier, a control circuit, etc. for controlling reading / writing of the nonvolatile memory cell array 2; , 13 is a RAM, 24 is a semiconductor inspection device (LSI tester), 231 is a power line disconnection information write signal line from the LSI tester 24, 232 is a power line disconnection information read signal line, 233 is a power line disconnection switch circuit, 234 Is a power supply terminal.
[0083]
Next, the operation of the configuration for implementing such a semiconductor memory device inspection method will be described. A DC test result performed by the external LSI tester 24 on the above-described semiconductor memory device 100 is rewritable to store power line disconnection information in the nonvolatile memory cell array via a power line disconnection information write signal line 231. Write to the non-volatile memory 230. When the writing is completed, the power supply line disconnection information is taken into the power supply line disconnection switch circuit 233 via the read signal line 232, and the power supply line from the power supply terminal 234 is disconnected according to the information.
[0084]
According to the above operation, if the result of the DC test inspected by the LSI tester 24 is defective, the power supply line is cut off, so that a probe card or an LSI tester which requires a probe for all chips as shown in FIG. Therefore, self-diagnosis can be realized even in a wafer batch inspection in which a power supply line common to each chip is provided as shown in FIG.
[0085]
FIG. 14 is a schematic diagram showing an outline of a wafer inspection using a probe card (inspection jig) in the present embodiment. In FIG. 14, reference numeral 20 denotes a wafer, 21 denotes a chip to be inspected (DUT: device under test), 243 denotes an A chip, 244 denotes a B chip, 245 denotes a C chip, 245 denotes a D chip, and 240 denotes a center. A probe 241 (first probe) for electrically connecting to all pads of the chip to be probe-inspected, and a plurality of pads provided on the left and right of the probe 241 for several chips to be BIST-inspected A probe card including a probe 242 (second probe) for electrically connecting to the (BIST pad), and 24 is an LSI tester.
[0086]
FIG. 15 is a block diagram showing a configuration of a B chip for performing a probe test and an A chip for performing a BIST test in FIG. In FIG. 15, reference numerals 243 and 244 denote A chips and B chips, which are semiconductor memory devices equipped with a CPU, a RAM, and the like, respectively, and 2 denotes a user use area 4 and a rewritable nonvolatile memory for storing test sequence data for BIST. Memory cell array comprising a nonvolatile memory 120 and a rewritable nonvolatile memory 250 for storing various information, a decoder 3, a sense amplifier, a control circuit, etc. for controlling reading / writing of the nonvolatile memory cell array 2 8 is a BIST activation terminal for activating a BIST operation; 12 is a CPU; 13 is a RAM; 113 is a BIST data transfer signal line from the nonvolatile memory 120; and 114 is CPU control by BIST data Signal lines 115 are for rewriting control by the CPU 12. Line, 251 is a test signal line by the LSI tester 24.
[0087]
Next, wafer inspection of the semiconductor memory device thus configured will be described. First, a probe 241 for connecting to all pads of a chip to be inspected is connected to the B chip 244, and a probe 242 for connecting to several pads of several chips to be inspected is A. Connect to chip 243. While the LSI tester 24 performs the rewriting inspection of the BIST data storage area 120 including the various information areas 230 and the writing of the BIST data to the BIST data storage area 120 with respect to the B chip 244, the A chip For the H.243, a self-diagnosis of the user use area 4 is performed using the BIST data storage area 120, the RAM 13, and the CPU 12.
[0088]
FIG. 16 is a flowchart in the inspection method of the A chip to the D chip. In FIG. 16, "1'st probe" indicates a state in which the probe 241 is connected to the A chip 243, "2 'nd probe" indicates a state in which the probe 241 is connected to the B chip 244, and "3' rd probe". Represents that the probe 241 is connected to the C chip 245, that is, the probe card 240 is shifted rightward and connected. Therefore, the state of FIG. 15 is the state of the “2 ′ nd probe”.
[0089]
In FIG. 16, “P-Test” indicates a DC check by the LSI tester 24, a rewrite check of the BIST data storage area 120 including the various information areas 230, and a BIST data transfer to the BIST data storage area 120. This shows a state in which a write test is being performed. “BIST-1” to “BIST-4” indicate a state in which a self-diagnosis test of the user use area 4 is performed using the BIST data storage area 120 and the RAM 13 or the CPU 12. Since the time of the BIST inspection is much longer than that of “P-Test”, it is divided into “BIST-1” and “BIST-4”.
[0090]
As shown in FIG. 16, in the present inspection method, while the D chip 246 performs “P-Test”, the C chip 245 is “BIST-1”, the B chip 244 is “BIST-2”, and the A chip Inspection can proceed in a pipeline process with 243 as “BIST-3”. When BIST data is not written in the BIST data storage area 120, BIST inspection is not executed, and even when “BIST-4” is completed, BIST inspection is not executed based on the inspection result information.
[0091]
(Twelfth embodiment)
Next, a flow in which the BIST inspection is divided for each step will be described. FIG. 17 is a block diagram showing a configuration example of the semiconductor memory device according to the twelfth embodiment of the present invention. In FIG. 17, reference numeral 100 denotes a semiconductor storage device having a CPU, a RAM, and the like mounted thereon, reference numeral 2 denotes a user use area 4, a rewritable nonvolatile memory 120 for storing BIST test sequence data, and a rewrite for storing a test state. A nonvolatile memory cell array including a possible nonvolatile memory 260; a memory peripheral circuit including a decoder, a sense amplifier, and a control circuit for controlling reading / writing of the nonvolatile memory cell array 2; a BIST operation 8; BIST start terminal for starting, 12 is a CPU, 13 is a RAM, 113 is a BIST data transfer signal line from the nonvolatile memory 120, 114 is a CPU control signal line based on BIST data, and 115 is a rewrite control signal line by the CPU 12. , 261 are test state write signals from the CPU 12. Line, the check state output control circuit 263, 264 test condition output signal line, 262 is a test condition output terminal.
[0092]
Next, the operation of the semiconductor memory device thus configured will be described. When power and CLK are applied to the semiconductor memory device 100 and a signal for activating the BIST operation is supplied to the BIST activation terminal 8, the BIST test sequence data is transferred from the nonvolatile memory 120 to the BIST data. The data is transferred to the RAM 13 via the signal line 113. Next, the RAM 13 outputs the internal test sequence data to the CPU 12 via the CPU control signal line 114. Further, in accordance with the test sequence data, the CPU 12 performs a rewrite self-diagnosis test of the user use area 4 in the nonvolatile memory cell array 2 via the rewrite control signal line 115.
[0093]
In each step during the self-diagnosis test, the CPU 12 writes the test status information via the test status write signal line 261 to the rewritable nonvolatile memory 260 that stores the test status. At the same time, the CPU 12 outputs inspection state information to the inspection state output control circuit 263 and the inspection state output terminal 262 via the inspection state output signal line 264.
[0094]
FIG. 18 shows a flow of a wafer inspection using a semiconductor memory device having the above-described features. In FIG. 18, first, the state of the “2′nd probe” in which the B chip 244 performs “P-Test” will be described. Inspection (1) (DC inspection) is performed on the B chip 244 by the LSI tester 24, and if NG, processing (14) (writing of power line disconnection information); if OK, inspection (2) (including various information areas) (Inspection of BIST data storage area). If the inspection (2) is NG, the process (15) (writing of NG result information) is performed, and if the inspection is OK, the process proceeds to the step of the process (3) (inspection status check of another DUT).
[0095]
In the meantime, for the A chip 243, the processing (4) (transfer the stored data for BIST to the RAM), the processing (5) (the CPU control BIST is executed by starting the RAM), and the processing (6) (read the inspection state storage area). , BIST start step is determined), then inspection (7) (BIST-1 inspection of user use area: various functions), processing (11) (various inspection results including margin test are stored in the inspection result storage area). Write), and proceeds to the BIST inspection step of processing (8) (writing the current inspection step state in the inspection state storage area and outputting the state to the output terminal). The LSI tester 24 stops each test in response to the result of the process (3) or the process (8), and the probe is separated from the pad.
[0096]
Next, the state shifts to the state of “3 ′ rd probe” for performing “P-Test” on the C chip 245. In the “3′rd probe” state, inspection (1), inspection (2), and processing (3) are performed on the C chip 245, and processing (4) and processing (3) are performed on the B chip 245 at the same time. 5), processing (6), inspection (7), processing (11), and processing (8) are performed. At the same time, processing (4), processing (5), processing (6), Inspection (9) (BIST-2 inspection of user use area: various margin tests), processing (11), and processing (8) are performed. The LSI tester 24 stops each inspection in response to the result of the process (3) or the process (8), disconnects the probe from the pad, and shifts to the “4′th probe” state.
[0097]
In the “4′th probe” state, processing (4), processing (5), processing (6), inspection (7), processing (11), and processing (8) are performed on the C chip 245. The processing (4), the processing (5), the processing (6), the inspection (9), the processing (11), and the processing (8) are performed on the B chip 245, and at the same time, on the A chip 244, Processing (4), Processing (5), Processing (6), Inspection (10) (BIST-3 inspection of user use area: various margin tests), Processing (11), Processing (12) (Storing sorted shipping information as information) (Write to area), process (13) (write redundant information from results of process (11) and process (12)), and process (8). The LSI tester 24 stops each test in response to the result of the process (3) or the process (8), disconnects the probe from the pad, and shifts to the next state.
[0098]
By performing the wafer inspection by the above operation, while the LSI tester 24 performs the DC inspection of the chip to be subjected to the probe inspection and the memory inspection of the BIST data storage area, the LSI tester 24 applies the BIST to the adjacent chip. Using the information in the data storage area, the RAM, and the CPU, it is possible to perform a BIST inspection of the nonvolatile memory cell array in a pipeline process, thereby significantly reducing the inspection time.
[0099]
3
【The invention's effect】
As described above, according to the present invention, by providing a semiconductor memory device with a function of operating a CPU and performing self-diagnosis of a nonvolatile memory cell array, it is possible to realize a BIST with a small increase in area, and to realize a semiconductor memory device. By providing various margin inspection circuits therein, a margin inspection can be performed at the time of self-diagnosis.
[0100]
Further, by providing an area for storing various types of information in the semiconductor memory device, it becomes possible to respond to sorting shipment 31 by a self-diagnosis test.
[0101]
Further, in the wafer inspection, a probe for connecting to all pads of the chip to be probe-inspected, and a probe for connecting to several pads for several chips to be BIST-inspected on the left and right thereof. By using the probe card, while the LSI tester is performing the probe test, the adjacent chip can perform the BIST test in a pipeline process, thereby significantly reducing the test time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a block diagram showing a configuration example of a semiconductor memory device according to a second embodiment of the present invention;
FIG. 3 is a block diagram illustrating a configuration example of a semiconductor memory device according to a third embodiment;
FIG. 4 is a block diagram showing a configuration example of a semiconductor memory device according to a fourth embodiment;
FIG. 5 is a block diagram showing a configuration example of a semiconductor memory device according to a fifth embodiment;
FIG. 6 is a block diagram showing a configuration example of a semiconductor memory device according to a sixth embodiment;
FIG. 7 is a block diagram showing a configuration example of a semiconductor memory device according to a seventh embodiment;
FIG. 8 is a diagram showing a relationship between an inspection determination level and a threshold voltage Vt distribution in a semiconductor memory device according to a seventh embodiment of the present invention;
FIG. 9 is a block diagram illustrating a configuration example of a semiconductor memory device according to an eighth embodiment;
FIG. 10 is a diagram showing the relationship between a write check determination level and a threshold voltage Vt distribution in a semiconductor memory device according to an eighth embodiment of the present invention;
FIG. 11 is a block diagram showing a configuration example of a semiconductor memory device according to a ninth embodiment of the present invention;
FIG. 12 is a block diagram showing a configuration example of a semiconductor memory device according to a tenth embodiment of the present invention;
FIG. 13 is a block diagram showing a configuration example for implementing a semiconductor memory device inspection method according to an eleventh embodiment of the present invention;
FIG. 14 is a schematic view showing an outline of a probe card and wafer inspection according to an eleventh embodiment of the present invention.
FIG. 15 is a block diagram showing a configuration of a B chip for performing a probe test and an A chip for performing a BIST test of FIG. 14;
FIG. 16 is a flowchart in the inspection method of the A chip to the D chip in FIG. 14;
FIG. 17 is a block diagram showing a configuration example of a semiconductor memory device according to a twelfth embodiment of the present invention;
FIG. 18 is a view showing an outline of inspection at each step of wafer inspection in a semiconductor memory device according to a twelfth embodiment of the present invention;
FIG. 19 is a block diagram showing a configuration of a conventional semiconductor memory device having a built-in BIST circuit.
FIG. 20 is a block diagram showing a configuration of a semiconductor memory device incorporating a further conventional BIST circuit.
FIG. 21 is a schematic diagram of a configuration for implementing a conventional wafer inspection method for a semiconductor memory device having a built-in BIST circuit.
FIG. 22 is a schematic diagram of a configuration for implementing a wafer inspection method for a semiconductor memory device further incorporating a conventional BIST circuit.
[Explanation of symbols]
1, 10, 100 semiconductor memory device
2 Non-volatile memory cell array
3 Memory peripheral circuit
4 User use area
5 Redundant area
6. BIST circuit (mode, address, data generation circuit, output comparison circuit)
7 BIST result storage memory
8 BIST activation terminal
11 BIST circuit with mask ROM
12 CPU
13 RAM
20 wafers
21 Chip to be inspected (DUT)
24 LSI tester
110 Mask ROM for storing test sequence data for BIST
113 BIST data transfer signal line
114 CPU control signal line
115 Rewrite control signal line
120 Rewritable nonvolatile memory for storing test sequence data for BIST
130 Mask ROM for storing BIST test sequence data in bank 0
131 Mask ROM for storing BIST test sequence data in bank 1
132 Bank 0 side memory block
133 Bank 1 side memory block
140 Rewritable Non-Volatile Memory for Storing BIST Test Sequence Data in Bank 0
141 Rewritable nonvolatile memory for storing test sequence data for bank 1 side BIST
142 Bank 0 side memory block
143 Bank 1 side memory block
151 Reference voltage switching signal line
152 Inspection reference voltage generation circuit
153 Read / rewrite voltage generation circuit
154 Read / rewrite power supply line
161 Frequency switching signal line
162 Inspection frequency control circuit
163 booster circuit
171 Read determination level switching signal line
172 Inspection decision level control circuit
173 Judgment level control signal line
174 Sense amplifier having a plurality of test decision levels
191 Rewriting function check judgment level switching signal line
192 Judgment level control circuit for rewriting function check
193 judgment level control signal line
194 Sense amplifier having a plurality of determination levels for rewriting function check
210 Rewritable nonvolatile memory for storing self-diagnosis test results
211 Self-diagnosis test result write signal line
212 Self-diagnosis result read signal line
213 Rank selection data operation circuit based on diagnosis result
214 rank selection data output terminal
220 Rewritable nonvolatile memory for storing sorting shipment information
221 Sorted shipment information read signal line
223 Redundancy switching control signal line
224 Redundancy control circuit
230 Rewritable nonvolatile memory for storing power line disconnection information
231 Power supply line disconnection information write signal line from LSI tester
232 Power line disconnection information read signal line
233 Power line disconnect switch circuit
234 Power supply terminal
240 Plow Card
241 Probe for connecting to all pads of the chip to be probed at the center
242 Probe for connecting to several pads of several chips to be BIST inspected on the left and right of probe 241
243 A chip
244 B chip
245 C chip
246 D chip
251 Test signal line by LSI tester
252 Various information writing signal lines
260 Rewritable nonvolatile memory for storing inspection status
261 Inspection status write signal line
262 inspection status output terminal
263 Inspection status output control circuit
264 Inspection status output signal line

Claims (13)

A semiconductor memory device having a self-diagnosis function,
A nonvolatile memory cell array having a user use area and a mask ROM cell storing instruction data for self-diagnosis;
A RAM to which the self-diagnosis instruction data is transferred from the mask ROM cell in response to an external self-diagnosis start signal;
A semiconductor memory device comprising: a CPU for performing a self-diagnosis of the user use area of the nonvolatile memory cell array based on the self-diagnosis instruction data transferred from the RAM, on a same chip. A semiconductor memory device having a self-diagnosis function,
A nonvolatile memory cell array having a user use area and a rewritable nonvolatile memory cell storing instruction data for self-diagnosis;
A RAM in which the self-diagnosis instruction data is transferred from the rewritable nonvolatile memory cell in response to an external self-diagnosis activation signal;
A semiconductor memory device comprising: a CPU for performing a self-diagnosis of the user use area of the nonvolatile memory cell array based on the self-diagnosis instruction data transferred from the RAM, on a same chip. A semiconductor memory device having a self-diagnosis function for a plurality of built-in nonvolatile memory cell arrays,
Each of the plurality of nonvolatile memory cell arrays has a user use area and a rewritable nonvolatile memory cell,
A specific nonvolatile memory cell array having a rewritable nonvolatile memory cell in which self-diagnosis instruction data is stored;
In response to an external self-diagnosis start signal, the user of another non-volatile memory cell array based on the self-diagnosis command data transferred from the rewritable non-volatile memory cell of the specific non-volatile memory cell array. A semiconductor memory device comprising a CPU for self-diagnosing a use area on the same chip. The semiconductor storage device includes:
Means for generating a plurality of test reference voltages based on a control signal from the CPU;
The semiconductor memory device as described in any one of claims 1 to 3, further comprising a means for inspecting the nonvolatile memory cell array with a voltage generated from the test reference voltage. The semiconductor storage device includes:
Means for generating a plurality of test frequencies based on a control signal from the CPU;
The semiconductor memory device as described in any one of claims 1 to 3, further comprising a means for inspecting the nonvolatile memory cell array boosting power generated from the inspection frequency. The semiconductor storage device includes:
Means for selecting a plurality of inspection determination levels for inspecting a threshold voltage distribution of the nonvolatile memory cell array after regular writing and erasing based on a control signal from the CPU;
Selected on the basis of the inspection determination level, the semiconductor memory device according to one of claims 1 to 3, further comprising a means for inspecting the nonvolatile memory cell array. The semiconductor storage device includes:
Means for selecting, based on a control signal from the CPU, a plurality of function test determination levels for testing a rewriting function of the nonvolatile memory cell array by a small change in a threshold voltage of the nonvolatile memory cell array;
Selected on the basis of the inspection determination level, the semiconductor memory device according to one of claims 1 to 3, further comprising a means for inspecting the nonvolatile memory cell array. The semiconductor storage device includes:
Means for writing a result of the self-diagnosis performed by the CPU to an information storage area in the nonvolatile memory cell array;
Based on the results of self-diagnosis read from the information storage area, any one claim of claims 1 to 3, characterized in that a means for outputting a rank selection data corresponding to the characteristic calculation and externally Semiconductor storage device. The semiconductor storage device includes:
Means for writing a result of the self-diagnosis performed by the CPU to a first information storage area in the nonvolatile memory cell array;
Means for calculating and outputting rank selection data according to characteristics based on the self-diagnosis result read from the first information storage area,
Means for controlling redundancy switching of the nonvolatile memory cell array based on the rank selection data and the sorted shipping information stored in advance in a second information storage area in the nonvolatile memory cell array. the semiconductor memory device of any one of claims 1, wherein 3. The semiconductor storage device includes:
Means for writing power-off information based on an inspection result performed by an external inspection device to an information storage area in the nonvolatile memory cell array;
The semiconductor memory device as described in any one of claims 1 to 3, characterized in that a switch circuit for disconnecting the power line based on the power-off information read from the information storage area. The semiconductor memory device of any one of claims 1 3 is a test fixture for testing a plurality onboard wafer,
A first probe provided at the center and electrically connected to all pads of the semiconductor memory device to be probe-tested;
A plurality of second probes provided on the left and right sides of the first probe for electrically connecting to a self-diagnosis pad of the semiconductor memory device to be subjected to a self-diagnosis test; Inspection jig for storage device. An inspection method using the inspection jig according to claim 11 ,
While performing a probe test on the semiconductor memory device to which the first probe of the inspection jig connected to the semiconductor inspection device is connected, a self test is performed on the semiconductor memory device to which the second probe is connected. A method for testing a semiconductor memory device, comprising performing a diagnostic test. The semiconductor storage device includes:
Means for writing the test progress of the self-diagnosis performed by the CPU to an information storage area in the nonvolatile memory cell array;
Means for reading out the inspection progress from the information storage area and outputting it to the outside,
Based on the output test elapsed, the semiconductor memory device of any one of claims 1 to 3, further comprising a means for determining a first inspection carried out during inspection resumed.

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