JPH07210456A - Memory controller - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a high-speed access mode of DRAM. CONSTITUTION:First and second registers 12 and 13 hold line addresses at the times of accessing this and last times and a comparator 14 compares the contents of these so as to detect the change of a line address. Then, when a mode does not become a high-speed access mode though the line address does not change, a control circuit 17 increases the ON-time of a line address strobe signal 8. On the other hand, when the mode is the high-speed access mode though the line address changes, the ON-time of the line address strobe signal 8 is reduced. As the result, when the memory access of an application program is repeated with regard to the same line address, the high-speed access mode is kept long time and when the line addres changes frequently, the high- speed access mode is finished in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a D equipped with a high speed access mode such as a page mode or a static column mode.
The present invention relates to a memory control device using a RAM.

[0002]

2. Description of the Related Art Generally, in a DRAM, in order to save the number of input pins, a row address is input and a column address is input twice to perform one access. In this case, when the row address is input, the row address strobe signal is turned on, and when the column address is input, the column address strobe signal is turned on, whereby the two addresses are distinguished. When the row address is the same and only the column address is different, the access is performed by inputting only the column address. This is called a high speed access mode. In this case, the row address strobe signal is kept on for a certain period of time, during which the column address strobe signal is turned on, and the operation of inputting the column address is performed a plurality of times. This is called page mode. Then, after the row address strobe signal is turned off, the row address strobe signal is input again and then the column address strobe signal is input.

[0003]

However, the above-described conventional technique has the following problems because the time during which the row address strobe signal is turned on is fixed. That is, the method of accessing the memory largely depends on the application program executed by the host device, and when there are many accesses within the same row address, the on time of the row address strobe signal is set as long as possible. There are more access in high-speed access mode,
The memory access speed can be improved. However, since the row address strobe signal is turned off after a certain period of time, it is impossible to improve the memory access speed more than a certain level. On the other hand, in an application program in which the row address changes frequently, if the row address strobe signal is turned on for a long time, the row address strobe signal must be turned off once when a different row address is given. . Then, after that, the row address strobe signal must be turned on again to start the memory access. Therefore, in such a case, the memory access speed is rather reduced.

[0004]

In order to solve the above-mentioned problems, a memory control device of the present invention is characterized by the following in a memory control device for accessing by a row address and a column address. A first register for holding the row address currently being accessed is provided. A second register for holding the row address accessed last time is provided. A comparator is provided for comparing the contents of the first and second registers. The following control circuit is provided. That is, as a result of the comparison by the comparator, if the currently accessed row address matches the previously accessed row address and the current access mode is not the high speed access mode, the row address strobe signal time is increased. On the other hand, when the currently accessed row address does not match the previously accessed row address and the current access mode is the high speed access mode, the row address strobe signal time is reduced.

[0005]

In the memory control device of the present invention, the row address at the time of the current access and the previous access is held in the first and second registers, and the change of the row address is detected by the comparison by the comparator. Then, the control circuit increases the on-time of the row address strobe signal when the high-speed access mode is not set although there is no change in the row address. On the other hand, if the high-speed access mode is set although the row address has changed, the on-time of the row address strobe signal is reduced. As a result, when the memory access of the application program is repeatedly performed for the same row address, the high-speed access mode is set for a long time, and when the row address changes frequently,
The fast access mode is set to end in a short time.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the memory control device of the present invention. The memory control device shown in FIG.
It is composed of a DRAM control unit 1 and a weight control unit 11,
The weight control unit 11 includes a first register 12, a second register 13, a comparator 14, and a control circuit 17.

First, the DRAM control unit 1 will be described with reference to FIG. The DRAM control unit 1 inputs an address signal (HA) 3 and a request signal (REQ) 4 from the host bus 2 and sends an acknowledge signal (AC) to the host bus 2.
K) 5 is output. To the host bus 2, a host device such as an arithmetic device (not shown) is connected. Here, the request signal 4 indicates that access from the host bus 2 to the address indicated by the address signal 3 has started,
The acknowledge signal 5 indicates that the memory access in the DRAM memory unit 6 is completed.

The DRAM control unit 1 also outputs a memory address (MA) 7, a row address strobe signal (RAS) 8 and a column address strobe signal (CAS) 9 to the DRAM memory unit 6. Here, the memory address 7 is an address for the DRAM memory unit 6,
When the row address strobe signal 8 is on, it indicates that the memory address 7 is a row address. On the other hand, when the column address strobe signal 9 is on, it indicates that the memory address 7 is a column address. Data (MD) 10 on the host bus 2 is input / output to / from the DRAM memory unit 6. Further, the DRAM control unit 1 inputs the wait signal (Wait_N) 16 from the weight control unit 11.

The wait control unit 11 inputs the address signal 3 and the request signal 4 from the host bus 2, the row address strobe signal 8 from the DRAM control unit 1, and the DRA.
The wait signal 16 is output to the M control unit 1. The wait signal 16 is a signal for notifying the DRAM controller 1 of the time value for which the wait controller 11 turns on the row address strobe signal 8. Weight control unit 11
As described above, includes the first register 12, the second register 13, the comparator 14, and the control circuit 17.

The first register 12 is composed of a semiconductor element which can be accessed at high speed, and latches a bit corresponding to a row address in the address signal 3 when the request signal 4 is turned on. The second register 13 is the first register 1
Similar to 2, consists of semiconductor elements that can be accessed at high speed,
The contents held in the first register 12 are held when the row address strobe signal 8 is turned on. The comparator 14 compares the contents of the first register 12 and the contents of the second register 13, and if the contents match, the hit signal (H
It) 15 is turned on, and if they do not match, the hit signal 15 is turned off. Therefore, immediately after a memory access request is issued from the host bus 2 by the request signal 4, whether the current row address is the same as or different from the row address which last accessed the row address strobe signal 8 and accessed the DRAM memory unit 6. It is indicated by the hit signal 15.

The control circuit 17 inputs the request signal 4 and the row address strobe signal 8 and outputs a wait signal 16. Both when the row address strobe signal 8 is already turned off when the hit signal 15 is input to the control circuit 17 and when the row address strobe signal 8 is still on and the high speed access mode is continued. In some cases. The control circuit 17 determines the wait signal 16 according to the states of the hit signal 15 and the row address strobe signal 8 at the input timing of the request signal 4. That is, the hit signal 15 causes the currently accessed row address to match the previously accessed address, and
When it is determined by the row address strobe signal 8 that the current access mode is not the high speed access mode, the length of the wait signal 16 is determined so as to increase the ON time of the row address strobe signal. On the other hand, hit signal 1
If the currently accessed row address does not match the previously accessed address according to 5, and it is determined by the row address strobe signal 8 that the current access mode is the high-speed access mode, the row address strobe signal ON time The length of the weight signal 16 is determined so that The contents of this control are shown in the flowchart of FIG. 2 described later.

Next, the operation of the above-mentioned device will be described. In FIG. 1, when the DRAM control unit 1 inputs the address signal 3 from the host bus 2, the DRAM control unit 1 accesses the DRAM memory unit 6 to generate a row address and a column address from the address signal 3, and the DRAM address is used as the memory address 7. Output to 6. Here, when memory addresses having the same row address but different column addresses are continuously accessed, both the row address and the column address are given in the first memory access, and only the column address is given in the subsequent memory access. At this time, the row address strobe signal 8 is turned on for a time corresponding to the length of the wait signal 16, and the column address strobe signal 9 is turned on from off every time the column address changes. Here, the time when the row address strobe signal 8 is turned on is controlled by the wait signal 16 of the wait controller 11.

FIG. 2 is a flow chart for explaining the operation of the weight controller 11. First, the weight controller 11
Waits for the request signal (REQ) 4 to be turned on (step S20). When the request signal 4 is turned on, next, the state of the row address strobe (RAS) signal 8 is checked (step S21). When it is determined that the row address strobe signal 8 is off, it can be determined that the access from the host bus 2 to the DRAM memory unit 6 is newly started. At this time, the state of the hit signal 15 is checked (step S24).

Here, when the hit signal 15 is on,
Indicates that the row address in the previous memory address and the row address in this memory address match. Therefore, in the case of such an application program, the row address strobe signal 8 is not turned off even in such a case by giving a time value larger than the time value given by the current wait signal 16. That is, there are more opportunities to use the high-speed access mode, and therefore the memory access access time can be shortened. Therefore, the control circuit 17 operates to lengthen the wait signal 16 (step S25). Specifically, the wait signal 16 is operated as follows. The unit of time here is the number of clocks. The current value given by the wait signal 16 is W0.

(Operation for Delaying Address Strobe Time) A predetermined clock number L of 1 clock or more is added to the current time value W0. However, as a result, when W0 becomes larger than the maximum value LL defined by the memory element, W0
Is the maximum value LL. That is, since there is a limit to the accessible time in the high speed mode due to the performance of the memory device, the maximum value LL is set accordingly. On the other hand, if the hit signal 15 is off in step S24 of FIG. 2, it can be determined that the value W0 of the wait signal 16 is an appropriate value.
W0 is not changed.

In step S21 of FIG. 2, when the row address strobe signal 8 is ON, it means that the high speed access mode is continued. In this case, the hit signal 15 is checked next (step S22), and when the hit signal 15 is on, nothing is done. That is, while the row address strobe signal 8 is on, there is an access by the next memory address having the same row address, so the wait signal 1
Since the value W0 of 6 can be determined to be appropriate, nothing is done.

On the other hand, when the hit signal 15 is off,
While the row address strobe signal 8 is on,
It can be determined that the value W0 of the wait signal 16 should be reduced because the memory address having a different row address is accessed. Specifically, the value W0 of the weight signal 16 is reduced as follows. (Operation for shortening the row address strobe time) Decrease a predetermined clock number S of 1 clock or more from the current time value W0. However, as a result, when it becomes smaller than the minimum value SS described below, W0 is set to the minimum value SS. This minimum value SS is the number of clocks by one access of the DRAM, that is, the total number of clocks when the row address is given once and the column address is given only once to perform the access. After performing the processing described above, the process returns to step S20 described above to prepare for the next memory access request from the host bus 2.

Next, a specific example of the above operation will be described with reference to the time charts of FIGS. Here, the read processing is taken as an example, and the increase and decrease values L and S of the wait signal 16 are both 1 clock. FIG. 3 shows an example in which the DRAM memory is read from the host bus 2 by the addresses A0 and A1 having the same row address in the high-speed access mode. At time t1, the request signal 4 is turned on from the host bus 2 (FIG. 3 (b)), and at the same time, the address A0 is received by the DRAM controller 1 and the wait controller 11. As a result, the DRAM control unit 1 and the weight control unit 11 are activated. That is, the DRAM control unit 1 turns on the row address strobe signal 8 to the DRAM memory unit 6 at time t2 (FIG. 4A) and sends the row address R0 as the memory address 7 (FIG. 3).
(E)). Next, at time t3, the column address strobe signal 9 is temporarily turned from OFF to ON (see FIG.
(B)), and the column address C0 is sent (FIG. 4 (e)).

In the wait controller 11, first, the row address R0 is held in the first register 12 by the request signal 4 at time t1. Here, in this memory reference,
It is assumed that the row address sent together with the previous row address strobe signal 8 and the current row address R0 do not match. Therefore, the hit signal 15 from the comparator 14
Remains off (time point t2 in FIG. 4C). Up to this point, the processes of steps S20, S21, and S24 of FIG. 2 are performed (FIG. 4 (e)). Next, at time t2, the contents of the first register 12 are transferred to the second register 13 by the row address strobe signal 8. As a result, since the contents of the first register 12 and the second register 13 are the same, the hit signal is always turned on at time t2 (FIG. 4 (c)), but this has an influence on the subsequent processing. Does not reach. Then, at time t4, the acknowledge signal 5
At the same time, the read data D0 is sent to the host bus 2 by the data 10 (FIG. 3 (c)).

Next, the memory reference is activated at the address A1 by the request signal 4 at time t5 (FIG. 3 (a)). At this time, the row address R0 of the address A1 is latched in the first register 12, and this is compared by the comparator 14 with the second register 13 latching the row address R0 of the previous address. Here, in the illustrated example, since the comparison results match and the hit signal 15 is turned on, the DRA
Only the column address C1 is given to the M memory unit 6 at time t7 (FIG. 3 (e)), and the value W0 of the wait signal 16 is not updated (FIG. 4 (d)). Up to this point, the address A1
2 corresponds to the processing of steps S20, S21, and S22 of FIG. 2 (FIG. 4 (e)). Then, the DRAM control unit 1 turns off the row address strobe signal 8 at time t9 when W0 clocks have passed from time t2, and terminates the high-speed access mode (FIG. 4A).

Next, an example of changing the value of the wait signal 16 will be described with reference to FIGS. 5 to 8 as well, the case of reading is taken as an example. 5 and 6 show
The case where the row address R2 that matches the row address R2 being held is given to the second register 13 when not in the high-speed access mode is shown. When the address A2 is given at the time t10 (FIG. 5A), the fact that the row address R2 of the address A2 matches the second register 13 at the time t11 means that the hit signal 15 is on. Shown (FIG. 6 (c)). Up to here is step S2 in FIG.
0, S21, and S24 (FIG. 6 (e)). As a result of step S24, since the hit signal 15 is on, the control circuit 17 performs a process of increasing the wait signal 16 (step S25 of FIG. 2). That is, the value W obtained by adding "1" to W0
The wait signal 16 whose new value is 0 + 1 is set to the DRAM
Input to the control unit 1 (FIG. 6 (d)). On the other hand, the DRAM control unit 1 turns on the row address strobe signal 8 at time t12 (FIG. 6A), and the column address C2 at time t13.
Is given (FIG. 6 (b)). Then, at time t14, the data D2 is read (FIG. 5 (d)).

Next, the same row address R2 as the address A2
It is assumed that a read request to the address A3 having is given at time t15 when the row address strobe signal 8 is on (FIG. 5A). At this time, the DRAM controller 1 gives only the column address C3 at time t16 (FIG. 5 (e)),
The data D3 is read at time t17 (FIG. 5 (d)). After that, the memory reference request is similarly processed from the host bus. Then, at the time t18 when the waiting time W0 + 1 has elapsed from the time t11, the row address strobe signal 8 is turned off (FIG. 6A), and the high speed access mode is ended. Then, in the next memory reference, W0 is set as the wait signal 16.
A value of +1 is used. As a result, when the memory access of the application program is repeatedly performed for the same row address, the high speed access mode is set for a long time.

FIG. 5 shows a case where the second register 13 is provided with an address A4 which does not match the row address being held in the high speed access mode. When address A4 is given at time t19 (FIG. 7A), time t20
In FIG. 8, the row signal R4 of the address A4 does not match the content of the second register 13 as indicated by the hit signal being turned off (FIG. 8 (c)). Up to this point corresponds to steps S20, S21, and S22 of FIG. 2 (FIG. 8 (e)). Here, the control circuit 17 performs a process of reducing the wait time 16 (step S23 in FIG. 2). That is, the value W0-1 obtained by subtracting "1" from W0 is set as a new value to be the wait time of the DRAM control unit 1 (FIG. 8 (d)). The DRAM control unit 1 temporarily turns off the row address strobe signal 8 at time t21 (FIG. 8A),
At time t22, the row address strobe signal 8 is turned on again (the same figure), a new row address R4 is given to the DRAM memory section 6 (FIG. 7 (e)), and the column address C4 is given at the time t23.
Is given (the same figure). Then, after that, the memory reference request from the host bus 2 is processed in the same manner. Then, at the time t25 when the waiting time W0-1 has elapsed from the time t22, the row address strobe signal 8 is turned off (FIG. 8A), and the high speed access mode is ended. Then, in the next memory reference, the value of W0-1 is used as the waiting time. As a result, when the row address is frequently changed due to the memory access of the application program, the high speed access mode is completed in a short time.

As described above, according to the above-described embodiment, when the application program executed by the host device makes many accesses within the same row address, the ON time of the row address strobe signal 8 is set. Is increased by a predetermined number of clocks, so that it is possible to increase the number of accesses in the high speed access mode. As a result, FIG. 9 (a)
As shown in FIG. 9, the ON time of the row address strobe signal 8 is constant, so that the high-speed access mode can be accessed only three times within the same row address. As shown, there are no such restrictions. Therefore, as long as the accesses within the same row address are maximally continuous, the row address need only be output once at the beginning, and it is not necessary to output the row address, so that the memory access speed can be improved. On the other hand, when the row address accessed by the application program changes frequently, the ON time of the row address strobe signal 8 is shortened, and the high speed access mode can be completed in a short time. As a result, as shown in FIG.
Conventionally, since the on time of the row address strobe signal 8 is constant, it is necessary to turn off the row address strobe signal 8 once when the row address is switched on the way, whereas the row address strobe signal 8 is shown in FIG. As such, it eliminates the need. Therefore, even in such a case, the procedure of turning off the row address strobe signal 8 is not required, and the memory access speed can be improved.

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made. For example, the present invention is not limited to the DRAM of an ordinary computer equipped with a display, a keyboard and the like, but can be widely applied to the DRAM of various information processing devices such as a control computer. Although the page mode has been described as an example of the high-speed access mode, the same applies to the static column mode. This is similar to the page mode except that the column address strobe signal is not used.

[0026]

As described above, according to the memory control device of the present invention, the row address strobe signal time is changed according to the change of the row address, so that the following effects can be obtained. That is, when the application program executed by the host device makes many accesses within the same row address, the row address strobe signal time is lengthened,
It is possible to increase access in the fast access mode. Therefore, the memory access speed can be improved. On the other hand, when the row address accessed by the application program changes frequently, the row address strobe signal time can be shortened to end the high speed access mode in a short time. Therefore, even in such a case, the memory access speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a memory control device of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of a weight control unit in FIG.

FIG. 3 is a time chart (No. 1) for explaining the operation of the apparatus of FIG.

FIG. 4 is a time chart (No. 2) for explaining the operation of the apparatus of FIG.

5 is a time chart (No. 3) explaining the operation of the apparatus of FIG. 1. FIG.

FIG. 6 is a time chart (No. 4) for explaining the operation of the apparatus in FIG.

FIG. 7 is a time chart (No. 5) for explaining the operation of the apparatus of FIG.

FIG. 8 is a time chart (No. 6) for explaining the operation of the apparatus in FIG.

FIG. 9 is a comparison diagram of the access capacities of the conventional device and the device of the present invention.

[Explanation of symbols]

 1 DRAM Control Unit 11 Weight Control Unit 12 First Register 13 Second Register 14 Comparator 17 Control Circuit

Claims (1)

[Claims] 1. A memory control device for memory access using a row address and a column address, comprising: a first register for holding a row address currently being accessed; and a second register for holding a row address previously accessed. The comparator for comparing the contents of the first and second registers, and the result of the comparison by the comparator, the currently accessed row address and the previously accessed row address match, and
If the current access mode is not the high-speed access mode, the row address strobe time is increased, but the currently accessed row address does not match the previously accessed row address, and the current access mode is the high-speed access mode. And a control circuit for reducing the row address strobe time.