JPH04262435A - Memory control system - Google Patents

Abstract

PURPOSE:To offer a memory control system for a computer system having a plurality of memory devices having different access speeds, wherein memory processing speeds can be maintained in accordance with individual access speeds, and wherein the processing speed of the computer system can be improved. CONSTITUTION:In a computer system 1 having a plurality of memory devices 13 and 14 that can be accessed by specifying a memory device using a device specifying signal outputted from a computer 11, a clock frequency of the reference clock CLK of a relevant system is variably set corresponding to a device specifying signal outputted from CPU 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method for a computer system having a plurality of memory devices.

0002

2. Description of the Related Art Generally, when designing a computer system, in order to improve processing speed, the frequency of a system clock (reference clock) is optimally selected depending on the access speed of a memory device.

FIG. 5 is a conventional timing diagram when accessing a memory device when the clock frequency is optimal.

In FIG. 5, time td is the minimum time required for the CPU to read data on the data bus, and time tac1 is the time required for reading data from the memory after the CPU specifies the memory address. is the access time until data is established on the data bus.
The time td1 is the time from when the data in the memory is established until when the CPU fetches the data.

In the case shown in FIG. 5, since time td1 is equal to time td, there is no wasted time in processing and the processing speed is high.

[0006]

However, computer systems often include a plurality of memory devices with different access speeds.

FIG. 6 is a timing diagram when accessing a memory device having a slow access speed in the related art. That is, the access time tac2 shown in FIG. 6 is longer than the access time tac1 shown in FIG. 5.

In FIG. 6, two wait cycles are inserted to delay the fetch by the CPU to wait for the data to be read from memory and established.

In the case shown in FIG. 6, the time from when the data read from the memory device is established to when the CPU fetches that data is (tm1+td), so the time tm1 is wasted time. There is.

FIG. 7 is a timing diagram when accessing a memory device with a high access speed in the related art. That is, the access time tac3 shown in FIG. 7 is shorter than the access time tac1 shown in FIG. 5.

In the case shown in FIG. 7, the time from when the data read from the memory device is established until the CPU fetches that data is (tm2+td), so the time tm2 is wasted time. There is.

In this way, in conventional computer systems, the frequency of the system clock is constant, so when multiple memory devices with different access speeds are installed, the clock frequency is adjusted to match the memory device with the slower access speed. This results in wasted time when accessing a memory device with a fast access speed.

[0013] Furthermore, even if the timing is adjusted by inserting a wait cycle when accessing a memory device with a slow access speed, wasted time will occur in many cases, and in either case, the processing speed of the system will decrease. It was the cause.

[0014] In view of the above-mentioned problems, the present invention provides a method for improving the processing speed of a system by maintaining a processing speed corresponding to each access speed when a plurality of memory devices having different access speeds are used. The purpose is to provide a memory control method that can

[0015]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the system according to the present invention provides a computer comprising a plurality of memory devices that are designated and accessible by a device designation signal output from a CPU. In the system, a clock frequency of a reference clock of the system is variably set in response to a device designation signal output from the CPU.

[0016]

[Operation] When the CPU accesses a memory device, it outputs a device designation signal, such as an address, to designate that memory device. Can be switched.

[0017]

[Embodiment] FIG. 1 shows a computer system 1 according to the present invention.
FIG. The computer system 1 is a CP
U11, memory controller 12, memories 13, 14,
and a clock generator 15, and between them are a data bus 30, an address bus 31, and a clock generator 15.
33, 35, control buses 32, 34, 36, and other control lines.

Note that the computer system 1 is provided with an IO for monitoring and input/output of data with the outside, but it is omitted in FIG. 1.

The memory controller 12 includes a decoder 21
is provided. The memory controller 12 is a CPU
Based on the address specified from 11, memory 13,
14, and C
Memory 13 based on the control signal from PU11
Alternatively, it outputs a memory control signal to 14 to control the memory. In other words, the address in this embodiment corresponds to the device designation signal in the present invention.

The decoder 21 determines which memories 13 and 14 the CPU 11 is attempting to access based on the address from the CPU 11, and sends a clock select signal CSS to the clock generator 15 through the control line 38 according to the determination result. Output. The clock select signal CSS is for setting the optimum clock frequency according to the access speed of the memories 13 and 14.

The clock select signal CSS is, for example,
The signal is "H" for the memory 13 with a fast access speed, and "L" for the memory 14 with a slow access speed. The decoder 21 that outputs such a clock select signal CSS can be easily realized using logic elements.

The memories 13 and 14 are both readable and writable memories having a plurality of memory blocks. The access time of the memory 13 is tac4, and the access time of the memory 14 is tac5, which is longer. In other words, the access speed of the memory 13 is faster than that of the memory 14.

Data regarding the access time of the memories 13 and 14 or the optimum clock frequency based on the access time is set in advance so that the CPU 11 can recognize it. For example, it is stored as a program or data in the memories 13 and 14, or set in a dip switch (not shown). The data is transferred from the CPU 11 to the memory controller 12 when the computer system 1 is started up.

The clock generator 15 generates a system clock CLK and supplies it to the CPU 11. System clock CLK generated by clock generator 15
The frequency of is immediately switched and supplied to the CPU 11 based on the above-mentioned clock select signal CSS.

[0025] Therefore, the CPU 11 uses the memory 13,1
4, the memory controller 12 specifies an address for one of the memories 13, 14, and sends a chip select signal, read/write designation signal, etc. to either of the memories 13, 14. Output.

At the same time, the decoder 21 of the memory controller 12 outputs a clock select signal CSS based on the address, and based on this signal, the clock generator 15 selects the system clock CLK of the optimum frequency for the designated memories 13 and 14. is supplied to the CPU 11, so accesses from the CPU 11 to the memories 13 and 14 are executed in synchronization with the system clock CLK of this optimum frequency.

FIG. 2 shows a timing diagram when the memory 13 with a fast access speed and the memory 14 with a slow access speed are accessed consecutively.

According to FIG. 2, the data read from the memory 13 is established after a time tac4 has elapsed since the address "N" for the memory 13 is established, and is then fetched by the CPU 11 after a time td has elapsed. .

Next, data read from the memory 14 is established after a time tac5 has elapsed since the address "M" for the memory 14 has been established, and then fetched by the CPU 11 after a time td has elapsed.

While the address "N" is specified, the clock select signal CSS is "H" in order to access the memory 13, so that the clock generator 15 is activated at T1 and T1 in the first half of FIG. A high frequency clock signal such as T2 is supplied to the CPU 11, but when address "M" is specified, the memory 14
In order to access the clock select signal CSS is
As a result, the clock generator 15 supplies low frequency clock signals to the CPU 11 as shown at T1 and T2 in the latter half of FIG.

According to the above embodiment, as shown in FIG. 2, although the memories 13 and 14 having different access speeds are used, the respective memories 13 and 1
There is no wasted time when accessing 4, so the processing speed is fast and maximum performance can be obtained.

FIG. 3 is a timing diagram when the access time is tac2, which is the same as shown in FIG. 6, and FIG. 4 is a timing diagram when the access time is tac3, which is the same as shown in FIG. .

According to these figures, even when various memory devices with different access speeds are used, the processing speed is improved because the wasted time that conventionally occurs during access is eliminated.

Note that from the point of view of processing speed, it is preferable to set the dead time to zero, but it is also possible to take into consideration the stability of the computer system 1 and allow some margin.

In the embodiment described above, the memories 13,1
Although the data regarding the access speed of No. 4 has been set in advance, it is also possible to automatically detect this. For example, the memory 13, 14 itself has a function to hold the data, and the data is transferred to the CPU 11 when the power is turned on.
It is possible to have a function to send data to.

The memory 13 can also be clocked at various clock frequencies.
, 14 may be repeatedly accessed, and the frequency at which the data can be accessed without error may be detected as the optimal frequency for the memories 13, 14.

In the above embodiment, the case where two types of memories 13 and 14 having different access speeds are used has been described, but three or more types may be used. memory 13,
The configuration of 14 can be changed in various ways. Further, the present invention can be applied not only to the memories 13 and 14 but also to memory devices in which data is substantially read and written, such as IO, other registers, and buffers. In addition, the configuration of the computer system 1 and its respective parts can be modified in various ways other than those described above.

[0038]

According to the present invention, when a plurality of memory devices having different access speeds are used, the processing speed corresponding to each access speed is maintained, and the processing speed of the system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer system according to the present invention.

FIG. 2 is a timing diagram when memories with different access speeds are successively accessed in the computer system of FIG. 1;

FIG. 3 is a timing diagram when the memory access time is tac2.

FIG. 4 is a timing diagram when the memory access time is tac3.

FIG. 5 is a conventional timing diagram when accessing a memory device when the clock frequency is optimal.

FIG. 6 is a timing diagram when accessing a memory device with a slow access speed in the related art.

FIG. 7 is a timing diagram when accessing a memory device with a high access speed in the related art.

[Explanation of symbols]

1 Computer system 11 CPU 13 Memory (memory device) 14 Memory (memory device)

Claims (1)

[Claims] Claim 1: A computer system comprising a plurality of memory devices that are designated and accessible by a device designation signal output from a CPU, wherein the system A memory control method characterized by variably setting the clock frequency of a reference clock.