JPH07143133A - Multi-layer protocol processor for common use of memory - Google Patents

Abstract

PURPOSE:To reduce a required memory quantity by using a memory for storing line input output data in common for layers and transferring the data indirectly through the use of addresses stored in the common use memory. CONSTITUTION:Each processing among layers 1-3 is implemented respectively by a layer 1 protocol processing section 101, a layer 2 protocol processing section 102, and a layer 3 protocol processing section 103. Each of the protocol processing sections 101-103 is connected to a common use memory 105 through a system bus 104 and to a bus contention arbitration control section 106 controlling the use of the common use memory 105. That is, each of the protocol processing sections 101-103 and the common use memory 105 are connected through the bus to be accessible to each other, and the bus contention arbitration control section 106 is connected to each processing section so as to avoid the collision when the bus is in use. Then input output line data themselves are not directly transferred among the layers 1-3 but transferred indirectly based on addresses stored in the common use memory 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layer 1 to layer 3 data communication processing apparatus based on a hierarchical structure, and more particularly to a data communication processing apparatus when the ATM protocol is used for layer 1.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing the configuration of a conventional data communication processing device. The conventional technique will be described below with reference to FIG.

In the apparatus shown in FIG. 4, the layer 1 protocol processing section 201, the layer 2 protocol processing section 202, and the layer 3 protocol processing section 203 perform respective processes of layers 1 to 3 respectively. The layer 2 protocol processing unit 202 and the layer 3 protocol processing unit 203 are connected to the layer 2 and layer 3 line data memory 206 via the system bus 204, and a bus contention arbitration control unit for controlling the usage status of the memory 206. It is connected to 207. The layer 1 protocol processing unit 201 using the ATM protocol is provided with a layer 1 line data memory 205 dedicated to layer 1 and is connected thereto because high speed processing is required.

A conventional layer 1 protocol processing unit 201
In the protocol processing performed by (ATM) and the layer 2 protocol processing unit 202, the processing is performed with the data segment, which is the combination of the user data and the header information of each layer, as the input data.

In the layer 1 protocol processing unit 201, cells 208 are transmitted / received to / from lines (users, terminals).
As processing on the receiving side at this time, the received cell 208 is stored in the next layer 1 line data memory 205 and assembled into a frame, and then the layer 2 protocol processing unit 202.
Transferred to. As the transmitting side processing, the frame transmitted from the layer 2 protocol processing unit 202 is decomposed into cells,
It is output as cell 208.

[0006] The layer 2 protocol processing unit 202 transmits / receives a frame to / from the layer 1 protocol processing unit 201. At this time, as the receiving side processing, the layer 2 protocol processing is performed by the header information in the input frame, After that, the header is deleted and the packet is delivered to the layer 3 protocol processing unit 203. As the transmitting side processing, header information is added to the packet received from the layer 3 protocol processing section 203 and transferred to the layer 1 protocol processing section 201 as a frame.

As described above, conventionally, layer 1 and layer 2
Frames were transferred directly between.

[0008]

The conventional data communication processing device described above has the following two problems.

(1) Double storage of user data Layer 1 requires a memory for storing user data (frames in this case) in the line input / output data dedicated to layer 1, and layers 2 and 3 for layers 2 and 3 It requires a memory for storing user data (packet) in a data segment (frame) to be transmitted / received to / from the layer 1.

The contents of the line data are composed of user data and header information of each layer, but most of them are occupied by user data. This user data is data that each layer does not refer to, and is originally not required for the protocol processing in each layer processing unit. Storing most of this line data and data not required by each layer protocol in layer 1 and layer 2 unnecessarily increases the memory amount of the entire system.

(2) Deterioration of processing capacity due to inter-layer data transfer User data occupying most of line data is layer 1
-By transferring between layers 2, it is necessary to perform the transfer processing in addition to the protocol processing, and the protocol processing capacity is reduced accordingly.

The present invention has been made in view of the problems of the above-described conventional technique, and is a layer 1 (AT) in a system based on a layer structure.
M), layer 2, and layer 3 are used for protocol processing, the amount of memory required for the entire system is reduced, and the processing capacity of the entire system is reduced.

[0013]

A memory sharing multi-layer protocol processing device of the present invention is a device for performing data communication processing based on a hierarchical structure, and is a layer 1 protocol processing device, a layer 2 protocol processing device and a layer 3 protocol. Each layer protocol processing has a processing device and a shared memory that stores user data and data such as header information used for protocol processing of each layer that is input / output between each layer protocol processing device and a line. Each of the devices is configured to access the shared memory,
In the frame transfer performed between the layer 1 and the layer 2 and the packet transfer performed between the layer 2 and the layer 3, the start and end addresses in the stored shared memory are not directly transferred. It is characterized in that data is indirectly transferred by a value.

[0014]

A shared memory for storing line input / output data is configured to be accessible by each layer protocol processing device, and frame transfer between layer 1 and layer 2 is indirectly performed by an address stored in the shared memory, not by the frame itself. Therefore, the memory for storing the line input / output data can be integrated into one.

Further, since the amount of data transferred between layer 1 and layer 2 is reduced, the processing required for data transfer in both protocol processing units is reduced.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and shows the outline of a block configuration of a layer 1 to 3 protocol processing device based on the present invention and the flow of data.

In this embodiment, the layer 1 protocol processing unit 1
01, the layer 2 protocol processing unit 102, and the layer 3 protocol processing unit 103 perform the respective processes of layers 1 to 3. Each protocol processing unit is connected to the shared memory 105 via the system bus 104, and
It is connected to a bus contention arbitration control unit 106 that controls the use of the shared memory 105.

Each reference numeral in the drawing indicates the following contents.

A0: packet start address a1: packet end address A0: frame start address A1: frame end address L2C: layer 3 protocol processing unit 103 to layer 2
Command to Protocol Processing Unit 102 L2S: Layer 2 Protocol Processing Unit 102 to Layer 3
Status Report to Protocol Processor 103 L1C: Layer 2 Protocol Processor 102 to Layer 1
Command to Protocol Processing Unit 101 L1S: Layer 1 Protocol Processing Unit 101 to Layer 2
Status Report to Protocol Processing Unit 102 X0: L2C storage address X1: L2S storage address X2: L1C storage address X3: L1S storage address In the present invention, realization of a change from the conventional configuration is a means for solving the problem.

That is, the following two points are realized.

(1) Connecting the Layer 1 Protocol Processing Unit to the Bus Since the memory that was conventionally dedicated to the Layer 1 protocol becomes the memory connected to the bus and shared by the protocols, Layer 1
A bus sequence (bus acquisition / release) processing circuit is added to the processing unit.

(2) Layer 1 from frame to address
-Change of interface between layer 2 Since the frame was directly passed between the conventional layer 1 (ATM) and layer 2, this was changed to indirectly pass the frame by the start address and the end address of the shared memory. To do.

Characteristic portions of the apparatus configuration and processing sequence in this embodiment for realizing the above will be described below.

(1) Device Configuration The present embodiment is greatly changed in that the frame storage memory, which is used exclusively by the protocol processing unit for layer 1 in the conventional example shown in FIG. 4, is connected to the bus. .

The protocol processing units of layers 1 to 3 and the shared memory used by them are connected to the bus so that they can access each other. The bus contention arbitration control unit 106 is connected to each protocol embedding unit 106 so as not to collide with each other when the bus is used. The I / O line data itself is not directly transferred between the layers, but is indirectly transferred by the address where it is stored in the shared memory. The address is, for example, a primitive (L2C, L2) between layers in FIG.
2S, L1C, L1S).

In order to have the above configuration, it is necessary to add a circuit for outputting a bus acquisition request to the bus contention arbitration control unit before accessing the frame storage memory. The same circuit as the protocol processing unit for 3 and layer 2 is used as it is, and the bus contention arbitration control unit is a two-way arbitration of the protocol processing unit for layer 3 and the protocol processing unit for layer 2 If the three-party arbitration is also added, the amount of change can be reduced, and if layer 1 is set to the highest level in the priority of competition, the layer 1 protocol processing part uses the shared memory in a state almost dedicated. As a result, almost the same circuit as the conventional circuit can be used.

In this embodiment, the contention arbitration control unit is a three-party arbitration unit, and the layer 1 protocol processing unit 101 has the highest priority as the priority of the contention of the shared memory 105.

(2) Processing Sequence Next, an embodiment will be described in which a frame is directly transferred between layer 1 and layer 2 but indirectly transferred by an address at which the frame is stored in the shared memory. The following two points are the points to be considered in the device configuration and the processing procedure when passing the address.

: Transfer method of frame storage address between layer 1 and layer 2: Where to manage frame storage address: direct transfer method between layer 1 and layer 2 or method via shared memory And the logical selection of what data format the frame store address should be transferred to (for example, whether only the address is transferred or is transferred with other primitives). It can be roughly divided.

In this embodiment, a method of physically matching with another primitive through a shared memory is shown. For example, when the layer 1 protocol processing unit 101 completes frame assembly, it outputs an L1S activation signal for reporting the current state to the layer 2 protocol processing unit 102. Upon receiving this, the layer 2 protocol processing unit sets L to the predetermined L1S storage address X3.
Go read 1S. The content of L1S indicates that the assembly is completed as a primitive, and the frame start address A0 and the frame end address A1 indicating the frame storage address are also shown.

The item (1) affects the processing sequence in the apparatus. For example, when memory management is performed by the layer 3 protocol processing unit 103, a memory address for receiving data (empty area) and a memory for transmitting data (data is stored in order from layer 3 to layer 2 and layer 2 to layer 1) The stored area) is transmitted.

FIG. 2 is a diagram showing a receiving side processing sequence when the layer 3 protocol processing unit 103 manages addresses, and FIG. 3 is a diagram showing a transmitting side processing sequence by the same address management.

First, the processing at the time of reception will be described with reference to FIG.

When a valid cell is received from the line and an address request for receiving the cell is sent from the layer 1 protocol processing section 101 through the layer 2 protocol processing section 102, the layer 3 protocol processing section 103 is sent. Does a search for an empty area to handle this. Thereafter, the address indicating the empty area, which is the above-mentioned search result, is sent to the layer 1 protocol processing unit 101 via the layer 2 protocol processing unit 102. The layer 1 protocol processing unit 101 performs layer 1 protocol processing for assembling a frame from the address indicated by the instruction, and then notifies the layer 2 protocol processing unit 102 of the end address indicating the length of the assembled frame. The layer 2 protocol processing unit 102 performs layer 2 protocol processing from the head address where the frame is assembled to the end of the frame into a packet, and notifies the layer 3 protocol processing unit 103 that the packet is received and the address where the packet is stored. To do. In response to this, the layer 3 protocol processing unit 103 performs layer 3 protocol processing.

Next, processing at the time of transmission will be described with reference to FIG.

When the layer 3 protocol processing section 103 sends a packet transmission request and the address in which the packet is stored to the layer 2 protocol processing section 102, the layer 2 protocol processing section 102 performs layer 2 protocol processing. As a result, when the address at which the frame corresponding to the transmission packet is stored is confirmed, the frame 1 is sent to the layer 1 protocol processing unit 101 together with the confirmed address. The layer 1 protocol processing unit 101 performs a layer 1 protocol process (ATM protocol process) for reading a frame stored at a specified address and disassembling it into cells 107, and sending this to a line and a layer 2 protocol. An end notification indicating that the transmission process is completed is sent to the processing unit 102. Layer 2 protocol processing unit 10
In 2, the layer 2 protocol processing for updating the state variable changed by the transmission is performed, and the transmission completion notification is sent to the layer 3 protocol processing unit 103. The layer 3 protocol processing unit 103 performs a layer 3 protocol process for updating a state variable, and also performs a process for adding an empty area to a managed address.

[0038]

Since the present invention is constructed as described above, it has the following effects.

The memory for storing the line input / output data is shared by layers 1 to 3, and the frame transfer between the layer 1 and the layer 2 is indirectly transferred not by the frame itself but by the address stored in the shared memory. By consolidating the memories for storing the input / output data into one, it is possible to reduce the required memory amount of the entire apparatus.

Further, since the amount of transfer data between layer 1 and layer 2 is reduced, the processing required for data transfer in both protocol processing units can be reduced, and the processing speed can be improved. is there.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a sequence diagram showing processing at the time of reception in the embodiment shown in FIG.

FIG. 3 is a sequence diagram showing processing at the time of transmission of the embodiment shown in FIG.

FIG. 4 is a diagram showing a configuration of a conventional example.

[Explanation of symbols]

 101 Layer 1 Protocol Processing Unit 102 Layer 2 Protocol Processing Unit 103 Layer 3 Protocol Processing Unit 104 System Bus 105 Shared Memory 106 Bus Contention Arbitration Control Unit 107 Cell

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[Procedure amendment]

[Submission date] November 10, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (1)

[Claims] 1. A device for performing data communication processing based on a hierarchical structure, comprising: a layer 1 protocol processing device, a layer 2 protocol processing device, and a layer 3 protocol processing device; and between each layer protocol processing device and a line. A shared memory that stores user data and data such as header information used for protocol processing of each layer,
Each of the layer protocol processing devices is configured to be accessible to the shared memory, and shared memory is used for frame transfer performed between layer 1 and layer 2 and packet transfer performed between layer 2 and layer 3. A memory sharing multi-layer protocol processing device characterized in that data is indirectly transferred by the start and end address values stored in a shared memory without directly transferring the data stored in the memory.