JPH0546564A - Message pass system - Google Patents

Abstract

PURPOSE:To improve the memory efficiency by securing a constitution where a processor takes a desired block out of a buffer pool for exchange of information and uses the block as a communication area. CONSTITUTION:In a message pass system where the information are exchanged to each other, a shared memory CM 20 is divided into the processor control areas PD 21 which are controlled by each processor. Each PD 21 includes a block BL 3K consisting of a memory area of the fixed length and a control area 4K which stores the head address of the precedent BT, 3K connected to the head address of the next BL 3K connected in the corresponding BL 3K. Then a head address is designated in the area 4K so that all relative blocks BL 3K are connected to each other for formation of a buffer pool. When a processor 1N wants to transmit a coupling message, an interruption signal is sent to the distant side of communication together with the head address of a chain block. Then a desired BL 3K is taken out of the buffer pool and a communication area is acquired for transmission of the message.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a message path system for exchanging information between a plurality of processors having a commonly accessible shared memory.

[0002]

2. Description of the Related Art Conventionally, as a message path system for exchanging information between a plurality of processors having a commonly accessible shared memory, a message path system shown in FIG. 12 is known. In this conventional message path system, in order to exchange information between the two processors 11 and 12, the processors 11 and 12 and the shared memory 20 are connected by the shared memory input / output buses 101 and 102, and the processor 11 and the shared memory 20 are connected. , 12 are connected to interrupt signal lines 103 and 104.

When information is exchanged between the two processors 11 and 12, a shared memory 20 is provided with a communication area having a fixed address and a memory of a fixed size for information exchange. Data is written in this communication area and transmitted to the other party by an interrupt signal. In response to this, the other party reads the data from this communication area for processing, or saves the data in a memory it manages. Then, after this, by notifying that the data can be written again in the communication area to the message transmitting side processor in the same manner, if there is further communication information, this transmitting side processor again communicates. Information was exchanged by making it possible to write in an area and repeatedly using a fixed area size communication area.

[0004]

However, in such a conventional message path method, since the communication area is fixed, when it is desired to continuously send messages, the communication for the previously sent messages is performed. It is necessary to wait until the area becomes free.Therefore, it is necessary to provide an area for multiple messages and to control communication waiting by software processing, which complicates the processing for transmission and communication area management. , There was a problem that message transfer efficiency was poor.

Further, since it is necessary to predict a situation in which a transmission message or a reception message is likely to occur continuously and to provide a message area commensurate with it as a communication area, an extra memory area that is not normally used Had to be obtained, and there was a problem that memory efficiency was also poor.

Further, when the receiving side processor continuously receives a plurality of messages, this processor must interrupt the processing before receiving the message in order to process these messages or save the messages. In some cases, there is a problem in that even if the process before reception is highly urgent, the process may be interrupted.

The present invention has been made in view of the above-mentioned problems of the prior art, and each processor efficiently uses a memory to enable information exchange with good transfer efficiency, and each processor has its own processing capability. An object of the present invention is to provide a message path method capable of processing a received message at a timing.

[0008]

According to the present invention, in a message path system in which information is mutually exchanged via a shared memory that can be commonly accessed by a plurality of processors, each shared memory is managed by each processor. Each processor management area is divided into blocks consisting of memory areas of a certain length, and in each block, the start address of the next block to be connected and the start address of the previous block By providing a control area for storing each block, by designating the start address in the control area of each block, all the related blocks are connected to form a buffer pool, and the processor that transmits information determines how many times from the buffer pool. A phase in which another block is separated, information is written to the separated block, and information is exchanged. To, the processor that transmits the head address of the head block of the block chain in which the information is written together with the interrupt signal and receives the information, when the interrupt signal is detected, processes the block chain in which the transmitter processor has written the information. After the information is processed by the processing program, it is connected to the processing waiting chain managed by the program by rewriting the contents of the control area provided in the block. Rewriting the information content of the block chain which has been processed to the information indicating that the process has been completed, and transmits the start address of the start block of the block chain together with the interrupt signal, and the transmission side processor detects the interrupt signal, and The receiving processor writes the processing completion information The block chain, to the pending chain managed by the processing program,
When the processing area is connected by rewriting the contents of the control area provided in the head block and the processing program processes the block chain passed from the reception side processor and indicating the completion of processing, the head block of the block chain By rewriting and connecting the contents of the control area and the contents of the control area in the block of the buffer pool, the memory block used in the information exchange is returned to the buffer pool.

[0009]

According to the message path method of the present invention, the processor only needs to separate blocks from the buffer pool for information exchange and use them as communication areas, so that memory efficiency is improved. Also, when the processor wants to send messages continuously, after sending an interrupt signal to the communication partner together with the start address of the chain block,
It is possible to separate some blocks from the buffer pool again and acquire the communication area for transmission, thus improving the transfer efficiency.

Further, since the receiving block ends the receiving process by connecting by rewriting the control areas of the received block chain and the processing waiting chain, the processing of the information is processed according to the processing capacity and timing of the receiving processor. Can be done.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a system using an embodiment of the present invention, in which a plurality of processors 11, 12, ...
05 is connected to each of the processors 11, 12, ... 1
Shared memory input / output bus 10 between N and shared memory 20
6 is connected.

As shown in FIG. 2, each processor 11, 1
2, ..., 1N are provided with a message transmission function unit 111 that controls a message transmission function, a message reception function unit 112 that controls a message reception function, and a message processing function unit 113 that processes a message.

Further, as shown in FIG. 3, the shared memory 20
Is a processor management area 21 managed by each processor,
, ..., 2N. Each of the processor management areas 21, 22, ..., 2N is divided into blocks 31, 32, ..., 3K having a constant length as shown in FIG. 4, and each of the blocks 31, 32 ,. Are provided with control areas 41, 42, ..., 4K.

Each control area 41, 42, ..., 4
As shown in FIG. 5, K is an N pointer 51 that stores the start address (Nadr) of the next block to be connected, and a P pointer 52 that stores the start address (Padr) of the connected previous block, .., 4N control areas 41, 42, ..., 4N, which are composed of a control area 53, can be connected to several blocks by designating Nadr and Padr of 4N.

The operation of the message path system having the above configuration will be described below.

There are two methods of using the P pointer of the first block of the block chain and the N pointer of the last block of the block chain. The first is information (Itop) indicating that the P pointer of the head program of the block chain is the head of the block chain.
1) is entered, and the information (Ibtm1) indicating the end of the block chain is added to the P pointer of the head block of the N pointer of the last block of the block chain. The second method is to enter the total number of blocks in the block chain including the first block of the block chain. Hereinafter, the former method will be referred to as a pointer usage method 1 and the latter method will be referred to as a pointer usage method 2. It should be noted that the pointer use method is unified and used in the system as a whole.

To create a block chain adopting the pointer usage method 1, for example, as shown in FIG. 4, Padr of the control area 41 of the block 31 is set to Itop1 and Na is set to Na.
The block 32 is linked to the block 31 by setting dr as the head address of the block 32 and further setting Padr of the control area 42 of the block 32 as the head address of the block 31. Next, the Nadr of the control area 42 is set as the head address of the block 33, and the Padr of the control area 43 of the block 33 is set as the head address of the block 32.
Block 33 is linked to block 32. Subsequently, the blocks are sequentially connected in the same manner, and finally the Nadr of the control area 4K of the block 3K is set to Ibtm1 to complete the connection of the blocks 31 to 3K.

When the pointer usage method 2 is adopted, in the example of FIG.
Becomes Itop2 and the number of blocks K. The processing program of each processor uses the Itop2 of the control area 41 and the number of blocks K to determine the last block 3K in the block chain.
Therefore, Nadr in the control area 4K is left as it is without being rewritten.

Each control area 41, 42, shown in FIG.
The 4K control area 53 stores information (Request) indicating that the processing of the processor of the message transmission destination is requested or information (Complete) indicating that the processing is completed. Note that these pieces of information are stored only in the first block of the chain block.

The buffer pool stores all blocks that are not used for processing the area managed by each processor.
As described above, it is configured by designating and connecting Nadr and Padr in the control area. Then, this buffer pool is created in the shared memory 20 in the areas 21, 22, ..., 2N managed by each processor.

Further, each processor 11, 12, ..., 1N
Has a pending queue in which incoming messages waiting for processing are concatenated. The processing program of each processor manages the processing waiting chain by knowing the head address of the head block of this processing waiting chain.
For example, as shown in FIG. 6, in the processing waiting chain 62 of the processor 12, blocks 71, 72, ..., 7M are waiting for the processing of the processor 12. Then, these blocks are controlled by the control areas 81, 8 of each block as described above.
2, ..., 8M are linked by specifying Nadr and Padr. Then, the processing program of the processor 12 knows the start address of the block 71, so that when the processor 12 starts the received message processing, the block 71 is accessed.

Now, assuming that the pointer processing method 1 is used, there are connected blocks 31, 32, ..., 3K as shown in the flowcharts of FIGS. 4 and 9.
It is assumed that this block chain is a buffer pool that can be used by the processor 11, and the processor 11 sends J blocks of messages (J is K or less) to the processor 12. At this time, first, as shown in FIG. 7, the processor 11 controls the control area 4 (J) of the block 3 (J + 1).
Paddr of +1) is set to Itop1 (steps S1 and S2 in FIG. 9), and N of the control area 4J of the block 3J is set.
By setting adr to Ibtm1, the block chain 9 of the blocks 31 to 3J from the buffer pool
1 is separated (step S3), the control area of the control area 41 of the block 31 is set to Request (step S4), information is written in the block chain 91, and the start address of the block 31 is transmitted to the processor 1 together with the interrupt signal. At this point, the buffer pool of the processor 11 becomes a block chain from block 3 (J + 1) to block 3K, and after transmitting the previous interrupt signal, the processor 11 can perform the next processing. 〓 (steps S5 to S7).

On the other hand, as shown in the flow chart of FIG. 10, when the processor 12 detects the interrupt signal, the processor 12 knows the start address of the block 31 by reading the transmitted address (step S11), and rewrites the control area. The transmitted block chain 91 is linked to the processing waiting chain of the processor 12 (step S
12-S15).

If the processing wait chain when the processor 12 detects this interrupt signal is as shown in FIG. 6, the processor 12 determines the Nadr of the control area 8M of the block 7M as shown in the flow charts of FIGS. To the head address of the block 31, the Padr of the control area 41 of the block 31 is rewritten to the head address of the block 8M (steps S21 and S22), and when the information of the block chain 91 is processed, the control area of the control area 41 is To Complete (steps S23 and S24), and the start address of the block 31 is transmitted to the processor 11 which is the message transmission source together with the interrupt signal (steps S25 to S30).

Processor 11 that has detected this interrupt signal
Connects the block chain 91 to the processing waiting chain of the processor 11 as a received message, as shown in the flowchart of FIG. This connecting method is similar to the connecting method of the processor 12 to the processing waiting chain 62 described above, and the Nadr of the control area of the last block of the processing waiting chain of the processor 11 is set to the head address of the block 31 (step S12). , S14), block 3
The connection is completed by setting the Padr of the control area 41 of No. 1 as the head address of the last block of the processing waiting chain (step S15).

Also here, the control area 4 of the block 31
If the waiting queue for the Padr of 1 is empty (step S12), the Padr of the control area 41 of the block 31 is
Is set as Itop1 and the processor 11 notifies the processing program of the start address of the block 31 as the start address of the processing waiting chain. Similar reception processing is performed even when the processing waiting chain 62 of the processor 12 is empty (step S13).

When the processing program of each processor processes the block chain of the processing waiting chain,
As shown in the flow chart of No. 1, the control area of the control area of the first block is Request and Com.
It is confirmed which one is a plete (step S2
1, S22).

The control area is Compl.
When ete, this blockchain is returned to the processor's buffer pool. For example, when the processing chain processes the block chain 91 and the processing chain is connected to the processing waiting chain of the processor 11, when the processing program processes the block chain 91, the processor 11 controls the control area 41 of the control area 41. When there is Complete information in the processor 1, the Padr in the control area 41 of the block 31 is set to the processor 1
The first address of the last block of the buffer pool of 1,
N of the control area of the last block of this buffer pool
By setting adr to the head address of the block 31, the block chain 91 is connected to the buffer pool of the processor 11. By doing this, blockchain 9
1 is returned to the buffer pool of the processor 11 and used again for the processing of the processor 11 (step S3).
1).

When the above-mentioned processing is carried out by the pointer usage method 2, only the method of separating blocks and the method of connecting block chains are different, and the processing of the other processors 11 and 12 is the same. Then, when the blocks are separated using the pointer usage method 2, for example, in FIG. 7, the Padr of the control area 41 of the block chain 91 is Itop2 and the number of blocks J.
The Naar in the control area 4J remains unchanged and does not change. Padr of control area 4 (J + 1) is It
op2 and the number of blocks (K-J), control area 4K
Nadr remains unchanged.

Regarding the connection between the block chains, for example, when connecting the block chain 91 to the block chain 62 as shown in FIG. 8, the number of blocks of Padr in the control area 81 is changed from M to (M + J). ,
The connection can be completed by setting the Nadr of the control area 8M as the head address of the block 31 and the Padr of the control area 41 as the head address of the block 7M.

[0032]

As described above, according to the present invention, the processor separates as many blocks from the buffer pool as necessary for information exchange so that the blocks can be used as a communication area. Can also use the buffer pool to improve memory efficiency. Also, when the processor wants to send messages continuously, after sending an interrupt signal to the communication partner together with the start address of the chain block, some blocks are again separated from the buffer pool to acquire the communication area and send. Therefore, the transfer efficiency can be improved. In addition, the receiving processor
By rewriting the control area, the received block chain and the processing waiting chain are linked to terminate the receiving process, so that the processing of the information can be performed in accordance with the processing capacity and timing of the receiving side processor, The system can be used efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a processor in the above embodiment.

FIG. 3 is a block diagram showing an internal configuration of a shared memory in the above embodiment.

FIG. 4 is a block diagram showing a configuration example of a buffer pool according to the above embodiment.

FIG. 5 is a block diagram showing an internal configuration of a control area in the above embodiment.

FIG. 6 is a block diagram showing a configuration example of a processing waiting chain according to the above embodiment.

FIG. 7 is a block diagram showing a method of using a buffer pool according to the above embodiment.

FIG. 8 is a block diagram showing a configuration example of a processing waiting chain according to the above embodiment.

FIG. 9 is a flowchart showing a block chain transmission procedure according to the pointer usage method 1 according to the above embodiment.

FIG. 10 is a flowchart showing a block chain reception procedure according to the pointer usage method 1 according to the above-described embodiment.

FIG. 11 is a flowchart showing a processing wait chain processing procedure according to the pointer usage method 1 according to the embodiment.

FIG. 12 is a block diagram showing a system configuration of a conventional example.

[Explanation of symbols]

 11, 12, ..., 1N processor 20 Shared memory 21, 22, ..., 2N processor management area 31, 32, ..., 3K block 41, 42, ..., 4K Control area 51 N pointer 52 P pointer 53 Control area 62 Waiting for processing Chain 91 Block chain 105 Interprocessor interrupt signal line 106 Shared memory input / output bus

Claims (1)

[Claims] 1. In a message path method in which information is mutually exchanged via a shared memory that can be commonly accessed by a plurality of processors, the shared memory is divided into processor management areas managed by the respective processors, Divide each processor management area into blocks consisting of a fixed length memory area,
In each block, a control area for storing the start address of the next block to be connected and the start address of the previous block connected is provided, and by specifying the start address in the control area of each block, all related The block that connects the blocks of the above to configure the buffer pool, and sends the information to the processor, separates some blocks from the buffer pool, writes the information to the separated block, and writes the information to the other party with whom the information is exchanged. When the processor that transmits the head address of the head block of the chain together with the interrupt signal and receives the information detects the interrupt signal, the block chain in which the transmitter processor has written the information is transferred to the processing waiting chain managed by the processing program. , Rewrite the contents of the control area provided in the block After further connection, after the information is processed by the processing program, the receiving processor rewrites the information content of the block chain, which is passed from the transmitting processor and completed the processing, to the information indicating that the processing is completed, and The start address of the first block of the block chain is transmitted together with the interrupt signal, and when the transmitter processor detects the interrupt signal, the receiver processor waits for the processing program to manage the block chain in which the receiver processor has written the processing completion information. When the processing program processes the block chain indicating the completion of processing, which is passed from the receiving side processor, by connecting to the chain by rewriting the contents of the control area provided in the first block, The contents of the control area of the first block and the buffer A message path method characterized in that the memory blocks used in information exchange are returned to the buffer pool by rewriting and concatenating the contents of the control area in the block of the pool.