JPH07121142A - Gradation data generating circuit - Google Patents

Abstract

PURPOSE:To make the circuit board small by using the same registers for odd-numbered pixels and even-numbered pixels of a display screen as registers selected according to display positions. CONSTITUTION:A thinning-out control part 8 outputs a decision signal for deciding the odd-numbered pixels and even-numbered pixels to be thinned out and a control signal such as a frame number. A gradation table register part 9 is a register which stores data to be thinned out by a thinning-out part 10. The thinning-out part 10 thins out the data, supplied from the gradation table register part 9, into display data to be outputted to a liquid crystal display device 12. A decoding part 13 decodes the frame number supplied from the thinning-out part 8 and the decision signal for deciding the odd-numbered and even-numbered pixels. Then the same register 9 is selected for the odd-numbered and even-numbered pixels of the display screen with the thinning-out signal generated by combining the decision signal for deciding the odd-numbered and even-numbered pixels and the frame number and the data are thinned out to generate the display data having gradations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention stores the contents of books, newspapers, magazines, characters, line drawings, photographs, etc. in an electronic, optical or magnetic recording medium, and reads them out to obtain a liquid crystal display device. The present invention relates to a gradation data generation sea route for displaying on.

[0002]

2. Description of the Related Art Currently, books, newspapers, magazine characters, line drawings,
Character data such as photographs and data such as image data including gradations are recorded on an electronic, optical or magnetic recording medium, and the recorded data is read to generate display data to be displayed on a liquid crystal display device. A mobile terminal equipped with a circuit that operates is being developed. These mobile terminal devices are provided with a circuit for storing data recorded on a recording medium in a semiconductor memory such as VRAM, reading the stored data, and displaying a gradation on a liquid crystal display device.

As a display device, a color display using a color CRT is generally used, but in recent years, in response to needs for miniaturization of devices, devices called laptop type and notebook type have been commercialized. . In the laptop type and the notebook type, a liquid crystal display device or a plasma display device is used instead of a normal CRT in order to reduce the weight and make the device thinner.

By the way, the liquid crystal display device and the plasma display device are partially expensive in color type, but they are still expensive and usually display in a single color. An example of a technique for converting color display data into monochromatic display data such as a liquid crystal display device or a plasma display device is described in detail in JP-A-2-299020 and 3-85687.

In the gradation display of a liquid crystal display, when the recorded data is stored in the VRAM, it is stored as data converted into a weighted bit pattern. For weighting, for example, when 8-gradation display is performed, display data for one pixel is configured with a 3-bit width, and "000" is gradation 1, "001" is gradation 2, ..., "111" is gradation. Express it as 8. When the gradation data is stored in the VRAM, it is divided for each bit plane, such as the data area of the second bit, the data area of the first bit, and the data area of the 0th bit of the data constituted by the 3-bit width. Is stored. A mobile terminal equipped with a circuit for generating display data is
The gradation pattern data is generated by reading out the bit pattern stored in the VRAM.

The grayscale data displayed on the liquid crystal display device is obtained by thinning out the data read from the VRAM. As a data thinning method, a method such as frame thinning in which the read data is thinned and converted into display data can be considered. The display of the liquid crystal display device is performed by turning ON / OFF the display pixels, and the frame thinning controls the ON / OFF in time. For example, when it is attempted to display the gradation of a gradation display of a certain pixel, as shown in FIG.
[0011] is output to the liquid crystal display, the gradation 3 is displayed. That is, the frames 1 to 5 at the pixel position are turned off and the frames 6 and 7 are turned on.

In a display device using a liquid crystal display device, flicker occurs due to interference between the frequency of a fluorescent lamp and the frequency of display data of the liquid crystal display device. Also,
In a device for displaying gray scales of a liquid crystal display device, there is a possibility that screen frame flicker may occur due to a decrease in frame frequency of display data and arrangement of display data. This is because human eyes recognize ON / OFF of the display pixel which is performing display.

Now, let us consider a case where display data having the same gradation is output to a certain area. When the display data of gradation 3 described above is output, the display pixels in this fixed area are turned on / off.
Is performed simultaneously on all pixels in the area. If the power is turned on / off at the same time, the human eyes recognize this on / off, resulting in a flicker on the display screen.

In order to reduce this flicker, the structure of the display data may be changed. Taking the above-mentioned display data [0000011] as an example, first, in order to increase the frame frequency of the display data, [001011]
001]. Then, the configuration of the display data is changed for each line and each pixel. For example, considering horizontal display data, the odd pixels on the display screen are [0
010001] is displayed, and the number of even-numbered pixels is [100010].
The display data structure is changed for each pixel so as to display "0". The configuration of the display data in the vertical direction is changed in the same manner. In the vertical direction, the structure of the display data is changed according to the line number.

The configuration of the prior art is shown in FIG. As shown in FIG. 7, VRAM 101, latches 102, 103, 10
4, gradation data generation unit 105, address generation unit 106,
The display control unit 107, the thinning control unit 108, the gradation table register 109, the thinning unit 110, the display data latch unit 111, and the liquid crystal display device 112 are included. The display data output to the liquid crystal display device 112 is data thinned out by the line number, the line discrimination signal, and the pixel discrimination signal. The data to be thinned out has a register structure in order to reduce the above-mentioned flicker and flicker. A register in which an arbitrary value is written is selected by the data read out from the VRAM and converted into gradation data, and the data is thinned out.

The VRAM 101 is a semiconductor memory in which weighted data is divided and stored for each bit plane. Latches 102, 103, and 104 are latches that read out the data stored for each plane and hold the data for each plane. The gradation data generation unit 105 generates gradation data from the data held in the latch for each plane.

The address generator 106 is a VRAM 101.
Generate the read address of. The display control unit 107
It reads the VRAM, controls thinning and thinning, and controls the liquid crystal display device. The thinning control unit 108 outputs a control signal 123 such as an odd / even pixel determination signal for performing thinning, an odd / even line determination signal, and a frame number. The gradation table register 109 is an 8-bit width register that is connected to the CPU bus and can be written to any value.

The thinning section 110 uses the frame number, the odd / even line discrimination signal and the odd / even pixel discrimination signal supplied from the thinning control section 108, and the gradation data 124 supplied from the gradation data generation section 105. The register setting values supplied from the gradation table register 109 are thinned out and the display data is output to the display data latch unit 111.
The display data latch unit 111 holds the data output from the thinning unit 110, and the liquid crystal display device 11 at the timing of the control signal output from the thinning control unit 108.
Output data to 2. Liquid crystal display device 112
Is a device for turning on / off the display pixel of the liquid crystal panel at the timing of the control signal supplied from the display control unit 107 to the input display data.

As shown in FIG. 8, the gradation table register 109 and the thinning section 110 are composed of the gradation table registers 140 to 143 and the frame thinning sections 160 to 16 respectively.
3, the gradation multiplexer units 164 to 167, the line thinning units 168 to 169, and the pixel thinning unit 170. A signal for writing data to this register is supplied from a CPU (not shown).

The gradation table register 140 is a register in which the display screen has odd lines and the gradation table of odd pixels is stored. Gradation table register 14
Reference numeral 1 is a register in which the display screen has odd lines and a gradation table of even pixels is stored. The gradation table register 142 is a register in which a gradation table register of an odd pixel is stored while the display screen is an even line. The gradation table register 143 is a register in which the display screen has even lines and the gradation table of even pixels is stored.

The frame thinning units 160 to 163 use the frame number as a selection signal from a register of 8 gradations and 8 bits in width (7 bits for 7 frames, 1 dummy bit) supplied from the gradation table registers 140 to 143. , A gradation table of 8 gradations having the same frame number is selected. The selected gradation table is data of 8 gradations _x 1 frame and 8 bits wide.
163 is composed of eight 8-to-1 multiplexers.

The gradation multiplexer units 164-167 are
One gradation and one frame of data are selected using gradation data as a selection signal from a gradation table of 8 gradations and 1 bit width (1 bit for 1 frame) supplied from the frame thinning units 160 to 163. Selected data is 1 gradation
It is data of 1-bit width of _X1 frame, and each of the gradation multiplexer units 164 to 167 is composed of one multiplexer of 8to1.

The line thinning units 168 to 169 use the odd / even line discriminating signal for discriminating between the odd line and the even line of the display screen as a selection signal, and the gradation multiplexer unit 1
The gradation data supplied from 64-167 are selected. Gradation multiplexer 164, gradation multiplexer 16
The data supplied from 6 is the data thinned out from the gradation table register to be displayed when the odd pixels of the odd line and the even line of the display screen are displayed.

The data supplied from the gradation multiplexer unit 165 and the gradation multiplexer unit 167 is the data thinned out from the gradation table register to be displayed at the time of the even pixel of each of the odd line and the even line of the display screen.

The line thinning unit 168 selects the data to be displayed when there are odd pixels on the display screen. Line thinning section 1
69 selects data to be displayed when there are even pixels on the display screen. The selected data is 1-bit wide data and is composed of one 2-to-1 multiplexer.

The pixel thinning unit 170 uses the odd / even pixel discrimination signal for discriminating between the odd pixel and the even pixel of the display screen as a selection signal, and supplies the odd pixel display data supplied from the line thinning unit 168 and the line thinning unit 169. The display data of 1-bit width is selected from the even pixel display data. The selected display data is 1-bit width data and is composed of one 2: 1 multiplexer.

The data read from the VRAM 101 is held in the latch 102, the latch 103, and the latch 104 for each plane. Latch 102, Latch 10
3, the data of each plane held in the latch 104,
Grayscale data 124 having a data structure in which the plane 3 data 120 is the highest level and the plane 1 data 122 is the lowest level
Is converted by the gradation data generation unit 105. The converted gradation data 124 is output to the thinning unit 110.

The thinning-out portion 110 distinguishes between the 3-bit width gradation data 124 and the odd-numbered pixels / even-numbered pixels of the 1-bit width display screen output from the thinning-out control portion 108.
Even pixel discrimination signal, odd / even line discrimination signal for discriminating odd line and even line of 1-bit width display screen, and 5-bit data of frame number of 3-bit width, and control output from display control unit 107 A signal is input. The thinning unit 110 thins out the display data having a 1-bit width as described above. The display data is held in the display data latch unit 111 and output to the liquid crystal display device 112 in accordance with the display timing controlled by the display control unit 107.

As shown in FIG. 10A, the data structure of the gradation table registers 140 to 143 is a table of 8 gradations and 8 bits wide. Display data is stored in F10 to F87. Frame thinning unit 160-163
The data of the gradation table registers 140 to 143 is thinned out by the frame, and the gradation multiplexer unit 164.
In ˜167, the gradation data of the gradation data is selected from the data supplied from the frame decimating units 160 to 163 and output to the line decimating units 168 to 169.
When the frame number is 1, frame thinning is performed and the data structure selected from the gradation table register is shown in FIG.
It is shown in 0 (b). For example, when the grayscale data is 3, the data selected by the grayscale multiplexer units 164 to 167 is the data stored in F31.

[0025]

In the above-described conventional grayscale data generation circuit, when grayscale data is displayed on the screen of the liquid crystal display device, in order to reduce flicker and flicker, an odd number pixel and an even number pixel are used. It is necessary to control the ON / OFF of the pixels of the liquid crystal display device by recognizing the display positions and frame numbers of the odd and even lines. In addition, in order to reduce flicker and flicker of the display screen, ON / O of the pixels of the liquid crystal display device
It becomes necessary to configure the FF by a software rewritable register. Therefore, there is a problem that the circuit scale of the register that stores the display data and the circuit scale of the circuit that generates the display data become large.

Therefore, in order to solve the problem that the circuit scale becomes large, the present invention reduces the circuit scale by using the same register for the odd-numbered pixel and the even-numbered pixel of the display screen for selecting the register according to the display position. The purpose is to

[0027]

A gradation data generation circuit of the present invention which solves the above-mentioned conventional problems includes a register which is connected to a CPU bus and can rewrite an arbitrary value, and a VR.
A grayscale data generation unit that converts grayscale data from bit data read from AM; a thinning unit that selects the register using the grayscale data converted from the bit data as a selection signal; and an odd pixel on the display screen. The register includes a decoding unit that generates a thinning signal that combines a discrimination signal that discriminates an even pixel and a frame number, stores a table of display data that is displayed by the odd pixel and the even pixel of the display screen in the register, and stores the odd pixel of the display screen. And a thinning signal that combines the frame number and the discrimination signal for discriminating even pixels,
A circuit is provided which selects the same register for odd-numbered pixels and even-numbered pixels on the display screen and performs thinning-out to generate display data having gradation.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A gradation data generation circuit according to an embodiment of the present invention is
As shown in FIG. 1, the VRAM 1, the latch 2, the latch 3,
Latch 4, gradation data generation unit 5, address generation unit 6, display control unit 7, thinning control unit 8, gradation table register unit 9, thinning unit 10, display data latch unit 11, liquid crystal display device 12, decoding unit 13 It is composed of.

In the VRAM 1, weighted data is divided and stored for each plane. Plane 3 latch 2, plane 2 latch 3, plane 1 latch 4
Holds the data read from the VRAM 1. The gradation data generation unit 5 generates gradation data from the data held in the latch for each plane.

The address generator 6 generates a read address for the VRAM 1. The display control unit 7 reads the VRAM and controls the liquid crystal display device 12. The thinning-out control unit 8 outputs a control signal such as a discrimination signal for discriminating between odd-numbered pixels and even-numbered pixels of the display pixels to be thinned out and frame numbers.

The gradation table register section 9 includes a thinning section 1
It is a register that stores data to be thinned out at 0. The thinning unit 10 thins the display data output to the liquid crystal display device 12 from the data supplied from the gradation table register unit 9.
The display data latch unit 11 holds the display data supplied from the thinning unit 10 and outputs the data to the liquid crystal display device 12 at the timing of the control signal supplied from the display control unit 7. The liquid crystal display device 12 turns ON / OFF the display pixels of the liquid crystal panel at the timing of the control signal supplied from the display control unit 7 for the input display data. The decoding unit 13 decodes the frame number supplied from the thinning-out control unit 8 and a discrimination signal for discriminating between an odd pixel and an even pixel of the display screen.

As shown in FIG. 2, the gradation table register unit 9 and the thinning-out unit 10 have a gradation table register 40.
To 41, gradation multiplexer units 60 to 61, frame +
The pixel thinning units 62 to 63 and the line thinning unit 64 are included.

The data structure of the gradation table registers 40 to 41 has a width of 8 gradations × 16 bits, and the gradation table register 40 is a register in which a gradation table in which display pixels are odd lines is stored. The gradation table register 41 is a register that stores a gradation table in which display pixels are even lines. A signal for writing data to this register is supplied from the CPU.

The gradation multiplexers 60 to 61 are provided with 8 gradations and 1 supplied from the gradation table registers 40 to 41, respectively.
A gradation table of the same gradation is selected by using gradation data as a selection signal from a 6-bit width register. The selected gradation table is 16-bit width data of 1 gradation × 16 frames, and the gradation multiplexer units 60 to 61 are each composed of a 16to1 multiplexer.

The frame + pixel thinning-out parts 62 to 63 are provided with one gradation x supplied from the gradation multiplexer parts 60 to 61.
The gradation table of the input frame number is selected by using the frame number as a selection signal from the gradation table of 16-bit width. The selected gradation table is data of 1-bit width for each of the odd-numbered pixel and the even-numbered pixel of the display screen, and the frame + pixel thinning units 62 to 63 are respectively 8 to 1
It is composed of two multiplexers.

The line thinning unit 64 determines the odd and even lines of the display screen from the 1-gradation, 2-bit width data supplied from the frame + pixel thinning units 62 to 63, and a display signal of the display screen. The display data is selected using the discrimination signal for discriminating the odd-numbered pixel and the even-numbered pixel as the selection signal. The data supplied from the frame + pixel thinning-out unit 62 is the data to be displayed on the odd lines of the display screen.
The data supplied from the frame + pixel thinning unit 63 is
This is the data that is displayed when there are even lines on the display screen. The selected display data is 1-bit wide data and is 4t.
It is composed of one multiplexer of o1.

FIG. 3 shows another embodiment of the present invention.
The gradation table register unit 9 and the thinning-out unit 10. The configuration of the present invention is equivalent to the gradation table registers 50-5.
1, the gradation multiplexer units 80 to 81, the frame / pixel thinning units 82 to 83, and the line thinning unit 84.

The data structure of the gradation table registers 50 to 51 is 8 gradations × 8 bits in width, and the gradation table register 50 is a register in which a gradation table of display lines of odd lines is stored. Gradation table register 5
Reference numeral 1 is a register in which a gradation table in which display pixels are even lines is stored. A signal for writing data to this register is supplied from the CPU.

The gradation multiplexers 80 to 81 are 8 gradations × 8 supplied from the gradation table registers 50 to 51.
Gradation data from a bit width register as a selection signal,
Select the gradation table of the same gradation. The selected gradation table is 1 gradation × 8 frames of 8-bit width data, and the gradation multiplexer units 80 to 81 are each composed of an 8-to-1 multiplexer.

The frame / pixel decimation units 82 to 83 are provided with 1 gray scale supplied from the gray scale multiplexers 80 to 81.
Using the frame number as a selection signal from the 8-bit width gradation table, the gradation table of the input frame number is selected. The selected gradation table is data of 1-bit width for each of odd-numbered pixels and even-numbered pixels of the display screen, and each of the frame + pixel thinning units 82 to 83 is composed of one 8-to-1 multiplexer.

The run-in thinning-out unit 84 judges the odd-numbered line and the even-numbered line of the display screen from the 1-gradation, 2-bit width data supplied from the frame / pixel thinning-out units 82 to 83, and the display screen. The display data is selected using the discrimination signal for discriminating the odd-numbered pixel and the even-numbered pixel as the selection signal. The data supplied from the frame / pixel thinning-out unit 82 is the data to be displayed when the odd-numbered lines on the display screen.
The data supplied from the frame / pixel thinning unit 83 is
This is the data that is displayed when there are even lines on the display screen. The selected display data is 1-bit width data and is composed of one 2: 1 multiplexer.

The signal output from the decoding unit 13 is the exclusive OR of the most significant bit of the frame number supplied from the thinning control unit 8 and the discrimination signal for discriminating between the odd pixel and the even pixel of the display screen. As shown in FIG. 4, the truth table of the signals output from the decoding unit 13 outputs the same signal as the frame number in the case of odd-numbered pixels on the display screen, and outputs 8 in frame 0 in the case of even-numbered pixels on the display screen. , 9 in frame 1, ..., 7 in frame 15. Since the selection signals for thinning out are different depending on the odd-numbered pixels and the even-numbered pixels on the display screen, even when the same gradation display data is selected by the gradation table register having the same register configuration, the display positions are different and ON / OFF
Is not done.

The data read from the VRAM 1 is held in the latch 2, the latch 3 and the latch 4 for each plane. The data of each plane held in the latch 2, the latch 3, and the latch 4 is converted by the grayscale data generation unit 5 into grayscale data having a data structure in which the plane 3 data is the highest rank and the plane 1 data is the lowest rank. It The converted gradation data is output to the thinning unit 10. The thinning unit 10 outputs 3-bit width gradation data, an odd / even line discrimination signal for discriminating odd lines and even lines of a 1-bit width display screen output from the thinning control unit 8 and lower 3 bits. A frame number having a bit width, 6 bits of data having a 1-bit width of the most significant bit of the frame number output from the decoding unit 13, and a control signal output from the display control unit 7 are input. The decimation unit 10 decimates the display data of 1-bit width as described above. The display data is held in the display data latch unit 11 and output to the liquid crystal display device 12 according to the display timing controlled by the display control unit 7.

As shown in FIG. 5, the data structure of the gradation table register 40 and the gradation table register 41 is a table of 8 gradations and 16 bits width. Display data is stored in F10 to F8F.

As shown in FIG. 6, the data structure of the gradation table register 50 and the gradation table register 51 is a table of 8 gradations and 8 bits wide. Display data is stored in F10 to F87.

[0046]

As described above in detail, according to the gradation data generating circuit of the present invention, when the bit width of the register for generating display data is equal to or more than the number of gradations, the frame number and the display screen are displayed. It is possible to generate the display data with a small-scale circuit configuration by selecting the gradation table register with the discrimination signal of the odd pixel and the even pixel and generating the display data. In addition, by generating display data from the same gradation table register for odd and even pixels,
Finer display data can be set, and flicker and flicker can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a grayscale data generation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a gradation table register unit 9 and a thinning unit 10 of FIG.

3 is a block diagram showing a configuration of a gradation table register unit 9 and a thinning unit 10 of FIG.

FIG. 4 is a diagram for explaining a selection signal of display data from the gradation table register of FIG.

5 is a data format diagram for explaining a data configuration of a gradation table register 40 and a gradation table register 41 of FIG.

6 is a data format diagram for explaining a data configuration of a gradation table register 50 and a gradation table register 51 of FIG.

FIG. 7 is a block diagram showing a configuration of a conventional grayscale data generation circuit.

8 is a block diagram showing a configuration of a gradation table register 109 and a thinning-out unit 110 of FIG.

FIG. 9 is a diagram showing a structure of gradation display and display data.

10 is a gradation table register 140-143 of FIG.
Data structure and frame thinning units 160-1 in FIG.
FIG. 6 is a data format diagram for explaining a configuration of data input to 64.

[Explanation of symbols]

 1 VRAM 2-4 Latch 5 Gradation data generation section 6 Address generation section 7 Display control section 8 Decimation control section 9 Gradation table register section 10 Decimation section 11 Display data latch section 12 Liquid crystal display device 13 Decoding section 40-41 Gradation Table register 60 to 61 Grayscale multiplexer unit 62 to 63 Frame / pixel thinning unit 64 Line thinning unit 50 to 51 Grayscale table register 80 to 81 Grayscale multiplexer unit 82 to 83 Frame + pixel thinning unit 84 Line thinning unit 101 VRAM 102 -10 3 latch 105 grayscale data generation unit 106 address generation unit 107 display control unit 108 thinning control unit 109 grayscale table register 110 thinning unit 111 display data latch unit 112 liquid crystal display device 140 to 143 grayscale table register Star 160-163 frame thinning unit 164 to 167 gradation multiplexer 168-169 line thinning section 170 pixel thinning unit

Claims (1)

[Claims] 1. An apparatus for storing weighted bit data for gradation display in a VRAM, reading out the stored data, thinning out the data, and outputting the data to a liquid crystal display device for display. A latch for holding the data read from the stored VRAM, a grayscale data generation unit for generating grayscale data from the weighted bit data held in the latch, and an arbitrary grayscale display connected to the CPU bus are provided. A register that can write a table value for performing the gradation data, the gradation number, a frame number for performing frame thinning, a signal obtained by decoding a signal that distinguishes an odd pixel and an even pixel of the display screen as a selection signal, and The thinning unit for thinning the display data from the register and the output from the thinning unit. A display data latch unit for holding display data, a control unit for controlling the display data latch unit and the liquid crystal display device, and connected to the CPU bus from the same register for odd and even pixels of the display screen. A gradation data generation circuit comprising a circuit for thinning out display data.