JPH07111979B2 - Method for manufacturing field effect transistor - Google Patents
Method for manufacturing field effect transistorInfo
- Publication number
- JPH07111979B2 JPH07111979B2 JP31139386A JP31139386A JPH07111979B2 JP H07111979 B2 JPH07111979 B2 JP H07111979B2 JP 31139386 A JP31139386 A JP 31139386A JP 31139386 A JP31139386 A JP 31139386A JP H07111979 B2 JPH07111979 B2 JP H07111979B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- insulating film
- effect transistor
- field effect
- transistor according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は電界効果トランジスタ（FET）の製造方法に関
するものである。TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor (FET).
従来の技術 従来、電極間分離膜や層間絶縁膜に用いられている膜
は、堆積中に膜質を変えて堆積しない。2. Description of the Related Art Conventionally, the films used for the electrode separation film and the interlayer insulating film are not deposited by changing the film quality during the deposition.
発明が解決しようとする問題点 従来の方法では、膜の熱膨張係数と基板のそれが相異な
るため、基板表面附近にストレスがはいり、製造工程中
クラックの発生や基板上の各素子に悪影響を及ぼすとい
う問題点がある。Problems to be Solved by the Invention In the conventional method, since the coefficient of thermal expansion of the film and that of the substrate are different from each other, stress is applied near the surface of the substrate, which may cause cracks during the manufacturing process or adversely affect each element on the substrate. There is a problem of exerting it.
問題点を解決するための手段 本発明は、これらの問題から、膜堆積中に基板界面から
表面に向って膜質を変化させることにより、基板界面の
ストレスを緩和するものである。Means for Solving the Problems In view of these problems, the present invention reduces the stress at the substrate interface by changing the film quality from the substrate interface toward the surface during film deposition.
作用 本発明の半導体装置の製造方法により、基板と絶縁膜と
の密着が強くなり、基板表面附近のストレスが緩和さ
れ、クラックの発生がなくなり、ウエハ面内の素子特性
の均一性が高まり、半導体装置の歩留りが向上する。By the method for manufacturing a semiconductor device of the present invention, the adhesion between the substrate and the insulating film is strengthened, stress near the surface of the substrate is relieved, cracks are eliminated, and the uniformity of the device characteristics in the wafer surface is increased. The device yield is improved.
実 施 例 以下本発明の一実施例を説明する。Example An example of the present invention will be described below.
第１図は、GaAs電界効果トランジスタ（GaAs FET）の製
造工程図である。第１図ａにおいてGaAs半絶縁性基板の
表面にフォトリソ技術とイオン注入技術を用い、イオン
注入層２を形成する。第１図ｂにおいてGaAs基板表面上
にPCVD−SiN膜３を堆積する。第１図ｃにおいて、ソー
ス・ドレインのオーミック電極4,ゲート電極５を形成
し、FETが完成する。FIG. 1 is a manufacturing process diagram of a GaAs field effect transistor (GaAs FET). In FIG. 1A, the ion implantation layer 2 is formed on the surface of the GaAs semi-insulating substrate by using the photolithography technique and the ion implantation technique. In FIG. 1b, a PCVD-SiN film 3 is deposited on the surface of the GaAs substrate. In FIG. 1c, the source / drain ohmic electrode 4 and the gate electrode 5 are formed to complete the FET.
従来PCVD−SiN膜３の膜質はSi/N＝0.7〜0.75で膜厚に対
してほぼ一定である。The film quality of the conventional PCVD-SiN film 3 is Si / N = 0.7 to 0.75 and is almost constant with respect to the film thickness.
本発明では、この絶縁膜の膜質を膜厚に対して変化させ
ることを特徴としている。The present invention is characterized in that the quality of the insulating film is changed with respect to the film thickness.
第２図は、半絶縁性GaAs基板上にプラズマCVD−SiN膜
（PCVD−SiN膜）を堆積した場合のPCVD−SiN膜中のSi,
N,Oの量の百分率表示した図である。この図は、SiN堆積
に用いられるSiH4,NH3の全流量を10SCCMから100SCCMま
で連続に増加させ、100W,0.3torrで堆積した場合であ
る。堆積膜厚は4200Åで、GaAs基板との界面では比較的
酸素Ｏの量が多く、表面附近では非常にその量は減少し
ている。SiN膜はGaAs基板に対して圧縮応力となりその
量は５×109dyn/cm2である一方酸素量が多い界面附近で
はSi−Ｏ−Ｎ膜であり、この場合GaAs基板に対して２×
109dyn/cm2と小さな引張応力となり、全膜厚では、GaAs
基板に対して応力がほとんどかからないようになる。今
回SiH4,NH3の全流量で行なった場合を述べたが、デポ時
の圧力を高圧から低圧に変化させた場合、プラズマ電界
（パワー）を低電界から高電界に変化させた場合、基板
温度を低温から高温に変化させた場合も同様、絶縁膜の
堆積速度が〜100Å/minから〜500Å/minの変化であれ
ば、堆積した絶縁膜は、第１図に示す絶縁膜が形成され
る。FIG. 2 shows Si in a PCVD-SiN film when a plasma CVD-SiN film (PCVD-SiN film) is deposited on a semi-insulating GaAs substrate.
It is the figure which expressed the percentage of the quantity of N and O. This figure shows the case where the total flow rate of SiH 4 and NH 3 used for SiN deposition is continuously increased from 10 SCCM to 100 SCCM and deposited at 100 W and 0.3 torr. The deposited film thickness is 4200Å, the amount of oxygen O is relatively large at the interface with the GaAs substrate, and the amount is very small near the surface. The SiN film has a compressive stress on the GaAs substrate and its amount is 5 × 10 9 dyn / cm 2 , while it is a Si—O—N film near the interface with a large amount of oxygen, and in this case it is 2 × on the GaAs substrate.
Tensile stress as small as 10 9 dyn / cm 2
Almost no stress is applied to the substrate. This time, we described the case where the total flow rate of SiH 4 and NH 3 was used. However, when the pressure during deposition was changed from high pressure to low pressure, when the plasma electric field (power) was changed from low electric field to high electric field, the substrate Similarly when the temperature is changed from low temperature to high temperature, if the deposition rate of the insulating film changes from ~ 100 Å / min to ~ 500 Å / min, the deposited insulating film will be the one shown in Fig. 1. It
第３図は、SiN膜による基板のそり（たわみ）を２イン
チウエハの中心を基準にして表わした図である。第２図
より、従来のPCVD−SiN膜の場合に比べ本発明の実施例
の場合の方が、そりが小さいことがわかる。従来のそり
は、半導体装置を製造する上で、フォトリソグラフィー
による不均一性を生み、半導体装置の歩留りを悪化させ
る。このため基板のたわみはできるだけ少ない方がよ
い。FIG. 3 is a view showing the warp (deflection) of the substrate due to the SiN film with reference to the center of the 2-inch wafer. From FIG. 2, it can be seen that the warpage is smaller in the example of the present invention than in the case of the conventional PCVD-SiN film. The conventional warpage causes non-uniformity due to photolithography in manufacturing a semiconductor device and deteriorates the yield of the semiconductor device. Therefore, it is preferable that the deflection of the substrate is as small as possible.
第４図は、SiN膜による基板上のFETの閾値電圧V+hを２
インチウエハの中心を基準にして表わした図である。第
３図より、従来のPCVD−SiN膜の場合に比べ本発明の実
施例の場合の方が、V+hの変化は小さいことがわかる。Fig. 4 shows the threshold voltage V + h of the FET on the substrate made of SiN film as 2
It is the figure expressed on the basis of the center of an inch wafer. From FIG. 3, it can be seen that the change in V + h is smaller in the case of the example of the present invention than in the case of the conventional PCVD-SiN film.
発明の効果 以上のように本発明によれば、基板と絶縁膜との密着が
強くなり、基板表面附近のストレスが緩和され、クラッ
クの発生がなくなり、ウエハ面内の素子特性の均一性が
高まり、半導体装置の歩留りが向上した。EFFECTS OF THE INVENTION As described above, according to the present invention, the adhesion between the substrate and the insulating film is strengthened, the stress near the substrate surface is relieved, the occurrence of cracks is eliminated, and the uniformity of device characteristics within the wafer surface is increased. The yield of semiconductor devices is improved.
第１図は本発明の一実施例における電界効果トランジス
タの製造工程を示す断面図、第２図は半絶縁性GaAs基板
上にプラズマCVD−SiN膜（PCVD−SiN膜）を堆積した場
合のPCVD−SiN膜中のSi,N,Oの量を百分率表示した特性
図、第３図はSiN膜により基板のそり（たわみ）を表わ
した特性図、第４図はSiN膜による基板上のFETの閾値電
圧V+hの分布を表わした特性図である。 １……GaAs半絶縁性基板、２……イオン注入層、３……
SiN絶縁膜、4,5……電極。FIG. 1 is a sectional view showing a manufacturing process of a field effect transistor according to an embodiment of the present invention, and FIG. 2 is a PCVD when a plasma CVD-SiN film (PCVD-SiN film) is deposited on a semi-insulating GaAs substrate. -Characteristics showing the amount of Si, N, O in the SiN film as a percentage, Fig. 3 shows the warp (deflection) of the substrate due to the SiN film, and Fig. 4 shows the FET on the substrate due to the SiN film. It is a characteristic view showing distribution of threshold voltage V + h . 1 ... GaAs semi-insulating substrate, 2 ... ion-implanted layer, 3 ...
SiN insulation film, 4, 5 ... Electrodes.
Claims (6)
体層を形成する工程と、前記第１の半導体層をはさんで
前記第１の半導体と同一導電型の高濃度の第２の半導体
層を形成する工程と、前記第1,第２の半導体層表面に被
着条件を連続的に変化させた絶縁膜を被着させる工程
と、ゲート部にショットキ電極を、ソースドレイン部に
オーミック電極を形成する工程とを含んでなる電界効果
トランジスタの製造方法。1. A step of forming a first-conductivity-type first semiconductor layer on a main surface of a semiconductor, and a high-concentration conductivity type having the same conductivity type as that of the first semiconductor with the first semiconductor layer interposed therebetween. A step of forming a second semiconductor layer, a step of depositing an insulating film on the surfaces of the first and second semiconductor layers, the deposition conditions being continuously changed, a Schottky electrode in the gate part, a source drain And a step of forming an ohmic electrode in the region.
を高圧から低圧に連続的に減圧する特許請求の範囲第１
項記載の電界効果トランジスタの製造方法。2. The pressure of the gas in one atmosphere at the time of forming the insulating film is continuously reduced from a high pressure to a low pressure.
A method for manufacturing a field effect transistor according to the item.
電界から高電界に連続的にパワーを上昇させる特許請求
の範囲第１項記載の電界効果トランジスタの製造方法。3. The method for producing a field effect transistor according to claim 1, wherein the power of the plasma electric field at the time of forming the insulating film is continuously increased from a low electric field to a high electric field.
加させる特許請求の範囲第１項記載の電界効果トランジ
スタの製造方法。4. The method for manufacturing a field effect transistor according to claim 1, wherein the total flow rate of gas at the time of forming the insulating film is continuously increased.
に高くする特許請求の範囲第１項記載の電界効果トラン
ジスタの製造方法。5. The method for manufacturing a field effect transistor according to claim 1, wherein the substrate temperature at the time of forming the insulating film is continuously increased from a low temperature.
minから〜500Å/minまで連続的に速くする特許請求の範
囲第１項記載の電界効果トランジスタの製造方法。6. An insulating film deposition rate at the time of forming an insulating film is about 100Å /
The method for producing a field effect transistor according to claim 1, wherein the speed is continuously increased from min to 500 Å / min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31139386A JPH07111979B2 (en) | 1986-12-25 | 1986-12-25 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31139386A JPH07111979B2 (en) | 1986-12-25 | 1986-12-25 | Method for manufacturing field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63161625A JPS63161625A (en) | 1988-07-05 |
| JPH07111979B2 true JPH07111979B2 (en) | 1995-11-29 |
Family
ID=18016644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31139386A Expired - Fee Related JPH07111979B2 (en) | 1986-12-25 | 1986-12-25 | Method for manufacturing field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07111979B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248179A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Semiconductor device |
| WO2007091301A1 (en) * | 2006-02-07 | 2007-08-16 | Fujitsu Limited | Semiconductor device and process for producing the same |
| JP5433922B2 (en) * | 2006-05-17 | 2014-03-05 | 富士通株式会社 | Compound semiconductor device |
-
1986
- 1986-12-25 JP JP31139386A patent/JPH07111979B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63161625A (en) | 1988-07-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |