JPH07111253A - Silicide forming method and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a tungsten silicide film having a uniform composition on a polycrystalline silicon film by a method wherein initial nuclei are formed while the pressure in a reaction chamber is set to a relatively high value and the surface of a formed film is kept clean and a film is formed while the pressure in the reaction chamber is set to a relatively low value. CONSTITUTION:After the heating of a wafer 12 is finished, the pressure in a reaction chamber 11 is set to 950mTorr and a required quantity of SiH2Cl2 gas which is one of reactive gases is supplied into the reaction chamber 11 and then a required quantity of WF6 gas which is the other reactive gas is supplied to form initial nuclei. After that, a very thin film 6 is formed. Then the supply of the gases is stopped and the reaction chamber 11 is evacuated and the surface of the very thin film 6 is cleaned. Then a pressure in the reaction chamber 11 is reset to a normal value of 150mTorr and the SiH2Cl2 gas which is one of the reactive gases is supplied into the reaction chamber 11 and, after an elapse of time for stabilizing conditions in the reaction chamber 11, the WF6 gas which is another reactive gas is supplied. As a result, a WSi2 film 3 having a uniform composition can be formed on a polycrystalline silicon film 1.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to chemical vapor deposition (CVD).
The present invention relates to a silicide forming method for forming a silicide film by a method and a semiconductor device manufacturing method using the forming method, and more particularly to a technique effectively applied to form a tungsten silicide film on a polysilicon film.

[0002]

2. Description of the Related Art In semiconductor devices such as ICs (integrated circuit devices) and LSIs (large-scale integrated circuit devices), wiring has become finer and its resistance has been reduced due to higher performance and higher speed. For example, "Monthly Semiconductor World" published by Press Journal, Inc.
September 1985 issue, issued August 15, the same year, P83 to P87, C
The VD method is described.

"Electronic Materials" issued by the Industrial Research Society, March 1989 issue, issued March 1, 1989, P53 to P56 describe "single-wafer metal CVD apparatus". In this document,
A process for forming WSi (tungsten silicide) using dichlorosilane (SiH ₂ Cl ₂ ) and tungsten hexafluoride (WF ₆ ) is disclosed. In addition, in this document, "Tungsten silicide process
The growth rate increases rapidly with temperature up to 00 ° C, and only slightly increases above this temperature. Therefore, for high throughput, good uniformity, and good reproducibility,
It is desirable to form a film at 500 ° C. or higher. The surface reaction controls the growth rate below 500 ° C.
Above ℃, the diffusion reaction controls the growth rate. In the diffusion reaction state, the growth rate is independent of the total pressure, proportional to the square root of the total gas flow rate, and proportional to the molar ratio of WF ₆ .
The Si / W composition ratio in the film depends on the temperature, pressure, SiH ₂ Cl ₂ : W
It increases with an increase in the ratio of F ₆ , but decreases with an increase in the total gas flow rate. The Si: W composition ratio has a correlation between the specific resistance and the measured sheet resistance. Is stated. " Also,
CVD apparatus according to this document, WSi by the third step as the first step as a countermeasure processing to natural oxide film (α-Si), a second step of a nucleation (WSi _x), deposition (WSi _{x) The} formation of _x and the deposition conditions are as follows: film formation temperature is 450 to 650 ° C., pressure is 150 mTorr or less, SiH ₂
The Cl ₂ / WF ₆ ratio is stated to be 32.

On the other hand, as a semiconductor device, a DRAM (Dynamic Random Access Memory) which is a volatile semiconductor memory device is used.
y) is known. A memory cell, which is a storage element of a DRAM, is composed of a series circuit of a memory cell selection MISFET and an information storage capacitive element. In the technical field of DRAM, high integration is being promoted, and memory cells are being reduced year by year. In a highly integrated memory cell, a MISFE for selecting a memory cell is formed on a minute plane.
T and the information storage capacitive element must be formed, but in that case as well, in order to prevent the operating speed from decreasing, it is necessary to reduce the resistance of the internal wiring connecting each element.

As a semiconductor device, an ultra high speed bipolar LSI is known. The ultra-high-speed bipolar LSI is described in "Electronic Materials", January 1985 issue, published by the Industrial Research Group, and P49-P55, January 1, 1985. This document describes SST (Super Self-align Process Technology).
Illustrates an npn transistor and manufacturing process. In manufacturing the npn transistor, the same reference is cited as follows: "The most important parts of the transistor, both the base and emitter regions, the base p + polysilicon electrode part, and the emitter contact part are all formed in one photoetching step. Therefore, it is not necessary to incorporate the alignment error between the photomasks (4 sheets) in the conventional planar structure in design, and a fine transistor can be easily manufactured with good controllability. The parasitic capacitance and parasitic resistance that hinder the high-speed operation of the transistor such as junction capacitance and base resistance are reduced, and the transistor becomes faster, and the emitter and base electrodes are made of polysilicon, and this is used as an impurity source. Reliable because the emitter and base compensation regions are formed It is possible to form a high shallow junction, it is possible to increase the cut-off frequency f _T. Shows the observation results of SEM of the cross section of the prototype npn transistor photograph 1. Emitter width 0.35 .mu.m, base contact width 0.35 .mu.m, The distance between the emitter and the base contact is 0.3 μm, and the dimension close to the quarter micron is easily realized with good controllability by using the ordinary light exposure technique.The width of the base region is about 1.7 to 1 for the double base. .8 μm, which is extremely small compared to the emitter width of the conventional planar structure. ”

[0006]

In order to manufacture a more miniaturized and complicated semiconductor device (semiconductor device),
Reducing the resistance value of miniaturized wiring has become an important issue. Therefore, as described in the above-mentioned document, it has become common to use a two-layer film structure (polycide structure) in which a silicide film is formed on an impurity-containing polysilicon film, as the wiring material of the gate electrode. As a result, the wiring resistance value is significantly reduced.
As a method of forming tungsten silicide (WSi ₂ ), the CVD method is adopted as described in the above-mentioned document. In conventional WSi ₂ formation,
It is formed under a constant pressure (150 mTorr or less).

By the way, in the present applicant, DRAM
As a gate electrode and a wiring, a tungsten silicide (WSi ₂ ) is formed on a polysilicon film containing impurities to form a low resistance wiring (electrode). If WSi ₂ is formed on the silicon film under constant pressure (150 mTorr), WS
It was found that the composition of i ₂ was not uniform near the interface of the polysilicon film. That is, in the vicinity of the interface with the polysilicon film, the composition ratio of silicon in WSi ₂ is lowered and the composition is not uniform. Such non-uniformity of composition causes non-uniformity of the progress rate of etching when etching is performed in a later step, which deteriorates etching characteristics such as etching residue, which is not preferable in manufacturing an element.

In addition, the applicant of the present invention needs to form an equivalent film on the polysilicon film containing the p + impurity (p + polysilicon film). Therefore, the inventor formed WSi ₂ on the p + polysilicon film under a constant pressure (150 mTorr) by the conventional CVD method. However, when WSi ₂ is formed on the p + polysilicon film,
It was found that unevenness occurs on the surface of WSi ₂ . That is, as shown in FIG. 7, when the WSi ₂ film 3 is formed on the n + polysilicon film 1 and the p + polysilicon film 2, the surface of the WSi ₂ film 3 on the n + polysilicon film 1 becomes smooth, The surface of the WSi ₂ film 3 on the p + polysilicon film 2 becomes an uneven surface 4 with grain size. This uneven surface is not preferable from the viewpoint of device production, for example, it may prevent fine etching when patterning the WSi ₂ film 3 from being favorably performed.

An object of the present invention is to provide a technique capable of forming a tungsten silicide film having a uniform composition on a polysilicon film.

Another object of the present invention is to provide a technique capable of forming a tungsten silicide film having a smooth surface on a p + polysilicon film. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0011]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, in the method of forming the tungsten silicide film on the polysilicon film in the semiconductor device manufacturing, the reaction chamber of the CVD device is set to a relatively high pressure (about 950 mTorr) at the start of the tungsten silicide film formation. A step (first step) in which SiH ₂ Cl ₂ and WF ₆ as reaction gases are caused to flow in a state in which WF ₆ is reduced to form initial nuclei on the polysilicon film, and the reaction chamber is in a high vacuum state (several meters).
(Around Torr) and exhausting the reaction gas to keep the surface of the formed film (ultra-thin film) clean, and flowing the reaction gas with the reaction chamber set to a relatively low pressure (about 150 mTorr). Forming process (second step)
A tungsten silicide film is formed on the polysilicon film by.

[0012]

According to the above-mentioned means, in the method for forming tungsten silicide of the present invention, WSi ₂ is formed on the polysilicon film with the vacuum degree in the reaction chamber set to a high pressure of about 950 mTorr at the start of film formation. However, since the pressure is increased, the WSi ₂ molecules generated by the reaction are formed above the surface of the wafer and descend and accumulate on the surface of the wafer to form an extremely thin film by the initial nuclei. An ultrathin film having a uniform composition and a uniform thickness is formed without being affected by the polysilicon film). Further, after being very thin film formation, for forming a WSi ₂ is switched to forming conditions substantially normal WSi _2, the surface will be flat desired WSi ₂ film is formed on the electrode film . In the present invention, the first
Since the amount of WF ₆ with respect to SiH ₂ Cl ₂ is reduced in the step, it becomes possible to form a film having the same quality as that of the WSi ₂ film formed in the second step. Further, in the present invention, between the first step and the second step, since the step of cleaning the surface of the formed film by stopping the supply of the reaction gas and flowing only the carrier gas is provided, A good quality film can be formed in the second step.

[0013]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to a wiring connecting each element of DRAM and a gate electrode of MISFET. FIG. 8 shows a cross-sectional view of a main part of a DRAM memory cell.

As shown in FIG. 8, the DRAM of the present invention is formed on the surface of a p-type semiconductor substrate 40 made of single crystal silicon. The p-type semiconductor substrate 40 is a LOCOS (Local Oxidat).
Each element formation region is separated by the field oxide film 61 by selective oxidation by the ion of silicon method. The memory cell is composed of a series circuit of a memory cell selecting MISFET formed on the surface of the p-type semiconductor substrate 40 and an information storage capacitive element.

The memory cell selecting MISFET has a gate electrode 36 formed integrally with the word line 36 on the gate insulating film 35, and an n-type semiconductor region 62 formed in self alignment with the gate electrode 36. . The n-type semiconductor region 62 is a source region of a memory cell selecting MISFET,
It has one of the functions of the drain region.

The information storage capacitive element is a plate electrode 6 formed on the upper layer of the memory cell selection MISFET via an interlayer insulating film 63 composed of BPSG films 63A and 63B.
4, a node electrode 65 and a dielectric film 66. The node electrode 65 is connected to the n-type semiconductor region 62 of the memory cell selecting MISFET, that is, one of the source region and the drain region, via the first connecting electrode 67 made of a polysilicon layer. The other of the source region and the drain region of the memory cell selection MISFET is connected to the bit line 68 via the second connection electrode 81 made of a polysilicon layer.

A method of manufacturing the memory cell gate electrode 36 of this embodiment will be described below with reference to FIG.

The p-type semiconductor substrate 40 uses the (100) crystal plane as an element formation surface, and selectively oxidizes by the LOCOS (Local Oxidation of Silicon) method to separate each element formation region. First, on the thin thermal oxide film grown on the entire surface of the p-type semiconductor substrate 40, ammonia (N
H ₃ ) and monosilane (SiH ₄ ) are thermally decomposed to grow a nitride film to form a resist pattern on the element formation region, and the nitride film is etched using this resist pattern as a mask to perform the thermal oxidation of the element isolation region. The film and the nitride film are removed. A p + type impurity serving as a channel stopper is ion-implanted using the resist pattern as a mask, and after the resist is removed, a thick field oxide film 61 is formed in the element isolation region by selective oxidation using the nitride film in the element formation region as a mask. In the embodiment, the element forming region of about 1 μm is separated.

After removing the thermal oxide film and the nitride film in the element formation region, a gate insulating film 35 is formed as shown in FIG. 9A. N channel MI for selecting the memory cell
The gate insulating film 35 of the SFET is formed of a silicon oxide film obtained by oxidizing the main surface of the p-type semiconductor region 40 by a thermal oxidation method using a vertical diffusion device provided with a load lock chamber. 8 in this embodiment
Oxygen (7 l / m) and hydrogen (3.5 l / m) are added at 50 ° C. to form a film having a thickness of 9 nm.

The gate electrode 36 is provided for the purpose of increasing the operating speed of the memory cell selecting n-channel MISFET.
It is formed of a laminated film in which a refractory metal silicide film is laminated on a polysilicon film. In this embodiment, the polycide film having the tungsten silicide film 3 formed on the impurity-containing polysilicon film 1 is patterned to form a memory cell selection MISFE.
The gate electrode 36 of T is used.

The impurity-containing polysilicon film 1 is batch-processed by a vertical chemical vapor deposition apparatus provided with a load lock chamber. FIG. 10 is a diagram showing a configuration of a chemical vapor deposition apparatus provided with the load lock chamber. In the figure,
(A) shows the conventional apparatus, (b) shows the apparatus used by the present Example.

The wafer 12 is accommodated in the cassette 69, carried in, and accommodated in the reaction chamber 71 by the transfer machine 70.
72 is a heater for heating.

In the reaction chamber 71, at 540 ° C. in this embodiment,
500 scc of monosilane (SiH ₄ ) at 375 mtorr
12 sccm of m, phosphine (PH ₃ ) is added to form a polysilicon film 1 with a thickness of 100 nm. This state is shown in Figure 9.
(B) of.

The wafer 12 having the polysilicon film 1 formed thereon is housed in the cassette 69 and sent to the tungsten silicide film forming step.

In the conventional apparatus shown in (a), since the wafer 12 is exposed to the atmosphere outside the reaction chamber 71, the surface of the polysilicon film 1 may be oxidized or impurities may be attached to the surface. In the apparatus of this embodiment shown in (b), since the cassette chamber 73 and the load lock chamber 74 are in a nitrogen atmosphere, the above-mentioned oxidation or adhesion of impurities is reduced. Therefore, in the manufacturing method using the conventional apparatus, the cleaning step is performed after the polysilicon film 1 is formed, but in the present embodiment, the cleaning step can be performed without the cleaning step. Is.

Next, the step of forming a silicide will be described. FIG. 1 is a timing chart showing the method of forming a tungsten silicide film according to the present embodiment, FIG. 2 is a schematic view showing the main part of a chemical vapor deposition apparatus for carrying out the method of forming a tungsten silicide of the present invention, and FIG. 3 is a semiconductor in the apparatus. FIG. 4 is a front view showing an essential part of a wafer supporting mechanism, FIG. 4 is a plan view showing an essential part of a semiconductor wafer supporting mechanism, and FIG. 11 is a plan view showing an overall structure of the apparatus.

Before explaining the silicide forming method of the present invention, an outline of a chemical vapor deposition apparatus for carrying out the present invention will be described with reference to FIGS.
In the chemical vapor deposition apparatus of the present embodiment, the wafer 12 accommodated in the cassette 69 is stored in the cassette chamber 7 as shown in FIG.
At 5, the so-called single-wafer processing is performed in which the supporting mechanism 15 pulls the sheets one by one from the cassette 69 and transfers them to the reaction chamber 11 via the transfer chamber 76. Reference numeral 77 is an annealing chamber for performing annealing.

As shown in FIG. 2, a wafer (semiconductor wafer) 12 is provided in a reaction chamber 11 of the CVD apparatus.
A heating susceptor 13 for supporting a sample such as the above is provided. Further, above the heating susceptor 13, a heating body 1 including a lamp for heating the heating susceptor 13 is provided.
4 are provided. The heating susceptor 13 is made of a graphite plate, is heated by the heating body 14, and is controlled to a desired temperature. The wafer 12 is attached to the lower surface of the heating susceptor 13 by the support mechanism 15.
The support mechanism 15, as shown in FIGS. 3 and 4,
A ring body 16 having a diameter larger than that of the wafer 12, and an arm 17 extending in the horizontal direction from the ring body 16;
The arm 17 includes an elevating shaft 19 whose upper end is fixed, and an elevating mechanism (not shown) that moves the elevating shaft 19 up and down. Support pins 20 are attached to the ring body 16 at 120 ° intervals. These support pins 2
0 is arranged so as to be inclined toward the upper center of the ring body 16. The wafer 12 is placed on the tips of the three support pins 20 or is removed from the three support pins 20. After the wafer 12 is loaded onto the three support pins 20, the support mechanism 15 operates and the ring body 16 moves.
Moves up to bring the wafer 12 supported by the support pins 20 into close contact with the lower surface of the heating susceptor 13. Then, in this state, the WSi ₂ film is formed. After the film is formed, the support mechanism 15 operates again, and the ring body 1
6 is lowered to a predetermined height so that the wafer 12 can be carried out of the reaction chamber 11.

On the other hand, a gas injection pipe 25 is provided in the reaction chamber 11 below the heating susceptor 13. The gas injection pipe 25 is composed of a ring-shaped pipe body and has a large number of injection ports (not shown) on the upper surface side, and the gas 26 is injected from the injection port toward the heating susceptor 13. Further, three gas supply pipes 27 are connected to the gas injection pipe 25, and each gas supply pipe 27 is connected to a cylinder 29. The three cylinders 29 are dichlorosilane (SiH ₂ Cl) which is a reaction gas.
₂ ), tungsten hexafluoride (WF ₆ ), and argon (Ar) that is a carrier gas are filled, and the valve 30 is opened and closed to supply and stop. In fact, the on-off valve,
The flow rate control valve etc. are built in and the control with higher accuracy is performed. An exhaust pipe 31 is attached to the reaction chamber 11. The exhaust pipe 31 is connected to a vacuum pump (not shown) so that the inside of the reaction chamber 11 can be controlled to a desired degree of vacuum.

In such a chemical vapor deposition apparatus, the degree of vacuum in the reaction chamber 11, the temperature of the sample attached to the heating susceptor 13, and the supply amounts of various gases can be freely controlled.

In the method for forming a tungsten silicide film according to the present invention, the chemical vapor deposition apparatus is used and WF is used.
₆ + SiH ₂ Cl ₂ -based reaction gas is used to deposit tungsten silicide (WS) on the polysilicon film 1 of the wafer 12.
i ₂ ) is formed. The timing chart for film formation is shown in Figure 1.
It looks like. Processing temperature and carrier gas (A
The supply amount of r) is constant from the beginning to the end of film formation. The processing temperature is, for example, 680 ° C., and the carrier gas is 100 sccm. Further, the film formation reaches the first step which reaches times B to C for forming the initial nuclei and the times E to F for forming the silicide film 8 on the forming film (ultra-thin film) 6 formed by the initial nucleation. And the second step. Further, the supply of the reaction gas is stopped between the first step and the second step, and the pressure is set to several mTo.
A cleaning step of rr is provided.

Next, formation of the WSi ₂ film 3 will be described with reference to the timing chart. At first,
After the semiconductor wafer 12 is loaded into the reaction chamber 11, the wafer 12 is attached to the lower surface of the heating susceptor 13 by the support mechanism 15. Further, a certain amount of Ar gas as a carrier gas, for example, 100 sccm is supplied into the reaction chamber 11, the pressure in the reaction chamber 11 is set to 150 mTorr, and the reaction chamber 11 is heated to a predetermined temperature, for example, 680 ° C. The supply amount of carrier gas and the heating temperature are kept constant until the film formation is completed.

After the heating of the wafer 12, the pressure inside the reaction chamber 11 is set to 950 mTorr and the reaction gas, SiH ₂ Cl ₂ gas, is set to a predetermined amount, for example, 20.
Supply 0 sccm. The SiH ₂ Cl ₂ gas is supplied in the same amount in the first step and the second step. After that, a predetermined amount of WF ₆ gas, which is another reaction gas,
For example, in the first step, 1.2 sccm is supplied, and initial nucleation is performed for a desired time, for example, about 10 seconds to form a forming film (ultra-thin film) 6. The period from time A to time B in the timing chart is the time when the processing conditions for the reaction chamber 11 and the wafer 12 are set. The period from time B to time C is the time devoted to initial nucleation. The first step is narrowly from time B to time C. In the first step, since the pressure in the reaction chamber 11 is high, WSi ₂ is formed at a position apart from the surface of the wafer 12 and accumulates on the surface of the wafer 12, so that the ultrathin film 6 formed by the initial nucleation forms the base material. Not affected by.
The flow of a small amount of WF ₆ , which is the reaction gas, is to form the same quality as the WSi ₂ film 8 formed in the second step. When the pressure is increased, the reaction is accelerated, and the film quality of the WSi ₂ film forming the ultrathin film 6 is different from that of the second step. Therefore, in order to make the film quality consistent, the supply amount of WF ₆ is made small in the first step.

Next, a cleaning step from time C to time D is provided. This cleaning step is performed for about 30 seconds, for example, to stop the supply of the reaction gas,
The inside of the reaction chamber 11 is evacuated to clean the surface of the ultrathin film 6. By cleaning the inside of the reaction chamber 11,
The film is well formed in the next second step.

Next, the pressure in the reaction chamber 11 is set to 15
Reset to 0 mTorr, SiH ₂ C which is one of the reaction gas
Flow ₁₂ (supplied amount is 200 sccm). Also, the reaction chamber 11
When the conditions inside reached a stable time E, WF ₆ as another reaction gas was 2.0 (the first step was 1.2 sc
m) About sccm is supplied. The second step is performed for a time of about 90 seconds, for example. As a result, the WSi ₂ film 3 having a thickness of about 150 nm is formed on the polysilicon film 1.
Will be formed. This state is shown in FIG. 9 (c). In the second step, since the WSi ₂ film is continuously formed on the flat ultrathin films 6 and 7, the surface of the WSi ₂ film 3 becomes flat. In addition, what is shown by (c ') in the figure is a state after the WSi ₂ film 3 is formed by the conventional manufacturing method.

FIG. 12 shows the results of comparing the composition in the depth direction of the polycide film thus formed between the conventional composition method (a) and the composition of this embodiment (b). It is a figure. In the conventional method, the composition of the silicide is changed near the interface between the polysilicon film 1 and the silicide film 3 and the ratio of silicon is reduced as shown by the arrow in the figure. On the other hand, the composition of this example does not show such a change and maintains a uniform composition. It is considered that this is because the silicide is formed without being affected by the underlying material as described above.

The gate electrode 36 is integrally formed and electrically connected to the word line (WL) 36 in the gate width direction (that is, formed of the same conductive layer).

An insulating film 7 is formed on the upper surface of the gate electrode 36.
8 is formed, and similarly, an insulating film 78 is formed on the upper surface of the word line 36. This insulating film 78 serves as the gate electrode 36.
Or a part of the word line 36 is covered.

The insulating film 78 has a dense and high-quality film quality, and is formed of a silicon oxide film deposited by a chemical vapor deposition apparatus provided with a load lock chamber mainly for the purpose of increasing the withstand voltage. It This silicon oxide film uses inorganic silane (monosilane: SiH ₄ ) 10 to 20 sccm and nitric oxide (N ₂ O) 700 sccm as the main source gas.
It is deposited by a low pressure CVD method in which a high temperature of about 00 ° C. and a pressure of about 450 mtorr are set. Insulating film 78 is 200n
It is formed with a film thickness of about m. This state is shown in FIG.

After depositing the insulating film 78, a chemically amplified resist gate is formed in the pattern of the electrode, and this resist 79 is formed.
Using as a mask, dry etching is performed by a microwave plasma etching apparatus to pattern the insulating film 78. In this embodiment, the insulating film 78 is plasma-etched in a halogen compound (CHF ₃ , CH ₂ F ₂ ) atmosphere at a temperature of −10 ° C. and a pressure of 6.5 mtorr using an RF output of 150 w and a microwave of 300 mA. . This state is shown in FIG. When the patterning of the insulating film 78 is completed, the resist 79 is removed, and the silicide film 3 and the polysilicon film 1 are etched using the patterned insulating film 78 as a mask. In this example, a temperature of 0 ° C.,
A gate electrode 36 having a polycide structure is formed by plasma etching using a microwave having an RF output of 35 / 16w and 250 mA in a chlorine (Cl ₂ ) and oxygen (O ₂ ) atmosphere at a pressure of 5 mtorr. The gate length is 0.3 μm.

In this embodiment, since the silicide film 3 having a uniform composition is obtained as described above, the etching characteristics are good.

After patterning the gate electrode 36, the n-type semiconductor region 62 used as either the source region or the drain region is self-aligned with the gate electrode 36 in the main surface portion of the p-type semiconductor substrate 40. It is formed.

The n-type semiconductor region 62 is formed, for example, by using an ion implantation method and introducing phosphorus (P) as an impurity. When introducing P to form the n-type semiconductor region 62, each of the gate electrode 36, the insulating film 78 laminated on the upper surface thereof, and the field oxide film 61 is used as an impurity introduction mask.

Next, sidewall spacers 80 that cover the side surfaces of the gate electrode 36 are formed. The sidewall spacer 80 has a dense and high-quality film quality, and is formed of a silicon oxide film deposited by the CVD method mainly for the purpose of increasing the withstand voltage. This silicon oxide film is deposited by the low pressure CVD method.

As shown in FIG. 8, the information storage capacitive element has a so-called stacked structure in which a node electrode 65, a dielectric film 66, and a plate electrode 64 are sequentially laminated on an upper portion of a memory cell selection n-channel MISFET. Composed of.

The node electrode 65 is electrically connected to one of the n-type semiconductor regions 62 of the memory cell selecting n-channel MISFET, and the peripheral portion thereof is on and above the gate electrode 36 of the memory cell selecting n-channel MISFET. It is stretched on another word line 36 adjacent to and extending to the word line 36 connected to 36. The node electrode 65 is
One of the n holes is formed through the connection hole formed in the interlayer insulating film 63.
It is connected to the type semiconductor region 62.

The node electrode 65 is formed of, for example, a polysilicon film. This polysilicon film is deposited by the CVD method, and an impurity such as an n-type impurity that reduces the resistance value is introduced during or after the deposition. The node electrode 65 corresponds to a storage node region that stores information stored in a memory cell, is arranged for each memory cell, and is formed independently of other adjacent memory cells.

The dielectric film 66 is formed along the top and side surfaces of the node electrode 65. The dielectric film 66 is Ta ₂
It is composed of O ₅ , and is deposited by, for example, the CVD method or the sputtering method.

The plate electrode 64 is formed on the dielectric film 66 and constitutes a node electrode 65 and a capacitor. The plate electrode 64 is integrally formed with and electrically connected to the plate electrode of the information storage capacitive element of this memory cell and the information storage capacitive element of another memory cell arranged adjacent to the periphery thereof. A plate electrode 64 common to a plurality of memory cells arranged in the memory cell array
Configured as.

The plate electrode 64 is formed of, for example, a polysilicon film. This polysilicon film is deposited by the CVD method, and an impurity such as an n-type impurity that reduces the resistance value is introduced during or after the deposition.

N-channel MISFET for memory cell selection
To the other n-type semiconductor region 62 of the complementary bit line (BL)
68 is electrically connected. This complementary bit line 68
Is a BPSG film 63A forming a lower layer of the interlayer insulating film 63.
The second contact hole (bit line contact hole) formed on the BPSG film 16A and extending over the surface of the
The connection electrode 81 of the other n-type semiconductor region 62
Connected to.

The complementary bit line 68 is also formed of a polycide film having the same structure as the gate electrode 36.

The BPSG film 63A and the BPSG film 63B laminated on the BPSG film 63A are formed for the purpose of flattening the surface and improving the step coverage of the complementary bit line 68. The upper BPSG film 63B is short-circuited between the complementary bit lines 68 or adjacent complementary bit lines 68 generated during patterning of the complementary bit lines 68 or the upper wiring thereof (based on the remaining etching mask). It is formed for the purpose of preventing a short circuit between wirings.
For the BPSG films 63A and 63B, for example, SiH ₄ is used as a main source gas, and PH ₃ and B are used as additives.
It is deposited by atmospheric pressure CVD using ₂ H _6, and is subjected to reflow for the purpose of flattening its surface.

(Embodiment 2) FIG. 5 is a schematic view showing a WSi ₂ film on an n + polysilicon film and a p + polysilicon film formed by the method for forming tungsten silicide of the present invention, and FIG. 6 is another embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device manufactured by using the tungsten silicide forming method according to the embodiment.

The outline of the chemical vapor deposition apparatus of this embodiment is the same as that of the above-described first embodiment, and as shown in FIG. 2, a reaction chamber (chamber) 11 of the chemical vapor deposition apparatus is provided. A heating susceptor 13 for supporting a sample such as a wafer (semiconductor wafer) 12 is provided. Further, above the heating susceptor 13, a heating body 14 including a lamp for heating the heating susceptor 13 is provided. The heating susceptor 13 is made of a graphite plate,
It is heated by the heating body 14 and controlled to a desired temperature. The wafer 12 is attached to the lower surface of the heating susceptor 13 by a support mechanism. The support mechanism 15 is shown in FIG.
As also shown in FIG. 4, a ring body 16 having a diameter larger than that of the wafer 12, an arm 17 extending in the horizontal direction from the ring body 16, and an elevating shaft 19 having an upper end fixed to the arm 17. And an elevating mechanism (not shown) for moving the elevating shaft 19 up and down. Support pins 20 are attached to the ring body 16 at 120 ° intervals. These support pins 20 are arranged so as to be inclined upward in the center of the ring body 16. The wafer 12 is
It is placed on the tips of the three support pins 20 or removed from the three support pins 20 by a robot hand (not shown) or the like. After the wafer 12 is loaded onto the three support pins 20, the support mechanism 15 operates and the ring body 16 moves up, so that the wafer 12 supported by the support pins 20 is placed on the lower surface of the heating susceptor 13. In close contact with. Then, in this state, the WSi ₂ film is formed. Further, after the film formation, the support mechanism 15 operates again, the ring body 16 descends to a predetermined height, and the wafer 1
2 is carried out to the outside of the reaction chamber 11.

On the other hand, a gas injection pipe 25 is provided in the reaction chamber 11 below the heating susceptor 13. The gas injection pipe 25 is composed of a ring-shaped pipe body and has a large number of injection ports (not shown) on the upper surface side, and the gas 26 is injected from the injection port toward the heating susceptor 13. Further, three gas supply pipes 27 are connected to the gas injection pipe 25, and each gas supply pipe 27 is connected to a cylinder 29. The three cylinders 29 are dichlorosilane (SiH ₂ Cl) which is a reaction gas.
₂ ), tungsten hexafluoride (WF ₆ ), and argon (Ar) that is a carrier gas are filled, and the valve 30 is opened and closed to supply and stop. In fact, the on-off valve,
The flow rate control valve etc. are built in and the control with higher accuracy is performed. An exhaust pipe 31 is attached to the reaction chamber 11. The exhaust pipe 31 is connected to a vacuum pump (not shown) so that the inside of the reaction chamber 11 can be controlled to a desired degree of vacuum.

In such a chemical vapor deposition apparatus, the degree of vacuum in the reaction chamber 11, the temperature of the sample attached to the heating susceptor 13, and the supply amounts of various gases can be freely controlled.

In the method for forming a tungsten silicide film of the present invention, the chemical vapor deposition apparatus is used and WF is used.
Tungsten silicide (WSi ₂ ) is formed on the polysilicon film of the wafer 12 by the reaction gas of ₆ + SiH ₂ Cl ₂ system.
To form. The timing chart of film formation is as shown in FIG. The processing temperature and the supply amount of the carrier gas (Ar) are constant from the beginning to the end of film formation. The processing temperature is, for example, 680 ° C., and the carrier gas is 100 sccm. Further, the film formation is the first step up to the time B to C for forming the initial nuclei and the second step up to the time E to F for forming the film on the formed film (ultra-thin film) formed by the initial nucleation. Formed by and. Further, between the first step and the second step, there is provided a cleaning step in which the supply of the reaction gas is stopped and the pressure is set to several mTorr.

Next, formation of the WSi ₂ film will be described with reference to the timing chart. First, n
After the semiconductor wafer 12 in which the + + polysilicon film and the p + polysilicon film are mixed is carried into the reaction chamber 11, the wafer 12
Is attached to the lower surface of the heating susceptor 13 by the support mechanism 15. Further, in the reaction chamber 11, A as a carrier gas
A constant amount of r gas, for example, 100 sccm is supplied, the pressure in the reaction chamber 11 is set to 150 mTorr, and the gas is heated to a predetermined temperature, for example, 680 ° C. The supply amount of carrier gas and the heating temperature are kept constant until the film formation is completed.

After the wafer 12 is heated, the pressure inside the reaction chamber 11 is set to 950 mTorr and the reaction gas, SiH ₂ Cl ₂ gas, is set to a predetermined amount, eg, 20.
Supply 0 sccm. The SiH ₂ Cl ₂ gas is supplied in the same amount in the first step and the second step. After that, a predetermined amount of WF ₆ gas, which is another reaction gas,
For example, supply 1.2sccm, desired time, for example about 10
Initial nucleation is performed for a second to form formed films (ultra-thin films) 6 and 7. The period from time A to time B in the timing chart is the time when the processing conditions for the reaction chamber 11 and the wafer 12 are set. The period from time B to time C is the time devoted to initial nucleation. The first step is narrowly from time B to time C. In the first step, since the pressure in the reaction chamber 11 is high, WSi
_{Since 2} is formed at a position distant from the surface of the wafer 12 and accumulates on the surface of the wafer 12, the ultra-thin film formed by the initial nucleation is not affected by the underlying material. Therefore, both the ultrathin film (WSi ₂ film) 6 on the n + polysilicon film 1 and the ultrathin film (WSi ₂ film) 7 on the p + polysilicon film 2 are formed to have flat surfaces and the same quality.

FIG. 5 is a schematic view showing a state in which the WSi ₂ films 2 and 4 are formed on the n + polysilicon film 1 and the p + polysilicon film 2 according to the present invention. The formation films (ultra-thin films) 6 and 7 formed in the first step have flat surfaces both on the p + polysilicon film 2 and on the n + polysilicon film 1. In the same figure, the surfaces of the ultrathin films 6 and 7 are indicated by a chain double-dashed line. In addition, the reaction gas W
To flow a small amount of F _{6 is} to form W in the second step.
This is to form the same quality as the Si ₂ film. When the pressure is increased, the reaction becomes faster and WS that forms ultra-thin films 6 and 7
Since the film quality of the i ₂ film is different from that of the second step, the supply amount of WF ₆ is made small in the first step in order to match the film quality.

Next, a cleaning step from time C to time D is provided. This cleaning step is performed for about 30 seconds, for example, to stop the supply of the reaction gas,
The inside of the reaction chamber 11 is evacuated to clean the surfaces of the ultrathin films 6 and 7. This is to clean the inside of the reaction chamber 11 so that the film formation in the next second step is favorably performed.

Next, the pressure in the reaction chamber 11 is set to 15
Reset to 0 mTorr, SiH ₂ C which is one of the reaction gas
Flow ₁₂ (supplied amount is 200 sccm). Also, the reaction chamber 11
When the conditions inside reached a stable time E, WF ₆ as another reaction gas was 2.0 (the first step was 1.2 sc
m) About sccm is supplied. The second step is performed for a time of about 90 seconds, for example. As a result, the n +
A thickness of 1 on the polysilicon film 1 or p + polysilicon film 2
The WSi ₂ film 3 of about 500 Å will be formed.
In the second step, W
Since the Si ₂ film is formed, the surface of the WSi ₂ film 3 becomes flat.

SST is known as a semiconductor device having a p + polysilicon film. Then, for the purpose of reducing the resistance value of the p + polysilicon film of SST, a semiconductor device was manufactured by applying the tungsten silicide forming method of the present invention. FIG. 6 is a sectional view of the SST. On the main surface of the semiconductor substrate 40 made of p + silicon, an n + island 42 is provided by an isolation insulating film (SiO ₂ film) 41. Further, the collector contact portion 44 and the emitter / base forming region 45 are formed in the n + island 42 by the SiO ₂ film 43 formed at the same time when the insulating film isolation insulating film 41 is formed. An n-type region 46 is formed on the surface layer of the emitter / base formation region 45. This n-type region 46
P-type region 47 is provided in the surface layer part of
The n + polysilicon film 1 is formed on the central surface layer of the mold region 47.
N + region (emitter region) due to diffusion of impurities from 4
9 is provided. The n + polysilicon film 1 serves as an emitter electrode, and serves as the isolation insulating film 41.
On the insulating film (SiO ₂ film) 50, a part of which is placed on the main surface. Then, the p + polysilicon film 2 is provided from the outside of the insulating film 50 to the lower surface. Part of this p + polysilicon film 2 is in contact with the main surface of the semiconductor substrate 40, and part is placed on the insulating film 51. Then, in the surface layer portion of the semiconductor substrate 40 in contact with the p + polysilicon film 2, p
A p + type layer 52 formed by diffusing impurities from the + polysilicon film 2 is formed. This p + type layer 52 becomes a contact region of the base. Further, the p + polysilicon film 2 serves as a base electrode. An n + polysilicon film 1 is formed on the collector contact portion 44. This n + polysilicon film 1 becomes a collector electrode.

A WSi ₂ film 3 is formed on the n + polysilicon film 1 and the p + polysilicon film 2 which will be the emitter / base / collector electrodes for the purpose of reducing the resistance. Therefore, when the WSi ₂ film 3 is formed, the semiconductor substrate 40 is placed in the reaction chamber 11 of the chemical vapor deposition apparatus, and the silicide formation of the present invention including the above-mentioned first step, cleaning step, and second step. The WSi ₂ film 3 is formed by the method. As a result, the n + polysilicon film 1 and the p +
The WSi ₂ film 3 having a flat surface on the surface of which the surface of the polysilicon film 2 is not uneven can be formed. Therefore, fine processing of the WSi ₂ film 3 becomes possible, and
The resistance value of the electrode can also be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of tungsten silicide which is the field of application which is the background has been described, but the invention is not limited thereto. The present invention can be applied to manufacturing techniques of other silicide films such as titanium silicide. Further, the present invention can be applied to the case where the underlying layer is other than polysilicon, for example, a silicide is formed on a single crystal silicon substrate or another conductor or semiconductor. Further, the present invention can be applied to a semiconductor device having other circuit configurations such as a logic circuit and a peripheral circuit of DRAM in addition to the above-mentioned DRAM memory cell and SST, and bipolar, CMOS, Bi.
It can be applied regardless of the element structure such as CMOS.

[0068]

【The invention's effect】

(1) According to the tungsten silicide forming method of the present invention, since the tungsten silicide is formed under the high pressure of the first step, a WSi ₂ film (ultra-thin film) having a flat surface and a uniform surface without being affected by the base is formed. The effect that it can be formed is obtained.

(2) According to the above (1), the tungsten silicide forming method of the present invention has an effect that the composition of the silicide becomes uniform in the vicinity of the interface with the polysilicon.

(3) According to the above (2), the tungsten silicide forming method of the present invention has the effect of improving the polycide etching characteristics.

(4) According to the method (1) above, according to the method for forming a tungsten silicide of the present invention, an extremely thin film having a flat surface and a uniform surface can be formed in the first step. Therefore, a WSi ₂ film is further formed in the second step. When stacked, the effect is obtained that a uniform WSi ₂ film having a flat surface can be formed.

(5) According to the method (1) above, according to the method for forming a tungsten silicide of the present invention, an extremely thin film having a flat surface and a uniform surface can be formed in the first step. Therefore, a WSi ₂ film is further formed in the second step. Even when stacked, a WSi ₂ film having a flat surface and a uniform surface can be formed, so that it is possible to form a thin WSi ₂ film.

(6) According to the method of forming a tungsten silicide of the present invention according to the above (3), WSi ₂ having a flat surface and a uniform surface is formed by the first step and the second step.
Since the film can be formed, there is an effect that fine processing can be performed when the WSi ₂ film is selectively etched and patterned.

(8) Due to the above (5) and (6), according to the present invention, the device pattern can be further miniaturized by forming a thin WSi ₂ film and microfabrication of the WSi ₂ film. The effect that can be achieved is obtained.

(9) According to the present invention, according to the above (1), a WSi ₂ film having a flat surface can be formed on the p + polysilicon film as well as on the n + polysilicon film.
It is possible to obtain the effect that a semiconductor device having a fine pattern with a low wiring (electrode) resistance value can be manufactured.

[Brief description of drawings]

FIG. 1 is a timing chart showing a method of forming a tungsten silicide according to an embodiment of the present invention.

FIG. 2 is a schematic view showing a main part of a chemical vapor deposition apparatus for carrying out the tungsten silicide forming method of the present invention.

FIG. 3 is a front view showing a main part of a semiconductor wafer support mechanism in a chemical vapor deposition apparatus for carrying out the method for forming tungsten silicide of the present invention.

FIG. 4 is a plan view showing an essential part of a semiconductor wafer supporting mechanism in a chemical vapor deposition apparatus for carrying out the method for forming tungsten silicide of the present invention.

FIG. 5 is a schematic view showing a WSi ₂ film on an n + polysilicon film and a p + polysilicon film formed by the method for forming tungsten silicide of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor device which is an embodiment manufactured by using the method for forming tungsten silicide of the present invention.

FIG. 7 is a schematic view showing a WSi ₂ film on an n + polysilicon film and a p + polysilicon film formed by a conventional tungsten silicide forming method.

FIG. 8 is a cross-sectional view of essential parts of a DRAM which is an embodiment of the present invention.

FIG. 9 is a diagram illustrating a gate forming process of a DRAM which is an embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a chemical vapor deposition apparatus for carrying out the polysilicon film forming method of the present invention.

FIG. 11 is a plan view showing the overall configuration of a chemical vapor deposition apparatus for carrying out the tungsten silicide forming method of the present invention.

FIG. 12 is a diagram showing the composition in the depth direction of the polycide film of the present invention.

[Explanation of symbols]

1 ... n + polysilicon film, 2 ... p + polysilicon film, 3
... WSi ₂ film, 4 ... Uneven surface, 6, 7 ... Formed film (ultra-thin film), 11 ... Reaction chamber (chamber), 12 ... Wafer (semiconductor wafer), 13 ... Heating susceptor, 14 ... Heating body, 15
... Support mechanism, 16 ... Ring body, 17 ... Arm, 19 ... Lifting shaft, 20 ... Support pin, 25 ... Gas injection pipe, 26 ... Gas, 27 ... Gas supply pipe, 29 ... Cylinder, 30 ... Valve,
31 ... Exhaust pipe, 35 ... Gate insulating film, 36 ... Gate electrode, 40 ... Semiconductor substrate, 41 ... Isolation insulating film, 42 ... N + island, 43 ... SiO ₂ film, 44 ...
Collector contact part, 45 ... Emitter / base formation region, 46 ... N type region, 47 ... P type region, 49 ... Emitter region (n + region), 50 ... Insulating film, 51 ... Insulating film, 52
... p + type layer, 61 ... field oxide film, 62 ... n type semiconductor region, 63 ... interlayer insulating film, 63A ... BPSG film, 63
B ... BPSG film, 64 ... Plate electrode, 65 ... Node electrode, 66 ... Dielectric film, 67 ... First connection electrode, 68 ...
Bit line, 69 ... Cassette, 70 ... Transfer machine, 71 ... Reaction chamber, 72 ... Heater, 73 ... Cassette chamber, 74 ... Load lock chamber, 75 ... Cassette chamber, 76 ... Transfer chamber, 77
... annealing chamber, 78 ... insulating film, 79 ... resist,
80 ... Spacer, 81 ... Second connection electrode.

Claims (19)

[Claims] 1. A method of forming a silicide film on an impurity-containing polysilicon film by chemical vapor deposition, comprising:
A step of forming initial nuclei in a state where the reaction chamber is set to a relatively high pressure at the start of film formation, and a step of keeping the reaction chamber in a high vacuum state and exhausting a reaction gas to keep the formed film surface clean, And a step of forming a film with the reaction chamber being set to a relatively low pressure. 2. The silicide forming method according to claim 1, wherein the tungsten silicide is formed on the polysilicon film by using a WF ₆ + SiH ₂ Cl ₂ based reaction gas as a reaction gas. 3. A method of manufacturing a semiconductor device, comprising forming a silicide film on a p + polysilicon film, wherein the silicide film is made of tungsten silicide formed by chemical vapor deposition. Silicide has a step of forming initial nuclei in a state where the reaction chamber is set to a relatively high pressure at the start of film formation, and a high vacuum state in the reaction chamber and exhausting reaction gas to keep the surface of the formed film clean. A method of manufacturing a semiconductor device, comprising: forming a film while forming a film in the reaction chamber with a relatively low pressure. 4. A method of manufacturing a semiconductor device using a polycide film in which a silicide film is formed on a polysilicon film, wherein the polycide film is formed by the following steps. . (A) A step of forming the polysilicon film. (B) A step of forming a thin film which becomes an initial nucleus of the silicide while the reaction chamber is set to a relatively high pressure at the start of forming the silicide film. (C) A step of bringing the reaction chamber into a high vacuum state by exhausting the reaction gas to keep the surface of the formed film clean. (D) A step of forming a film of the silicide while the pressure inside the reaction chamber is set to a relatively low pressure. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the silicide is tungsten silicide. 6. A method of manufacturing a semiconductor device using a polycide film in which a tungsten silicide film is formed on an impurity-containing polysilicon film, wherein the polycide film is formed by the following steps. Manufacturing method. (A) A step of forming the impurity-containing polysilicon film. (B) A step of forming a thin film serving as an initial nucleus of the tungsten silicide while the reaction chamber is set to a relatively high pressure at the start of forming the tungsten silicide film. (C) A step of bringing the reaction chamber into a high vacuum state by exhausting the reaction gas to keep the surface of the formed film clean. (D) A step of forming a film of the tungsten silicide while the pressure inside the reaction chamber is set to a relatively low pressure. 7. A method of manufacturing a semiconductor device using a polycide film in which a tungsten silicide film is formed on an impurity-containing polysilicon film, wherein the polycide film is formed by the following steps. Manufacturing method. (A) A step of forming the impurity-containing polysilicon film by a chemical vapor deposition apparatus provided with a load lock chamber. (B) A step of forming a thin film which becomes an initial nucleus of the silicide while the reaction chamber is set to a relatively high pressure at the start of forming the silicide film. (C) A step of bringing the reaction chamber into a high vacuum state by exhausting the reaction gas to keep the surface of the formed film clean. (D) A step of forming a film of the silicide while the pressure inside the reaction chamber is set to a relatively low pressure. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the silicide film is formed without a cleaning step after the polysilicon film is formed. 9. A method of manufacturing a semiconductor device having a series circuit of a memory cell selection MISFET and an information storage capacitive element, wherein the gate electrode of the MISFET and the internal wiring of the semiconductor device are provided on an impurity-containing polysilicon film. A method of manufacturing a semiconductor device, comprising using a polycide film having a silicide film formed thereon, the polycide film being formed in the next step. (A) A step of forming the polysilicon film. (B) A step of forming a thin film which becomes an initial nucleus of the silicide while the reaction chamber is set to a relatively high pressure at the start of forming the silicide film. (C) A step of bringing the reaction chamber into a high vacuum state by exhausting the reaction gas to keep the surface of the formed film clean. (D) A step of forming a film of the silicide while the pressure inside the reaction chamber is set to a relatively low pressure. 10. The method of manufacturing a semiconductor device according to claim 7, wherein the silicide is tungsten silicide. 11. A method of manufacturing a semiconductor device having a series circuit of a memory cell selection MISFET and an information storage capacitive element, comprising: a gate electrode of the MISFET and an internal wiring of the semiconductor device; A method for manufacturing a semiconductor device, comprising using a polycide film having a silicide film formed thereon, the polycide film being formed in the next step. (A) A step of forming the impurity-containing polysilicon film by the first chemical vapor deposition apparatus. (B) The tungsten silicide is formed by a second chemical vapor deposition apparatus, and a thin film that becomes an initial nucleus of the tungsten silicide is formed with the reaction chamber of the apparatus set to a relatively high pressure at the start of film formation. Process. (C) A step of bringing the reaction chamber into a high vacuum state by exhausting the reaction gas to keep the surface of the formed film clean. (D) A step of forming the tungsten silicide by the second chemical vapor deposition apparatus and forming a film of the tungsten silicide in a state where the reaction chamber is set to a relatively low pressure. 12. A method of manufacturing a semiconductor device having a series circuit of a MISFET for selecting a memory cell and a capacitance element for storing information, comprising: a gate electrode of the MISFET and an internal wiring of the semiconductor device; A method of manufacturing a semiconductor device, comprising using a polycide film having a silicide film formed thereon, the polycide film being formed in the next step. (A) A step of forming the impurity-containing polysilicon film by a first chemical vapor deposition apparatus provided with a load lock device. (B) Tungsten silicide is formed by a second chemical vapor deposition apparatus, and a thin film serving as an initial nucleus of the tungsten silicide is formed with the reaction chamber of the apparatus set to a relatively high pressure at the start of film formation. Process. (C) A step of bringing the reaction chamber into a high vacuum state by exhausting the reaction gas to keep the surface of the formed film clean. (D) A step of forming the tungsten silicide by the second chemical vapor deposition apparatus and forming a film of the tungsten silicide in a state where the reaction chamber is set to a relatively low pressure. 13. The method of manufacturing a semiconductor device according to claim 12, wherein after the polysilicon film is formed, the silicide film is formed without a cleaning step. 14. The method of manufacturing a semiconductor device according to claim 12, wherein the first chemical vapor deposition apparatus is an apparatus that performs batch processing, and the second chemical vapor deposition apparatus is single-wafer processing. A method for manufacturing a semiconductor device, which is a device for performing the above. 15. The method of manufacturing a semiconductor device according to claim 12, wherein the relatively high pressure in the step (b) is about 950 mTorr, and the high vacuum state in the step (c) is several mTorr. The method for manufacturing a semiconductor device, wherein the relatively low pressure in the step (d) is about 150 mTorr. 16. The method of manufacturing a semiconductor device according to claim 12, wherein the semiconductor device mounts a CMOS circuit, and the polysilicon is n + polysilicon and p + polysilicon. Method. 17. The method of manufacturing a semiconductor device according to claim 12, wherein one of the reaction gases for forming the silicide is tungsten hexafluoride, and the flow rate thereof in the step (b) is higher than that in the step (d). A method for manufacturing a semiconductor device, characterized in that the number is set to be small. 18. A method of manufacturing a semiconductor device having a logic circuit including a driving MISFET, comprising:
A method of manufacturing a semiconductor device, wherein a polycide film having a silicide film formed on an impurity-containing polysilicon film is used for the gate electrode and the internal wiring of the semiconductor device, and the polycide film is formed by the following step. (A) A step of forming the impurity-containing polysilicon film by a chemical vapor deposition apparatus. (B) A step of forming the silicide by a chemical vapor deposition apparatus and forming a thin film which becomes an initial nucleus of the tungsten silicide in a state where the reaction chamber of the apparatus is set to a relatively high pressure at the start of film formation. (C) A step of bringing the reaction chamber into a high vacuum state by exhausting the reaction gas to keep the surface of the formed film clean. (D) A step of forming the silicide by the chemical vapor deposition apparatus and forming a film of the silicide while the reaction chamber is set to a relatively low pressure. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the semiconductor device mounts a CMOS circuit, and the polysilicon is n + polysilicon and p + polysilicon. Method.