JPH0680831B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a conductive modulation type semiconductor device used as a power switching element.

[Technical background of the invention and its problems]

In recent years, a power MOSFET has appeared on the market as a power switching element, but an element having a sufficiently low on-resistance at a blocking voltage of 1000 [V] or higher has not yet been realized. The reason is that the higher the blocking voltage V _B , the higher the on-resistance Ron of the device.
It is known that there is the following relationship between the two.

Ron ∝ V _B ^{2.5 In} order to improve such a situation, a conductivity modulation type switching element has recently been proposed. The basic structure is shown in FIG. This structure is a power MO that is usually called vertical DMOS.
It can be said that the n ⁺ layer that becomes the drain region of the SFET is replaced with the p ⁺ layer. That is, a high resistance n ⁻ layer 12 (second region) is formed on the p ⁺ substrate 11 (first region), and the p ⁺ layer 13 (third region) is selectively formed on the surface of the n ⁻ layer 12. further selectively formed n ⁺ layer 14 (the fourth region) in the surface portion of the p ⁺ layer 13, the p ⁺ layer 13
A gate electrode 16 is formed on the surface region sandwiched by the n ⁻ layer 12 and the n ⁺ layer 14 as a channel region with a gate insulating film 15 interposed therebetween. Reference numeral 17 is a source electrode arranged so as to extend from the p ⁺ layer 13 to the n ⁺ layer 14, and 18 is a drain electrode.

The operation of this element is as follows. When the source electrode 17 is grounded and a positive voltage is applied to the gate electrode 16 and the drain electrode 18, p ⁺ directly below the gate electrode 16 is operated by the same principle as the MOSFET.
It is turned on because the surface of the layer 13 is inverted and an electron channel is formed. What is different from the MOSFET is the drain side p ⁺ substrate 11
As a result, holes are injected into the n ⁻ layer 12, and the injected holes are accumulated in the n ⁻ layer 12 to reduce the resistance in this region. Due to the effect of this conduction modulation, the on-resistance can be made sufficiently low irrespective of the above equation which is a problem in the case of MOSFET.

However, this switching element has a drawback that the turn-off time becomes much longer than that of the MOSFET, while the on-resistance is reduced. This is because it takes time for the carriers accumulated in the n ⁻ layer 12 to disappear. This turn-off mechanism will be described in detail. FIG. 2 shows a typical switching waveform of the conductivity modulation type switching element. From the figure, it can be seen that there are two phases I and II at turn-off. First Phase I
Is that the channel on the surface of the p ⁺ layer 13 disappears due to the gate voltage becoming zero, and the electron current flowing through this channel becomes zero, so that the drain current immediately decreases by that amount. is there. The second Phase II following this is the n ^- layer
Due to the carrier remaining in 12, the p ⁺ layer 13-n ^- layer 12-p ⁺
The current flowing due to the transistor action of the substrate 11 is attenuated by the carrier life τ.

n ⁻ layer 12 has an impurity concentration of 10 ¹⁴ [cm ⁻³ ] and a thickness of 40 to 50 μm
The typical turn-off time t _off is 10
It exceeds [μsec].

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide a conductive modulation type semiconductor device in which the turn-off time is sufficiently short while maintaining a low on-resistance.

[Outline of Invention]

The present invention focuses on the fact that in the device structure shown in FIG. 1, the ratio of the electron current to the hole current in the drain current at the time of ON is almost determined by the injection efficiency of holes from the p ⁺ substrate 11, and the n ⁻ layer 12
An n ⁺ layer having a total amount of impurities of 4 × 10 ¹³ [cm ⁻² ] or more is provided in a portion of the (second region) in contact with the p ⁺ substrate 11 (first region).

In the case of a device in which the conductivity type of each region is reversed, a p ⁺ layer having a total impurity amount of 4 × 10 ¹³ [cm ⁻² ] or more may be provided at the same position.

〔The invention's effect〕

According to the present invention, by suppressing the carrier injection from the drain side and changing the ratio of the electron current and the hole current in the drain current, it is possible to increase the rate of the current decrease instantaneously in phase I described above. As a result, the turn-off time can be significantly shortened. At the same time, according to the invention,
The voltage at which the high resistance layer punches through increases, and the voltage blocking capability of the device also improves.

Example of Invention

Examples of the present invention will be described below. FIG. 3 shows an element structure of one embodiment, and portions corresponding to those of FIG. 1 are designated by the same reference numerals as those of FIG. This will be described according to the manufacturing process. First, on a p ⁺ substrate 11 of about 1 × 10 ²⁰ [cm ⁻³ ], 6 × 10 ¹⁷
[Cm ^-3 ], 5 μm thick n ⁺ layer 19 and 3 × 10 ¹⁴ [cm ^-3 ], 40 μm
The m-thick n ⁻ layer 12 is formed by the ion implantation method and the vapor phase growth method. Next, by selective diffusion method, p ⁺ to a depth of about 5 μm
A layer 13 is formed, and an n ⁺ layer 14 is further formed on the surface thereof. Then, the gate insulating film 15 is formed by high temperature thermal oxidation, and the n ⁺ layer 14 and
In order to form an ohmic electrode in the p ⁺ layer 13, the gate insulating film 15 is perforated, aluminum is deposited by several μm, and selective etching is performed to form the gate electrode 16 and the source electrode 17. Finally, a V-Ni-Au film is vapor-deposited on the back surface of the wafer to form a drain electrode 18, which is completed.

The switching waveform of the device according to this embodiment is shown in FIG. In this device, due to the presence of the n ⁺ layer 19, from the p ⁺ substrate 11
The efficiency of hole injection into the n ^- layer 12 is significantly reduced, and accordingly, the ratio of the electron current to the current flowing through the n ^- layer 12 at the time of ON is increasing. As a result, as is apparent from comparison with FIG. 2, when the gate voltage becomes zero and the electron current is interrupted or cut off, the current decrease in Phase I is large, and the turn-off time is t _off 6 [μsec]. It is reduced to about 1/2 of the conventional one.

FIG. 5 is the result of theoretical calculation of the ratio of the electron current in the on-current when the total amount of impurities existing in the n ⁺ layer 19 of FIG. 3 is changed. From this data, the ratio of the electron current starts to increase when the amount of impurities in the n ⁺ layer 19 exceeds 4 × 10 ¹³ [cm ⁻² ], and the increasing tendency is remarkable above 3 × 10 ¹⁴ [cm ⁻² ]. Appears in.

For reference, 2 × 10 ¹⁶ [c at a portion of the n ⁺ layer 19 of FIG. 3
m ⁻³ ], an n layer with a thickness of about 15 μm (total impurity amount 3 × 10 ¹³ [c
m ^-2 ]) to increase the punch-through breakdown voltage of the n ^- layer 12 is known. However, even if the n layer having such an impurity amount is provided, almost no increase in the ratio of the electron current is recognized, as is apparent from FIG. That is, the impurity amount of the n ⁺ layer 19 is set to 4
The turn-off time can be shortened from the point where it exceeds × 10 ¹³ [cm ^-2 ], and the effect of further shortening the turn-off time can be obtained by setting it to 3 × 10 ¹⁴ [cm ^-2 ] or more. Moreover, the amount of impurities in the n ⁺ layer 19 is 3 × 10 ¹⁴ to 10
If the ratio is about ¹⁵ [cm ^-2 ], the proportion of electron current will increase, and there will always be hole current.
It is kept low enough compared to DMOS.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an example of a conductive modulation type switching element,
FIG. 2 is a diagram showing the switching operation waveform, FIG. 3 is a diagram showing a conductive modulation type switching element of an embodiment of the present invention, and FIG. 4 is a diagram showing the switching operation waveform.
The figure is a figure for demonstrating the effect of this invention. 11 ... p ⁺ substrate (first area), 12 ... n ^- layer (second area), 13 ...
p ⁺ layer (third region), 14 ... N ⁺ layer (fourth region), 15 ... Gate insulating film, 16 ... Gate electrode, 17 ... Source electrode, 18 ... Drain electrode, 19 ... N ⁺ layer.

Claims (3)

[Claims] 1. A first region of a first conductivity type having a high impurity concentration,
A second region of the second conductivity type having a low impurity concentration provided on the first region, a third region of the first conductivity type selectively formed on the surface of the second region, and the third region. A fourth region of the second conductivity type having a high impurity concentration, which is selectively formed on the surface portion, and a portion sandwiched between the second region and the fourth region surface of the third region surface is used as a channel region. A semiconductor device in which a gate electrode is formed on a channel region via a gate insulating film, a source electrode is formed in contact with the surfaces of the third region and the fourth region at the same time, and a drain electrode is formed on the surface of the first region. 2. The semiconductor device according to claim 2, wherein a high-concentration second conductivity type layer having a total amount of impurities of 4 × 10 ¹³ cm ⁻² or more is provided in a portion of the second region in contact with the first region. 2. The semiconductor device according to claim 1, wherein the total amount of impurities in the high-concentration second conductivity type layer is in the range of 3 × 10 ¹⁴ cm ^-2 or more. 3. The semiconductor device according to claim 1, wherein the total amount of impurities in the high-concentration second conductivity type layer is in the range of 10 ¹⁵ cm ^-2 or less.