JPH0888357A - Lateral igbt - Google Patents

Abstract

PURPOSE: To lower the ON-voltage of a device by a method wherein a second type carrier current has a polarity opposite to the polarity of a second conductivity type drain layer and the ratio of the second type carrier current in a total current is increased to increase the accumulation of the second type carrier current on the source side. CONSTITUTION: A trench 7 is formed in the surface of an n-type silicon layer 3 between an n-type buffer layer 4 and a p-type base layer 11. An n-type bypass layer 12 is so formed in the n-type silicon active layer 3 under the trench 7 as to be brought into contact with a silicon oxide film 2. Therefore, a positive hole current applied to a source electrode 9 can be reduced by the trench 7. On the other hand, an electron current can be applied to a device through the n-type bypass layer 12 and the reduction of the electron current caused by the trench 7 can be suppressed. With this constitution, the ratio of the electron current in a total current can be elevated and the accumulation of the electron current on the source side is increased, so that the ON-voltage of the device can be lowered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral IGBT.

[0002]

2. Description of the Related Art An IGBT (Insulated Gate Bipolar Transistor) is one of the insulated gate high withstand voltage semiconductor elements.
). The IGBT is a new high breakdown voltage semiconductor device having both the high speed switching characteristics of a power MOSFET and the high output characteristics of a bipolar transistor.
It is widely used in the field of power electronics such as inverters and switching power supplies.

FIG. 27 is a sectional view showing the element structure of a conventional lateral IGBT. In the figure, reference numeral 71 denotes a silicon substrate, and a low concentration (high resistance) n-type silicon layer (active layer) 73 is provided on the silicon substrate 71 via a silicon oxide film 72.

On the surface of the n-type silicon active layer 73,
The p-type base layer 81 is selectively formed, and the n-type source layer 80 is selectively formed on the surface of the p-type base layer 81.

On the p-type base layer 81 sandwiched between the n-type source layer 80 and the n-type silicon active layer 73, a gate electrode 78 is provided via a gate insulating film (not shown). . The source electrode 79 is arranged so as to contact the n-type source layer 80 and the p-type base layer 81.

An n-type buffer layer 74 is selectively formed on the surface of the n-type silicon active layer 73 which is separated from the p-type base layer 81 by a predetermined distance, and the drain is formed on the surface of the n-type buffer layer 74. A high-concentration (low-resistance) p-type drain layer 75 provided with an electrode 76 is selectively formed.

The operation of the lateral IGBT constructed as described above is as follows. That is, at the time of turn-on, a positive voltage is applied to the gate electrode 78 with respect to the source electrode 79.

As a result, the channel region on the surface of the p-type base layer 81 below the gate electrode 78 becomes conductive, and n
Electrons are injected into the n-type silicon active layer 73 from the type source layer 80, and holes are injected into the n-type silicon active layer 73 from the p-type drain layer 75.

As a result, the n-type silicon active layer 73 undergoes conductivity modulation to have a low resistance, and a main current flows between the drain and source. On the other hand, when turned off, a negative voltage is applied to the gate electrode 78 with respect to the source electrode 79.

As a result, the channel region on the surface of the p-type base layer 81 below the gate electrode 78 becomes non-conductive, electrons are not injected from the n-type source layer 80 to the n-type silicon active layer 73, and the n-type is formed. The silicon active layer 73 does not cause conductivity modulation, and eventually the main current stops flowing between the drain and source.

However, this type of lateral IGBT has the following problems. That is, at turn-on,
There is a problem that the on-voltage becomes high due to the voltage drop generated in the channel region on the surface of the p-type base layer 81.

[0012]

As described above, the conventional lateral IGBT has a problem that the ON voltage becomes high due to the voltage drop in the channel region. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a lateral IGBT having a low on-voltage.

[0013]

In order to achieve the above object, a lateral IGBT according to the present invention (claim 1) comprises a low-concentration first-conductivity-type active layer formed on an insulating film. A second conductive type base layer selectively formed on the surface of the first conductive type active layer; a first conductive type source layer selectively formed on the surface of the second conductive type active layer; A gate electrode disposed on the second conductive type base layer between the conductive type source layer and the first conductive type active layer via a gate insulating film, and selected on the surface of the first conductive type active layer. Formed on the first conductivity type active layer between the second conductivity type drain layer and the second conductivity type base layer, and a second conductivity type drain layer formed under the groove. And a high-concentration first-conductivity-type bypass layer formed on the first-conductivity-type active layer.

Another lateral IGBT according to the present invention (claim 2) is a low-concentration first conductivity type active layer formed on an insulating film, and is selectively formed on the surface of the first conductivity type active layer. A second conductive type base layer, a first conductive type source layer selectively formed on a surface of the second conductive type base layer, and a second conductive type base layer formed in a region of the second conductive type base layer. A comb-shaped source electrode in contact with the first conductivity type source layer, and a gate insulating film on the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer. And a gate electrode formed in a comb shape so as to mesh with the comb-shaped source electrode, and a second conductivity type drain layer selectively formed on the surface of the first conductivity type active layer. It is characterized by having.

[0015]

According to the present invention (claim 1), the first type carrier current having the same polarity as the second conductivity type drain layer flowing into the source electrode can be reduced by the groove formed in the first conductivity type active layer. .

On the other hand, a second type carrier current having a polarity opposite to that of the second conductivity type drain layer is also affected by the groove.
Since the seed carrier current can flow in the device through the high-concentration (low resistance) first-conductivity-type bypass layer below the groove, the decrease in the second-type carrier current due to the groove can be suppressed to a low level.

Therefore, the proportion of the second type carrier current in the total current increases, and the accumulation of the second type carrier current on the source side increases, so that the on-voltage of the element decreases. Further, according to the present invention (Claim 2), since the gate electrode and the source electrode are formed in a comb shape so as to mesh with each other, compared to the case where the gate electrode and the source electrode are formed in a stripe shape. Since the area of the channel region per unit area of the surface of the second conductivity type base layer increases, the on-voltage decreases.

[0018]

Embodiments will be described below with reference to the drawings. FIG. 1 is a lateral IGBT according to a first embodiment of the present invention.
3 is a cross-sectional view showing the element structure of FIG.

In the figure, reference numeral 1 denotes a silicon substrate, on which a low concentration (high resistance) n-type as an SOI semiconductor layer is provided via a silicon oxide film 2 as an SOI insulating film. A silicon active layer 3 is provided.
That is, the silicon oxide film 2 and the n-type silicon active layer 3 form an SOI substrate.

Here, the thickness of the silicon oxide film 2 is from 1 to
It is preferably about 5 μm. The thickness of the n-type silicon active layer 3 is preferably 20 μm or less, more preferably 10 μm or less.
μm or less. The impurity concentration of the n-type silicon active layer 3 is preferably 1.0 × 10 ^{10 to} 3.0 × 10 ¹² cm ⁻² , more preferably 0.5 to 1.8 × 10 ¹² cm ⁻² .

Further, p is formed on the surface of the n-type silicon active layer 3.
The type base layer 11 is selectively formed, and the n-type source layer 10 is selectively formed on the surface of the p-type base layer 11.

A thickness of 60 n is formed on the p-type base layer 11 sandwiched between the n-type source layer 10 and the n-type silicon active layer 3.
A gate electrode 8 is provided via a gate insulating film (not shown) of about m. Further, the source electrode 9 is arranged so as to contact the n-type source layer 10 and the p-type base layer 11.

An n-type buffer layer 4 is selectively formed on the surface of the n-type silicon active layer 3 which is separated from the p-type base layer 11 by a predetermined distance, and the drain is formed on the surface of the n-type buffer layer 4. High concentration (low resistance) p provided with electrode 6
The type drain layer 5 is selectively formed.

Further, the n-type buffer layer 4 and the p-type base layer 1
A trench groove 7 is formed from the surface in the n-type silicon layer between the n-type silicon layer 1 and the n-type silicon active layer 3 under the trench groove 7. Has been formed. The n-type bypass layer 12 is in contact with the silicon oxide film 2.

According to this embodiment, the n-type silicon active layer 2
The hole current flowing into the source electrode 9 can be reduced by the trench groove 7 formed in. On the other hand, the electron current is also affected by the trench groove 7, but since the electron current can flow in the element through the low-resistance n-type bypass layer 12 under the trench groove 7, the electron current due to the trench groove 7 is generated. The decrease of is kept low.

Therefore, the ratio of the electron current to the total current increases, and the accumulation of the electron current on the source side increases, so that the on-voltage of the element decreases. 2 shows the trench groove 7
In a plan view showing the pattern (trench groove pattern), a strip-shaped trench groove pattern is shown. By using such a trench groove pattern, it is possible to realize a lateral IGBT having a high breakdown voltage because it does not prevent the depletion layer from spreading when a reverse bias is applied. Further, by using such a trench groove pattern, even when the trench groove 7 reaches the n-type bypass layer 12, a high withstand voltage lateral IGBT is obtained.
Can be realized.

FIG. 3 is a plan view showing another trench groove pattern. This forms a plurality of rectangular trench grooves 7, and the n-type silicon active layer 3 remains in the trench grooves 7. By using such a trench groove pattern, the hole current flowing through the source electrode 9 can be more effectively reduced, and the ON voltage can be lowered.

FIG. 4 is a plan view showing still another trench groove pattern. This is an example in which a rectangular trench groove 7 is formed on the entire surface of the n-type silicon active layer 3. This trench groove pattern is most effective in reducing the hole current among the trench groove patterns so far. However, in this case, in order to obtain a high breakdown voltage, it is necessary to thicken the n-type silicon active layer 3 between the trench groove 7 and the n-type bypass layer 12.

FIG. 5 is a sectional view showing the element structure of a lateral IGBT according to the second embodiment of the present invention. The lateral IGBT of this embodiment is different from that of the first embodiment in that the size of the n-type bypass layer 12 is reduced. That is, the n-type bypass layer 1 is formed only in the region below the trench groove 7.
2 is formed and does not extend to the region below the p-type base layer 11. Also in this embodiment, since the n-type bypass layer 12 is formed in the necessary region (lower part of the trench groove 7), the same effect as that of the previous embodiment can be obtained.

FIG. 6 is a sectional view showing the element structure of a lateral IGBT according to the third embodiment of the present invention. The lateral IGBT of this embodiment is different from that of the second embodiment in that the trench groove 7 reaches the n-type bypass layer 12.
Also in this embodiment, the same effect as in the second embodiment can be obtained.

Further, in the case of this embodiment, after the trench groove 7 is formed, the n-type impurity is ion-implanted,
Since the n-type bypass layer 12 can be formed, when the SOI substrate is formed by the bonding method, the trench groove 7 from the surface is formed.
Since it is not necessary to form and align with the n-type bypass layer 12 from the back surface, the process can be simplified.

FIG. 7 is a sectional view showing the element structure of the lateral IGBT according to the fourth embodiment of the present invention. The lateral IGBT of this embodiment is different from that of the third embodiment in that the n-type bypass layer 12 is separated from the silicon oxide film 2. Also in this embodiment, the same effect as that of the third embodiment can be obtained.

FIG. 8 is a sectional view showing the element structure of a lateral IGBT according to the fifth embodiment of the present invention. The lateral IGBT of the present embodiment is different from that of the fourth embodiment in that the n-type bypass layer 12 is formed not only on the bottom of the trench groove 7 but also on the side of the trench groove 7, and the entire circumference of the trench groove 7 is surrounded. The n-type bypass layer 12 is formed in the. According to this embodiment, it is possible to more effectively reduce the resistance until the electrons reach the channel region.

In the second to fifth embodiments, as the pattern of the trench groove 7, any of the trench groove patterns shown in FIGS. 2 to 4 may be used. FIG. 9 is a sectional view showing the element structure of a lateral IGBT according to the sixth embodiment of the present invention.

The lateral IGBT of this embodiment differs from that of the first embodiment in that a trench gate is used. That is, after forming a trench groove reaching the silicon oxide film 2 and forming a gate insulating film 14 on the side wall of this trench groove, the inside of the trench groove is filled with a gate electrode 13.

At this time, a high-concentration p-type diffusion layer 15 is formed on the surface of the p-type base layer 11 on the drain side of the n-type source layer 10. As a result, the hole current directly flows into the source electrode 9 without passing under the n-type source layer 10, so that the latch-up of the parasitic thyristor can be prevented.

10 to 12 show the lateral IGB of this embodiment.
It is a top view which shows the concrete pattern of the trench groove pattern in T. 10 to 12 are respectively shown in FIGS.
This corresponds to FIG. 4, and the same effects as those obtained when using the trench groove patterns of FIGS. 2 to 4 are obtained.

FIG. 13 is a sectional view showing the element structure of a lateral IGBT according to the seventh embodiment of the present invention. The lateral IGBT of this embodiment is different from that of the sixth embodiment in that the size of the n-type bypass layer 12 is reduced. That is, the n-type bypass layer 12 is formed only in the region below the trench groove 7, and does not extend to the region below the p-type base layer 11. Also in this embodiment, the required area (trench groove 7
Since the n-type bypass layer 12 is formed in the lower part), the same effect as the sixth embodiment can be obtained.

FIG. 14 is a sectional view showing the element structure of a lateral IGBT according to the eighth embodiment of the present invention. The lateral IGBT of this embodiment is different from that of the seventh embodiment in that the trench groove 7 reaches the n-type bypass layer 12. Also in this embodiment, the same effect as that of the seventh embodiment can be obtained.

Further, in the case of this embodiment, similarly to the case of the lateral IGBT of the third embodiment, the alignment between the trench groove 7 and the n-type bypass layer 12 becomes unnecessary, so that the process can be simplified. Like

FIG. 15 is a sectional view showing the element structure of a lateral IGBT according to the ninth embodiment of the present invention. The lateral IGBT of this embodiment is different from that of the eighth embodiment in that the n-type bypass layer 12 is separated from the silicon oxide film 2. Also in this embodiment, the same effect as that of the eighth embodiment can be obtained.

FIG. 16 is a plan view of a lateral IGBT according to the tenth embodiment of the present invention, and FIG. 17 is a sectional view taken along the line AA 'of the lateral IGBT of FIG. In the figure, reference numeral 21 indicates a silicon substrate, and on the silicon substrate 21, S
SO through the silicon oxide film 22 as an OI insulating film
A low concentration (high resistance) n-type silicon active layer 23 is provided as an I semiconductor layer.

Here, the thickness of the silicon oxide film 2 is from 1 to
It is preferably about 5 μm. In addition, the n-type silicon active layer 23
The thickness of is preferably 20 μm or less, more preferably 1
It is 0 μm or less. The impurity concentration of the n-type silicon active layer 23 is preferably 1.0 × 10 ^{10 to} 2.0 × 10 ¹² cm ⁻² , more preferably 0.5 to 1.8 × 10 ¹² cm ⁻² .

On the surface of the n-type silicon active layer 23, p
The type base layer 30 is selectively formed, and the n type source layer 29 is selectively formed on the surface of the p type base layer 30.

Here, the p-type base layer 30 is formed, for example, by ion implantation of boron, but by adjusting the diffusion time and the dose amount, the diffusion of boron in the lateral direction is suppressed and formed shallow. Further, the n-type source layer 29 is formed by ion implantation of an element in which lateral diffusion hardly occurs, for example, arsenic ion implantation.

As a result, a channel region is formed in which the distance between the n-type silicon active layer 23 and the n-type source layer 29 of the p-type base layer 30, that is, the channel length is shorter than usual (about 3 μm). To be done.

On the p-type base layer 30 in the channel region, a comb-teeth-shaped gate electrode 27 is provided via a gate insulating film (not shown) having a thickness of about 60 nm. Also,
A source electrode 28 is embedded so as to reach from the surface of the n-type source layer 29 to the middle of the p-type base layer 30, and the source electrodes 28 are arranged so as to mesh with the comb-teeth-shaped gate electrode 27.

An n-type buffer layer 24 is selectively formed on the surface of the n-type silicon active layer 23 separated from the p-type base layer 30 by a predetermined distance, and the drain is formed on the surface of the n-type buffer layer 24. A high concentration (low resistance) p-type drain layer 25 provided with an electrode 26 is selectively formed.

According to this embodiment, since the gate electrode 27 and the source electrode 28 are formed in a comb-teeth shape so as to mesh with each other, compared to the case where the gate electrode and the source electrode are formed in a stripe shape. Since the area of the channel region per unit area of the surface of the p-type base layer becomes large, the on-voltage can be lowered.

Further, according to this embodiment, since the channel length is short, the voltage drop in the channel region is small, and the IG
The current density of BT becomes high. Generally, the shorter the channel length, the smaller the voltage drop and the higher the current density. However, according to the research by the present inventor, in the case of the lateral IGBT, the increase in the current density is larger than normally expected. I understood.

FIG. 18 is a characteristic diagram showing the channel length dependence of the current / voltage characteristics of the IGBT representing the above. In the figure, a is the IGB in the case of the conventional normal channel length.
The current-voltage characteristics of T are shown, b shows the current-voltage characteristics of the IGBT that is 33% shorter than the normal channel length, and c shows the current-voltage characteristics of the IGBT that is 47% shorter than the normal channel length. It shows the voltage characteristics.

It is understood from FIG. 18 that the current / voltage characteristics are greatly improved and the current density is significantly increased by shortening the channel length. 19 and 20 are plan views showing other patterns of the gate electrode 27 and the source electrode 28.

FIG. 19 shows a case where the comb-teeth-shaped portion of the gate electrode 27 is triangular and the comb-teeth-shaped portion of the source electrode 28 is trapezoidal. FIG. 20 shows the gate electrode 27.
Also, the case where the shape of the comb-teeth portion of the source electrode 28 is both triangular is shown.

FIG. 21 is a sectional view showing the element structure of the lateral IGBT according to the eleventh embodiment of the present invention. The difference between the lateral IGBT of this embodiment and that of the tenth embodiment is that
The n-type silicon active layer 23 is thin, the n-type buffer layer 24,
The p-type base layer 30 reaches the silicon oxide film 22. In this embodiment, the same effect as that of the tenth embodiment can be obtained. Further, the pattern of the gate electrode 27 and the source electrode may be any one of FIG. 16, FIG. 19 and FIG.

FIG. 22 is a sectional view showing the element structure of the lateral IGBT according to the twelfth embodiment of the present invention. The difference between the lateral IGBT of this embodiment and that of the tenth embodiment is that
This is because the source electrode 29 is not embedded.
However, since the channel length is short,
The current density is high as in the above embodiment.

Further, in this embodiment, the gate electrode 27 is extended to the region of the n-type silicon active layer 23 via the insulating film (not shown). As a result, the gate electrode 27 can have the function of a field plate, and the breakdown voltage can be improved.

FIG. 23 is a sectional view showing the element structure of a lateral IGBT according to the thirteenth embodiment of the present invention. The difference between the lateral IGBT of this embodiment and that of the twelfth embodiment is that
This is because the distance between the gate electrode 27 and the source electrode 28 is shortened. As a result, the lateral length of the n-type source layer 29 is shortened, and the latch-up current can be increased.

FIG. 24 is a plan view showing a main part of a lateral IGBT according to the fourteenth embodiment of the present invention. The lateral IGBT of this embodiment is different from that of the twelfth embodiment in that the lateral length of the n-type source layer 29 is extremely short. In this case, the contact between the n-type source layer 29 and the source electrode 28 has a small area, which may cause contact failure. Therefore, as shown in FIG.
Long lateral part 2 for making contact with 8
9 are provided at predetermined intervals.

FIG. 25 is a sectional view showing the element structure of the lateral IGBT according to the fifteenth embodiment of the present invention. The difference between the lateral IGBT of this embodiment and that of the twelfth embodiment is that
The n-type silicon active layer 23 is thin, the n-type buffer layer 24,
The p-type base layer 30 reaches the silicon oxide film 22. Also in this embodiment, the same effect as in the twelfth embodiment can be obtained.

FIG. 26 is a sectional view showing the element structure of a lateral IGBT according to the 16th embodiment of the present invention. The difference between the lateral IGBT of this embodiment and that of the thirteenth embodiment is that
The n-type silicon active layer 23 is thin, the n-type buffer layer 24,
The p-type base layer 30 reaches the silicon oxide film 22. In this embodiment, the same effect as that of the thirteenth embodiment can be obtained.

The horizontal IG according to the tenth to sixteenth embodiments
In BT, the comb-teeth-shaped source electrode was formed by embedding, but n
Similar effects can be obtained even when formed on the surfaces of the mold source layer and the p-type base layer.

[0062]

As described above in detail, the present invention (Claim 1)
According to the above, the groove formed in the active layer of the first conductivity type and the first conductivity type bypass layer below the groove increase the carrier current of the second kind having the opposite polarity to the drain layer of the second conductivity type in the total current. Since the accumulation of the second type carrier current on the source side increases, the on-voltage of the element decreases.

Further, according to the present invention (Claim 1), since the gate electrode and the source electrode are formed in a comb shape so as to mesh with each other, the second electrode below the gate electrode is formed.
Since the area of the channel region per unit area of the surface of the conductive type base layer becomes large, the on-voltage becomes low.

[Brief description of drawings]

FIG. 1 is a sectional view showing an element structure of a lateral IGBT according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a trench groove pattern.

FIG. 3 is a plan view showing another trench groove pattern.

FIG. 4 is a plan view showing still another trench groove pattern.

FIG. 5 is a sectional view showing an element structure of a lateral IGBT according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing an element structure of a lateral IGBT according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing an element structure of a lateral IGBT according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing an element structure of a lateral IGBT according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view showing an element structure of a lateral IGBT according to a sixth embodiment of the present invention.

FIG. 10 is a plan view showing a trench groove pattern.

FIG. 11 is a plan view showing another trench groove pattern.

FIG. 12 is a plan view showing still another trench groove pattern.

FIG. 13 is a sectional view showing an element structure of a lateral IGBT according to a seventh embodiment of the present invention.

FIG. 14 is a sectional view showing an element structure of a lateral IGBT according to an eighth embodiment of the present invention.

FIG. 15 is a sectional view showing an element structure of a lateral IGBT according to a ninth embodiment of the present invention.

FIG. 16 is a lateral IGBT according to a tenth embodiment of the present invention.
Plan view showing the device structure of

17 is a cross-sectional view taken along the line AA ′ of the lateral IGBT of FIG.

FIG. 18 is a characteristic diagram showing channel length dependence of current / voltage characteristics of the IGBT.

FIG. 19 is a plan view showing patterns of gate electrodes and source electrodes.

FIG. 20 is a plan view showing another pattern of the gate electrode and the source electrode.

FIG. 21 is a lateral IGBT according to an eleventh embodiment of the present invention.
Cross-sectional view showing the device structure of

FIG. 22 is a lateral IGBT according to a twelfth embodiment of the present invention.
Cross-sectional view showing the device structure of

FIG. 23 is a lateral IGBT according to a thirteenth embodiment of the present invention.
Cross-sectional view showing the device structure of

FIG. 24 is a lateral IGBT according to a fourteenth embodiment of the present invention.
Plan view showing the main part of

FIG. 25 is a lateral IGBT according to a fifteenth embodiment of the present invention.
Cross-sectional view showing the device structure of

FIG. 26 is a lateral IGBT according to a sixteenth embodiment of the present invention.
Cross-sectional view showing the device structure of

FIG. 27 is a cross-sectional view showing a device structure of a conventional lateral IGBT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Silicon oxide film 3 ... N-type silicon active layer (first conductivity type active layer) 4 ... N-type buffer layer 5 ... P-type drain layer (second conductivity type drain layer) 6 ... Drain electrode 7 ... Trench groove 8 ... Gate electrode 9 ... Source electrode 10 ... N-type source layer (first conductivity type source layer) 11 ... P-type base layer (second conductivity type base layer) 21 ... Silicon substrate 22 ... Silicon oxide film 23 ... N Type silicon active layer (first conductivity type active layer) 24 ... N type buffer layer 25 ... P type drain layer (second conductivity type drain layer) 26 ... Drain electrode 27 ... Gate electrode 28 ... Source electrode 29 ... N type source layer (First conductivity type source layer) 30 ... P-type base layer (second conductivity type base layer)

Claims (2)

[Claims] 1. A low-concentration first conductivity type active layer formed on an insulating film, and a second selectively formed on the surface of the first conductivity type active layer.
A conductive type base layer, a first conductive type source layer selectively formed on a surface of the second conductive type base layer, and the first conductive type source layer and the first conductive type active layer. A gate electrode disposed on the second conductive type base layer via a gate insulating film, and a second electrode selectively formed on the surface of the first conductive type active layer.
A conductive type drain layer, a groove formed in the first conductive type active layer between the second conductive type drain layer and the second conductive type base layer, and the first conductive type active layer under the groove And a high-concentration first-conductivity-type bypass layer formed on the substrate. 2. A low-concentration first-conductivity-type active layer formed on an insulating film, and a second selectively-formed surface of the first-conductivity-type active layer.
A conductive type base layer, a first conductive type source layer selectively formed on the surface of the second conductive type base layer, and a first conductive type source layer formed in a region of the second conductive type base layer. A comb-teeth-shaped source electrode so as to be in contact with the layer, and a gate insulating film provided on the second conductive type base layer between the first conductive type source layer and the first conductive type active layer, And a gate electrode formed in a comb shape so as to mesh with the source electrode in a comb shape, and a second electrode selectively formed on the surface of the first conductivity type active layer.
A lateral IGBT comprising a conductive drain layer.