JPH0675752A - Leading one predicting device and floating point addition/ subtraction device - Google Patents

Abstract

PURPOSE:To omit the normalizing process by calculating accurately the bit shift extent for normalization when the cancellation occurs in subtraction of the mantissa value in a floating point calculation mode. CONSTITUTION:A cancellation value predicting device 21 predicts the cancellation value within a 1-bit error range, and a borrow transmitting device 22 transmits the borrow given from the side of the least significant bit. Then a selector 23 corrects the output of the device 21 into an accurate bit shift extent based on the information on the device 22 and then the result is outputted for normalization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for performing addition normalization of floating point arithmetic, and more specifically,
The present invention relates to a preceding 1 prediction device that predicts a precision loss caused by addition and subtraction of floating point arithmetic, and a floating point addition and subtraction device that uses the preceding 1 prediction device.

[0002]

2. Description of the Related Art In addition and subtraction of a floating point operation, a mantissa value may be subtracted depending on a combination of signs of two operands and addition and subtraction processing. When the absolute value of the difference between the exponent values of the two operands is 1 or less due to the subtraction of the mantissa value, there may be two or more digits missing in the mantissa value. When the digit loss occurs, a step of calculating the digit loss amount to normalize the mantissa value subtraction result and a step of normalizing the subtraction result based on the digit loss amount are necessary. However, if the digit cancellation amount is calculated and normalized after waiting for the output of the mantissa value subtraction result, the execution time of addition normalization becomes long. Therefore, it is known that the execution time of addition normalization can be reduced by predicting the amount of precision loss during normalization prior to execution of subtraction of the mantissa value or in parallel by means independent of addition operation. It was

As a conventional example, there is JP-A-2-144624. The conventional example (conventional example 1) will be described below with reference to the drawings. FIG. 8 is a diagram showing an algorithm for predicting a digit loss amount in Conventional Example 1 using a state transition diagram. XOR (P, Propagate = propagation), AND (G, Generate = occurrence), NOR (Z, Zero =) resulting from bit comparison of corresponding bit positions of two operands of two's complement representation
The amount of cancellation is predicted by looking at the combination of networks that process the (zero) state signal from the most significant bit side. First, the state of the most significant bit (GMS
B, ZMSB, PMSB) is discriminated, and if the state is G or Z
If so, a signal representing the number of shifts is generated. This number is a count of each determined continuous state signal and is generated as long as the state is true. When the state becomes false, the generation of the shift amount signal is stopped and the adjustment signal is issued. The adjustment signal is based on the carry from the lower bit at the false bit position and the state of the false bit position is used to determine the sign of the addition result.

When the state of the most significant bit is P (PMSB), the stop of the shift number signal depends on the state of the state signal at the bit position following the false bit position. If the second state (Gj or Zj) at the false bit position is accompanied by a state signal of the third state (Z if P → G, G if P → Z), the third state is false when the shift signal is generated. Or the shift signal is stopped at the bit position following the false bit position. In these cases, the adjustment signal will be based on the carry from the lower bit at the bit position where the shift signal was stopped, and the state at this position will determine the sign of the addition result.

By this mechanism, the number of consecutive 0s or 1s counted from the most significant bit generated by the addition / subtraction of the mantissa value, that is, when the addition / subtraction result of the mantissa value becomes positive, is continuous by means different from the addition / subtraction circuit. When the result of subtracting the mantissa value is negative, the number of consecutive 1's in the two's complement representation can be obtained.

As a conventional example, Japanese Patent Laid-Open No. 5-53765.
There is a gazette. The conventional example (conventional example 2) will be described below with reference to the drawings.

FIG. 9 is a block diagram of the leading 1 detection circuit of the second conventional example. Reference numeral 804 in the figure represents a one-digit element of the leading 1 detection circuit.

The minuend X and the subtraction Y are input to the redundant binary value generation circuit 901 for each bit, and the redundant binary value Zsd is generated. Explaining the kth bit, this redundancy 2
The decimal circuit executes the subtraction Xk-reduction Yk and outputs redundant binary values Zsdk = 1, 0, -1. Next, Zsdk is input to the intermediate sum intermediate carry generation circuit 902, and the intermediate sum S is added according to the rule of Table 1 by referring to Zsdk + 1 of 1 bit higher.
k, generate intermediate carry Ck.

[0009]

[Table 1]

Next, the scan value generation circuit 903 is performed by using the intermediate sum Sk and the intermediate carry Ck-1 from the lower bit of 1 bit.
At, the scan value Zk is generated according to the rules of Table 2.

[0011]

[Table 2]

At this time, since the number of 0s from the most significant bit of Z until the first 1 appears is a bit shift amount at the time of normalization or a value 1 bit smaller than that, this Z Is input to the priority encoder,
It was possible to obtain the bit shift amount at the time of normalization or a number smaller by 1 bit. Further, by this mechanism, a bit shift amount for normalization or a number smaller by 1 bit can be obtained independently of the addition / subtraction circuit regardless of the sign of the subtraction result of the mantissa value.

Next, FIG. 1 is a block diagram of a mantissa arithmetic unit of a floating point addition / subtraction apparatus using the leading 1 detection circuit of the conventional example 2.
It shows in 0. When the subtraction is performed on the two floating-point data X and Y consisting of the mantissa part, exponent part, and sign part, digit alignment processing, mantissa part addition / subtraction processing, and normalization processing are executed in this order. The floating point addition / subtraction device using the leading 1 detection circuit of the conventional example 2 shown in FIG. 10 will be described below as an example.

First, the digit alignment process is executed as follows. Two input operand exponents (Xe, Ye)
Is input to the subtraction circuit 305, the shift signal generation circuit 304, and the selector circuit 306. At the same time, the operand mantissas (1.Xf or 0.Xf, 1.Yf or 0.
Yf) is also input to the left / right one-digit shift circuit 301. At this time, in the subtraction circuit 305, the operand exponent value Xe,
Subtracting Ye, the absolute value (Xe-Ye) and the sign value (Xe-
Ye) and. At the same time, the shift signal generation circuit 304 detects whether or not each input operand is a normalized number, and the code values (Xs, Ys) of the operands are detected.
) And the subtraction execution signal SUB are used to create a control signal that shifts the two input operand mantissa values to the left or right. The left / right shift circuit 301 shifts the two input operand mantissa values to the right or left based on the control signal from the shift signal generation circuit 304. The output of the left / right shift circuit 301 is input to the swap circuit 302, where the subtraction circuit 3
Based on the code value (Xe-Ye) output from 05,
The input data is swapped, the mantissa value of the operand with a small exponent value is input to the right barrel shift circuit 303, and the other mantissa value of the operand with a small exponent value is input to the adder / subtractor circuit 307. In the right barrel shift circuit 303, the input value is shifted to the right by the absolute value (Xe-Ye) of the difference between the operand exponent values output from the subtraction circuit 305. In this way, the digit alignment process is executed.

Secondly, addition / subtraction processing and rounding processing are executed by the addition / subtraction circuit 307.

Thirdly, the normalization process will be described. In parallel with the second addition process and the rounding process, the prediction of the digit cancellation amount is executed by using the leading 1 detection circuit 311 and the priority encoder 308. The predicted digit cancellation amount is output as Zae from the priority encoder 308.

The left barrel shift circuit 309 shifts the output value of the adder / subtractor circuit 307 to the left by using the predicted digit cancellation amount Zae output from the priority encoder 308. At the same time, the value of the first digit higher than the decimal point is output to the signal line L1. L1 is "0" if the value after left shift is not normalized, and becomes "1" if it is normalized. If L1 is "0", it means that the predicted digit cancellation amount Zae was smaller by 1, so it is necessary to shift the digit to the left by one digit. This is executed by the alignment circuit 312.

At the same time, the predicted amount of cancellation Zae
Is also input to the subtraction circuit 310, and two subtractions Ze'-Zae and Ze'-Zae-1 are simultaneously executed in the subtraction circuit 310 and output to the data lines L2 and L3. Then, in the selector circuit 313, the value of the signal line L1 is "0".
If so, the subtraction result of Ze'-Zae is output, and if the value of the signal line L1 is "1", the subtraction result Ze of Ze'-Zae-1 is output, and the normalization processing is realized.

[0019]

However, in the configuration like the above-mentioned conventional example 1, when the subtraction result of the mantissa value is negative, the number of consecutive 1's is calculated from the most significant bit in the 2's complement representation. However, in the floating-point format, the mantissa value is generally expressed as an absolute value. Therefore, when performing the conversion, the number of consecutive 1s and the bit shift amount during normalization cause a 1-bit error. Could occur.

Further, in the configuration of the above-mentioned conventional example 2, the bit shift amount to be output is the bit shift amount at the time of normalization or the bit shift amount 1 bit less than the bit shift amount at the time of normalization. In addition to the process of digit-matching the mantissa value subtraction result with the obtained bit shift amount, a process of further correcting an error of 1 bit is necessary.

Therefore, in view of the above problems, the present invention accurately predicts the bit shift amount at the time of normalization in parallel with or prior to the subtraction of the mantissa value, regardless of whether the subtraction result is positive or negative. And a floating point adder / subtractor capable of high-speed arithmetic processing by simultaneously performing subtraction of a mantissa value and prediction of an accurate bit shift amount at the time of normalization by using the preceding one predictor. It is intended to provide.

[0022]

In order to solve the above-mentioned problems, the preceding one predictor of the present invention has a means for generating the above-mentioned precision loss amount within an error range of 1 bit, and a borrow from the lower bit side. A means for generating propagation information is provided, and the selector outputs an accurate bit shift amount necessary for normalizing the precision cancellation amount depending on the presence or absence of the borrow.

Further, in the floating-point addition / subtraction device of the present invention, in the addition / subtraction circuit of the floating-point operation mantissa value, the two mantissa value operands after the digit alignment processing are simultaneously input to the addition / subtraction circuit and the preceding one prediction device. Then, the addition / subtraction circuit executes subtraction, inputs the subtraction result to the barrel shifter, and shifts the subtraction result input to the barrel shifter using the bit shift amount output from the preceding one prediction device. It is a thing.

[0024]

According to the present invention, by using the preceding one predictor having the above-mentioned configuration, the amount of precision loss during mantissa value subtraction can be accurately predicted in parallel with or prior to the mantissa value subtraction, regardless of whether the subtraction result is positive or negative. can do. In addition, by operating this preceding 1 prediction device at the same time as the mantissa value subtraction, the mantissa value subtraction result is obtained, and at the same time, the digit cancellation amount prediction value is used to normalize the mantissa value subtraction result. The device can be realized.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An outline of a preceding one predicting device and a floating point addition / subtraction device according to an embodiment of the present invention will be described below by first comparing a conventional example 2 with the present invention.

In the conventional example 2, the bit shift amount at the time of normalization may be indicated correctly and the value may be indicated by one bit less. These cases will be described in more detail using examples.

For example, the number of input bits is 8 for both the subtracted number and the reduced number.
Consider the case of bits. Subtracting X (7: 0) -reduction Y (7: 0) is executed, and when X> Y, the scan value Zk is set to the third bit for the first time with the least significant bit as 0 bit.
Considering the situation where = 1 appears, Z = 00001ααα: α = 0 or 1.

In this case, X (7: 0) -Y (7: 0) =
If the difference S (7: 0) is set, the maximum value of this difference S is maxS1, and the minimum value is minS1, then maxS1 = 000011111 minS1 = 00000101. Further, when the correct bit shift amount is indicated, the maximum value is maxS2, the minimum value is minS2, the maximum value when the bit shift amount is 1 bit less is maxS3, and the minimum value is minS3.
Then, maxS2 = 00001111 minS2 = 00001000 maxS3 = 00000111 minS3 = 00000101.

When the bit shift amount is reduced by one bit, the first Zk = 1 bit (the least significant bit is k =
0, and in the case of this example, subtraction X by bits less than or equal to the bit one lower than k = 3) (k = 2 in this example)
It can be seen that this corresponds to the case where (2: 0) -Y (2: 0) becomes negative.

Similarly, when Y> X, X (2: 0) -Y
It can be seen that this corresponds to the case where (2: 0) becomes positive.

In this example, the case where the input is 8 bits has been described. However, even in the case of a general arbitrary input bit number, in the conventional example 2, a subtraction result less than or equal to the bit one lower than the bit for which Zk = 1 is first obtained. , X> Y: X (k-1: 0) -Y (k-1: 0) <0 Y> X: X (k-1: 0) -Y (k-1: 0)> It can be seen that when 0, the bit shift amount is one bit smaller.

The present invention corrects and outputs the correct bit shift amount at the time of normalization, corresponding to the case where the bit shift amount is reduced by one bit as described above.

That is, 1) X> Y, 2) Y> X, 3) X (k-1: 0)> Y (k-1: 0), 4) Y (k-1: 0)> X ( k-1: 0) is used to correct and output the position of the scan value Zk = 1 which appears for the first time from the most significant bit of Conventional Example 2 and is then normalized regardless of whether the subtraction result is positive or negative. In this case, it is possible to output an accurate bit shift amount.

How to obtain the above four pieces of information is the binary value created in the conventional example 2 in order to distinguish 1) X> Y and 2) Y> X. Instead of creating the scan value Zk, the redundant binary value ZZk is created according to Table 3.

[0035]

[Table 3]

By doing so, ZZ which appears for the first time
When k ≠ 0 is ZZk = 1, 1) X> Y, ZZk = -1
In the case of, 2) Y> X. ZZk =
0 corresponds to Zk = 0 in the conventional example 2, and ZZK ≠ 0 corresponds to Zk.
Corresponds to = 1.

Next, how to obtain information on the magnitude relationship between X (k-1: 0) and Y (k-1: 0) will be described.

For example, when X (k-1: 0) <Y (k-1: 0), X (n: 0) -Y (m: 0) (n≥k, m≥
x (k-1: 0) -Y (k-1: 0) when executing k)
Since <0, the borrow (borrow B
It can be seen that x (k)) occurs. Similarly, X (k-1:
0)> Y (k-1: 0), Y (m: 0) -X
When (n: 0) is executed, Y (k-1: 0) -X (k-1
It can be seen that a borrow (borrow By (k)) occurs in the digit of Y (k) because: 0) <0. Therefore, in the present embodiment, a borrow propagation device is introduced, and Bx (k) and Bx
By creating y (k), X (k-1: 0) and Y
Information on the magnitude relation of (k-1: 0) is obtained.

Further, 1) X> Y and 4) Y (k-1: 0)
> X (k-1: 0) in combination, 2) Y> X and 3) X (k-1: 0)> Y (k-1: 0) in combination with the most significant bit It is provided with a selector for increasing the number of consecutive ZZk = 0 until ZZk ≠ 0, which appears for the first time from the above, by these functions. In the embodiment of the present invention, regardless of whether the subtraction result is positive or negative, The bit shift amount for accurate normalization is obtained. By thus inputting the output to the priority encoder, the bit shift number for normalizing the subtraction result can be obtained.

The mantissa value subtraction and the normalization are completed by shifting the mantissa value subtraction result in the binary absolute value representation by the barrel shifter using this bit shift number.

A description will be given below with reference to the drawings.

FIG. 1 is a block diagram of a mantissa value addition system circuit using the leading one predictor according to the present invention. In FIG. 1, 11 is an adder / subtractor circuit that adds and subtracts a mantissa value and outputs an absolute value, 12 is a preceding 1 prediction device having the configuration of the present invention for predicting a digit cancellation amount, and 13 is a temporary value for normalization. A barrel shifter for shifting a numerical value, and 14 is a priority encoder.

FIG. 2 is a block diagram of the preceding one predictor 12 when the input operand of the present invention is 8 bits. In FIG. 2, reference numeral 21 denotes a digit loss amount predicting device that estimates the digit loss amount within a 1-bit error range independently of the addition / subtraction circuit. The scan value ZZk = redundant binary number described above in this device
The value of 1, 0, -1 is output. Reference numeral 22 denotes a borrow propagation device that outputs the propagation of borrow from the lower bit independently of the adder / subtractor circuit. This device outputs the above-mentioned borrows Bx (k) and By (k) for an arbitrary k. Reference numeral 23 indicates a digit cancellation amount predicting device 2 based on the output from the borrow propagation device 22.
It is a selector that operates the bit shift amount required for normalization from the output of 1.

FIG. 3 is a detailed diagram of the digit loss amount predicting device 21 written at the gate level. In FIG. 3, 31 and 32 are 8-bit input operands, and PLUS 33 and MINUS 3
4 is the scan value ZZk, when ZZk = 1, PLUS = 1 and MINUS = 0, and when ZZk = 0, PLUS = 0 and MINUS =
When 0 and ZZk = -1, it is a signal line for outputting with PLUS = 0 and MINUS = 1. At this time, PLUS = 1 and MINUS
There is no state where = 1. Here, the number of consecutive 0s until ZZk ≠ 0 appears for the first time from the most significant bit, that is, PLUS for the first time from the most significant bit.
= "1" or MINUS = "1", whichever comes first, PLUS = "0" or MINUS
The number of = “0” corresponds to the digit loss amount when the borrow from the lower bit is not taken into consideration. Here, when the number other than ZZk = 0 that appears for the first time is ZZk = 1, the result of subtraction of the mantissa value is positive, and when ZZk = -1, it corresponds to the negative case.

Gx 35, Gy 36, and P37 are bit lines for each bit to be output to the borrow propagation device, and Gx
x 35 is (NOT operand X) AND (operand Y), that is, (Xk, Yk) = (0, 1), and Gy 36 is (operand X) AND (NOT operand Y), that is, (Xk,
Yk) = (1,0), P37 is (operand X) XNOR
(Operand Y), that is, (Xk, Yk) = (0, 0)
Indicates or (1, 1). Gx (n) 35 is the operand X
Gy is a signal that the nth bit of
(N) 36 is a signal that the nth bit of the operand Y has generated a borrow, and P (n) 37 is a signal that propagates the borrow from the lower bit. Gx (n) 35 and Gy
The reason why the 6th bit is not required in (n) 36 is that the 6th bit has already been taken into consideration in the redundant binary subtraction of the 7th bit.

FIG. 4 is a diagram in which the borrow propagation device 22 is written at the gate level. In FIG. 4, 41 is an external clock input (clock 1) for precharging and discharging the precharge line and outputting the value of the precharge line, and 42 is a clock for outputting the value of the precharge line. Input (clock 2) of
It has a phase opposite to that of clock 1. 131
Numerals 144 to 144 are precharge lines which are precharged when clock 1 is "0" and discharged when clock 1 is "1" and a path to ground is open. Bx 39 is a signal that the borrow from the operand X is propagated to the nth bit, and By 4
0 is a signal that the borrow from the operand Y is propagated to the nth bit. Bx 39 and By 40 do not require both 0th bit and 1st bit,
This is because there is no borrow propagating to the 0th bit and the borrow propagating to the 1st bit has already been taken into consideration when creating ZZk.

In general, borrow propagation is B (n) = G (n) + P (n) * G (n-1) = G (n) + P (n) * {P (n-1) * G ( n-2) + P (n-1) * P (n-2) * G (n-3) + ...} It is represented by (1).

The bit precharge line for which the equation (1) is satisfied is discharged when the clock 1 is "1". Therefore, since the discharged bit has a borrow from the lower bit, it is possible to set a bit having a borrow from the lower bit by outputting it through an inverter. However, when the clock 1 is "0", the inverter is set to high level. By using a tri-state inverter that becomes an impedance, it is possible to maintain the state when the clock signal is "1" even when the clock signal is "0" by using the floating capacitance such as the wiring capacitance. There is.

FIG. 5 is a diagram showing the selector 23 in more detail. In FIG. 5, reference numeral 51 is a demultiplexer, which is information from the outputs PLUS33 and MINUS 34 of the precision cancellation device 21, that is, ZZk = 1, 0, −1, and the information Bx 39 and By 40 from the borrow propagation device 22, that is, Y. (K-1
: 0)> X (k-1: 0), X (k-1: 0)> Y (k-1:
0) selects the bit shift amount for normalization.

FIG. 6 is a diagram in which the demultiplexer 51 is written at the transistor level. If the output Bx (k) 36 from the borrow propagation device is "0", the position of PLUS (k) is directly output as LZA (k) to the output PLUS (k) 33, and if it is "1", PLUS (k) is output. The position of is corrected to 1 bit lower bit and output as LZA (k-1). Similarly, the output B from the borrow propagation device 22 is output to the output MINUS (k) 34.
If y (k) 37 is "0", the position of MINUS (k) is output as LZA (k), and if "1", MINUS is output.
Correct the position of (k) to 1 bit lower bit and change LZA (k-
Output as 1). This is when there is a borrow from the lower bit in the output from the digit loss amount prediction device 21, that is, 1) X> Y and 4) Y (k-1: 0)> X (k-1:
0) or 2) Y> X and 3) X (k-1: 0)> Y
In case of (k-1: 0), it corresponds to the correction so that the digit cancellation amount is increased by 1 bit. This output LZA (7:
When 0) is input to the priority encoder and the number of consecutive zeros from the most significant bit is counted, the number is the bit shift amount for normalization.

Next, the operation of the above configuration will be described using an example. As an example, an 8-bit operand X (7: 0) = 111010100, Y as an input after digit matching of mantissa values
(7: 0) = 11001101 is X (7: 0) -Y
Consider the case where it is input as (7: 0). First, the operand loss X (7: 0) = 111010 is input to the precision canceller 21.
100, Y (7: 0) = 11001011, is input. In the actual binary subtraction, the difference S is S (7: 0) = 0000
It is 0111. The digit cancellation amount predicting device 21 generates a scan value ZZk which is a redundant binary number, and as a result thereof,
PLUS (7: 0) 33 = 00001000, MINUS (7:
0) 34 = 00000001, that is, ZZk = 000
0100T (T = -1) is output. At this stage, ZZk ≠ 0, which first appears from the highest rank and appears ZZk = 1, shows that X> Y.

As an output to the borrow propagation device 22, Gx (5: 0) 35 = 001001 which indicates a bit that a borrow may occur from the operand X, and a bit which a borrow may occur from the operand Y are shown. Gy
(5: 0) 36 = 010000, P indicating borrow propagation
(6: 1) 37 = 110011 is output.

Next, in the borrow propagation device 22, the precharge lines 131 to 144 are precharged when the clock 1 is "0", and when the clock 1 is "1", the Gx
(5: 0) 35 = 001001, Gy (5: 0) 36 =
Input 010000 and P (6: 1) 37 = 110011. Then, the precharge lines 131, 132, 1
A path from 33, 134, 142, 143, 144 to ground is created and discharged. If the clock 2 is set to "0" at this stage, Bx (7: 2) 39 = 000111 and By (7:
2) 40 = 111000 is output. That is, since ZZk ≠ 0 for the first time in ZZ (4) counting from the most significant bit, and ZZk = 1, X> Y. Looking at the borrow Bx (4) at this time, Bx (4) = 1,
In this case, ZZk ≠ 0 for the first time from the most significant bit.
This is the case where it is necessary to increase the number of consecutive 0s by 1 bit until

Next, the PLUS (7: 0) 33 is sent to the selector 23.
= 00001000, MINUS (7: 0) 34 = 0000
0001 (that is, ZZ (7: 0) = (0000100
T) (T = -1)), Bx (7: 2) 39 = 000011
If you enter 1, By (7: 2) 40 = 111000,
LZA (7: 0) 38 = 00000101 is output.
In LZA (7: 0) = 00000101, 5 bits of 0 continue until the bit in which 1 appears for the first time from the most significant bit, so the number of bit shifts in normalization is 5 bits. Therefore, if this result is input to the priority encoder 24 which looks at the most significant bit, the bit shift signal "101" for the decoded normalization input to the barrel shifter is obtained. This binary value "1"
01 "is 5 in decimal notation.

In this example, X (7: 0) is Y (7:
0), but it is X (7: 0).
The same effect can be obtained when is smaller than Y (7: 0). In the present embodiment, the preceding one prediction device has a configuration independent of the mantissa value addition / subtraction circuit, but if the borrow propagation device is shared with the mantissa value addition / subtraction circuit, the borrow propagation device portion can be omitted. . Not limited to the 8-bit configuration, any number of bits may be used in general.

Further, when the present invention is used in a system in which it is known that one of the dividend and the subtraction is always greater than the other, the subtraction result is always either positive or negative. The signed digit loss predictor can be replaced with a simple digit loss predictor, and the device that generates information about which operand generated a borrow is generated from the smaller operand of the minuend and the subtraction. It can be replaced with a device that propagates only borrow.

Further, in this embodiment, the redundant binary number expression is used in the process of obtaining the number of consecutive zeros from the most significant bit generated by the mantissa value subtraction, but the binary number is not introduced. It is also possible to adopt a configuration in which only the processing is performed.

Next, FIG. 7 shows a block diagram of the mantissa operation part of the floating point addition / subtraction device using the preceding one prediction circuit. Similar to the conventional example 2, when subtraction is performed on two floating point data X and Y consisting of a mantissa part, an exponent part, and a sign part, digit alignment processing, mantissa part addition / subtraction processing, and normalization processing are performed in this order. To be executed.

The floating point adder / subtractor using the preceding 1 predictor circuit of the present invention shown in FIG. 7 will be described below as an example. The digit alignment process and the mantissa part addition / subtraction process are the same as those in the conventional example 2. The explanation of the first and second parts is
It has been described in the section of the conventional technique. The processing up to this point is the same as in the second conventional example, but the normalization processing is performed by the left barrel shift circuit 309 with respect to the mantissa value, which is the first embodiment of the present invention.
Digit cancellation amount Z predicted based on the output of the prediction device 321
This is completed by using ae and shifting the output of the adder / subtractor circuit 307 to the left to output it. With respect to the exponent value, the predicted digit cancellation amount Zae is input to the subtraction circuit 310, and the subtraction circuit 31
At 0, Ze'-Zae = Ze is executed, and Ze is output to complete the process.

[0060]

According to the present invention, since the accurate value of the bit shift amount required for the addition normalization is obtained by the above configuration, in the process of normalizing the addition result,
Digit adjustment is performed by the bit shift amount output by the conventional preceding 1 predictor, and the most significant bit is checked to find that the most significant bit is 0.
In the case of, the process of shifting by one bit more can be eliminated.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a mantissa value addition system circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a preceding one prediction device in the embodiment.

FIG. 3 is a detailed diagram of a precision cancellation amount prediction apparatus in the embodiment.

FIG. 4 is a detailed view of a borrow propagation device according to the embodiment.

FIG. 5 is a detailed diagram of a selector in the embodiment.

FIG. 6 is a detailed diagram of a demultiplexer according to the embodiment.

FIG. 7 is a block diagram of a floating point addition / subtraction device according to an embodiment of the present invention.

FIG. 8 is a diagram of a simple algorithm for predicting a precision loss according to Conventional Example 1.

9 is a block diagram of a leading 1 detection circuit of Conventional Example 2. FIG.

FIG. 10 is a block diagram of a floating point addition / subtraction device of Conventional Example 2.

[Explanation of symbols]

 12 Leading 1 Predictor 21 Digit Loss Predictor 22 Borrow Propagator 23 Selector

Claims (5)

[Claims] 1. A first digit for generating a predicted digit loss within the error range of 1 bit when the digit loss occurs in the subtraction result of the mantissa value in the addition / subtraction instruction of the floating point operation.
Means, second means for generating information on the propagation of borrow from the lower bit side that occurs at the time of subtraction of the mantissa value, and third means for operating the precision cancellation amount using the borrow propagation information. According to the presence / absence of the borrow, the third means outputs a bit shift amount for normalizing the mantissa value in which the digit cancellation has occurred, from the digit cancellation prediction amount obtained by the first means. The preceding 1 prediction device characterized by the above. 2. When a digit loss occurs in the subtraction result of the mantissa value in the addition / subtraction instruction of the floating point arithmetic, the digit loss amount is generated within the error range of 1 bit, and the digit loss predicted amount is generated, and
Outputs whether the result of the add / subtract instruction is positive or negative
And the information of the borrow propagation from the lower bit side that occurs during the mantissa value subtraction, and the borrow that occurs when the mantissa value of the operand is subtracted The subtraction result is a positive number, which is provided with a second means for separately generating two types of borrows that occur at this time and a third means for manipulating the predictive loss amount using the propagation information of the borrow. If the subtraction result is negative, the subtraction result is negative.If the subtraction result is negative, the subtraction result is negative depending on whether there is a borrow or not. The preceding one prediction device, wherein the third means outputs a bit shift amount for normalizing the mantissa value in which the digit cancellation has occurred, from the obtained digit cancellation prediction amount. 3. The leading one predictor according to claim 2, wherein each of the digits is a minuend X composed of an i-digit binary number and a subtraction Y composed of a j-digit binary number (i and j are natural numbers). And a first means for generating a redundant binary number Zsd each of which is composed of (1, 0, -1) for each digit, and kth digit (k is the least significant digit) from the lower digit of the redundant binary digit Zsd. Zsdk + is used by using the redundant binary value Zsdk of which the bit is k = 0) and the redundant binary value Zsdk + 1 of the k + 1th digit from the lower order.
Intermediate carry Ck according to the formula Zsdk = 2Ck + Sk so that Ck = Zsdk when 1 = “1” or “−1” and CK = 0 when Zsdk + 1 = “0”.
, Second means for generating the intermediate sum Sk, and "0" when the addition result for each digit of the intermediate carry Ck-1 from the lower digit and the intermediate sum Sk is 0, and "1" when the addition result is-, And a third means for generating a redundant binary number ZZk of "-1" when it is "1". 4. A mantissa part operand, an exponent part operand,
A floating-point addition / subtraction device that adds or subtracts two operand data in a floating-point format having a sign part operand, and an addition / subtraction circuit to which two mantissa operands after digit alignment processing are input, respectively. The preceding 1 prediction device described, a barrel shifter to which the output of the adder / subtractor circuit is input, and a priority encoder that receives the numerical value output from the preceding 1 prediction device and determines the number of consecutive zeros from the highest order, A floating point addition / subtraction device, wherein the output of the addition / subtraction circuit input to the barrel shifter is shifted and output using the output of the priority encoder. 5. A mantissa part operand, an exponent part operand,
A floating-point addition / subtraction device for adding or subtracting two operand data in a floating-point format having a sign part operand, wherein the addition / subtraction circuit receives two mantissa value operands after digit alignment processing. The preceding 1 prediction device described, a barrel shifter to which the output of the adder / subtractor circuit is input, and a priority encoder that receives the numerical value output from the preceding 1 prediction device and determines the number of consecutive zeros from the highest order, A floating point addition / subtraction device, wherein the output of the addition / subtraction circuit input to the barrel shifter is shifted and output using the output of the priority encoder.