JPH0553765A - Preceding one detecting circuit and floating point adder-subtractor - Google Patents

Abstract

PURPOSE:To simultaneously proceed the prediction of a cancelling amount and the subtraction of a mantissa by predicting the cancelling amount at the time of subtracting the mantissa which is generated when the difference of an exponent value is + or -,1 or 0, in a floating point adder-subtractor. CONSTITUTION:A minuend Xk and a subtrahend Yk are used so as to generate a redundant binary numeral Zsd in a redundant binary numeral generating circuit 101. Next, the redundant binary numerals Zsd(and Zsd k+j of the k-th(k is a natural number) digit and the (k+1)-th digit from low order are used so as to generate intermediate carry C(and an intermediate sum Sk in accordance with a formula Zsdk=2Ck+Sk so that Ck=2sdk is adopted at the time of Zsdk+1=1 or -1 and Ck=0 is adopted at the time of 2sdk+1=0 in an intermediate sum and intermediate carry generating circuit 102. A scan value generating circuit 103 generates scan value Zk by intermediate carry Ck-1 and the intermediate sum Sk from low order so that Zk=0 is adopted at the time of Ck-1+Sk=0 and Zk=1 is adopted at the time of the formula except Ck-1+Sk=0. The position of one at the highest order of Zk, order becomes the position which is equal to the highest significant digit position or the one digit higher position at the time of subtracting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention executes addition and subtraction on two floating point data consisting of a mantissa part, an exponent part, and a sign part, and when an invalid digit occurs in the upper digit, the most significant position of the significant digit is set at high speed. The present invention relates to a prediction circuit and a floating point addition / subtraction device using this circuit.

[0002]

2. Description of the Related Art Conventionally, when performing mantissa subtraction on two floating point data X and Y consisting of a mantissa part, an exponent part, and a sign part, digit alignment processing, mantissa part addition / subtraction processing, and normalization processing are executed in this order. To be done. An example of a conventional floating-point addition / subtraction apparatus that executes addition / subtraction of floating-point numbers shown in FIG. 4 will be described below.

In FIG. 4, first, digit alignment processing is executed as follows. Two input operand exponents (X
e, Ye) is a subtraction circuit 405, a shift signal generation circuit 404,
It is input to the selector circuit 406. At the same time, the operand mantissa part (1.Xf or 0.Xf, 1.Yf or 0.Yf) is input to the left / right one-digit shift circuit 401.
At this time, the subtraction circuit 405 subtracts Ye from the operand exponent value Xe to obtain an absolute value (absolute value (Xe-Ye)),
A code value (code value (Xe-Ye)) is generated. At the same time, the shift signal generation circuit 404 detects whether or not each input operand is a normalized number using the exponent values Xe and Ye, and detects the code values (Xs, Ys) of the operands.
The subtraction execution signal sub is used to create a control signal that shifts the two input operand mantissa values to the left or right. This control is shown in Japanese Patent Application No. 1-38687. The left / right shift circuit 401 shifts the two input operand mantissas to the right or left based on the control signal from the shift signal generation circuit 404. The output of the left / right shift circuit 401 is the swap circuit 40.
2, the input data is swapped based on the code value (code value (Xe-Ye)) output from the subtraction circuit 405, and the mantissa value of the operand whose exponent value is not large is the right barrel shift circuit. The other operand mantissa value having a large exponent value is input to the adder / subtractor circuit 407. The right barrel shift circuit 403 shifts the input value to the right by the absolute value (absolute value (Xe-Ye)) of the difference between the operand exponent values output from the subtraction circuit 405. In this way, the digit alignment process is executed.

Next, addition / subtraction processing and rounding processing are executed by the addition / subtraction circuit 407. Further, the normalization process will be described. Exponent value X of two floating point input operands
The subtraction result obtained by subtracting the index value Ye from e is 0, 1 or -1.
In this case, when the floating point number subtraction is executed, an invalid digit may occur in the upper part of the mantissa subtraction value and the digit may be lost. A priority encoder (hereinafter referred to as PE) 408 and a left barrel shift circuit 409 are required for the normalization process of the mantissa value with the digit cancellation. The output result from the adder / subtractor circuit 407 is input to the PE 408 and the left barrel shift circuit 409. The PE 408 detects the amount of left shift required for normalization from the result output from the adder / subtractor circuit 407.
Then, the left barrel shift circuit 409 normalizes the mantissa value subtraction result based on the shift amount detected by the PE 408.

On the other hand, the exponent value input to the selector circuit 406 is the code value (code value (X
e-Ye)), select the one with a smaller index value. The output of the selector circuit 406 is input to the subtraction circuit 410, and the shift amount detected by the PE 408 is subtracted to obtain the exponent value of floating point number addition / subtraction.

As described above, in the conventional floating point addition / subtraction device, in order to normalize the mantissa value subtraction result, the PE 408 detects the number of invalid digits occurring in the upper part of the mantissa value subtraction result, and the detected amount. It was normalized based on.

[0007]

In the conventional floating-point adder / subtractor as described above, the difference between exponents is 0,
When 1 or -1, for the result of subtracting the mantissa value after digit alignment processing, the number of invalid digits occurring in the higher order of the subtraction result is obtained by PE 408, and the number of invalid digits obtained by PE 408 is used. Since the result of numerical subtraction was normalized by the left barrel shift circuit, subtraction of the mantissa value and shift amount detection for normalization and normalization are executed continuously, slowing down the floating point addition / subtraction execution speed. It was the cause.

In view of the above problems, the present invention provides a leading 1 detection circuit that predicts the amount of invalid digits (or the most significant digit) of a mantissa part subtraction result at high speed, and at the same time, uses the leading 1 detection circuit. Accordingly, it is an object of the present invention to provide a floating-point addition / subtraction device that can simultaneously perform subtraction of a mantissa value and prediction of the number of invalid digits of the subtraction result, and can shorten the calculation required time.

[0009]

[Means for Solving the Problems]
Therefore, the leading 1 detection circuit of the present invention has completed the digit alignment processing.
For each of the two floating-point mantissa operands after
Each digit is subtracted and each digit is composed of (-1, 0, 1)
First means for generating a redundant binary value Zsd, and redundant binary
Redundant binary value Zsd in the kth digit from the lower order of the value Zsd_k When
Redundant binary value Zsd at the k + 1th digit from the lower order_{k + 1} Using
Zsd_{k + 1} S when = "1" or "-1"_k =
-Zsd_k And Zsd_{k + 1} S = when "0"
_k = Zsd _k So that the expression Zsd_k = 2 · C_k + S
_k According to this, intermediate carry C_k , Intermediate sum S_k Generate
Second means and intermediate carry C from the lower digit_k-1 And intermediate sum
S_kWhen the addition result of is 0, it is "0". When it is not 0,
Signal Z of "1"_k With a third means for generating
Of.

Further, the floating-point addition / subtraction device of the present invention is a floating-point addition / subtraction device for adding or subtracting two operand data in a floating-point format having a mantissa operand, an exponent operand, and a sign operand. The two mantissa operands after the addition are simultaneously input to the adder / subtractor circuit and the leading 1 detection circuit, the addition / subtraction circuit executes subtraction, and the subtraction result is input to the left barrel shift circuit, and the leading 1 detection circuit is added. Is used to shift the subtraction result input to the left barrel shift circuit to the left by using a value obtained by decoding the predicted number of invalid digits generated in the upper part of the addition / subtraction circuit by PE.

[0011]

According to the present invention, by using the leading 1 detection circuit having the above-described structure, it is possible to predict the number of invalid digits generated during the mantissa value subtraction in a fixed time regardless of the number of digits of the operand. In addition, by operating this leading 1 detection circuit at the same time as the mantissa value subtraction, the mantissa value subtraction result is obtained, and at the same time, the predicted value of the number of digits cancellation is used to normalize the mantissa value subtraction result. A floating point adder / subtractor can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the leading 1 detection circuit used in the floating point addition / subtraction device of the present invention. In floating-point arithmetic, a case where a mantissa digit is lost occurs when mantissa value subtraction is executed when the difference between exponent values is 0, 1 or -1. Leading one detector circuit to be described now is a circuit for predicting the time of mantissa value subtracted perform the cancellation of mantissa values at high speed, where the minuend is X, 2 of the subtrahend Y ^k-1
A range of 3 digits from a digit having a weight of 2 to a digit having a weight of 2 ^{k + 1} is shown. However, k is a natural number. In the following description, processing of a digit having a weight of 2 ^k will be described.

In FIG. 1, reference numeral 101 denotes a redundant binary number generating circuit, which is a redundant binary value Z for each digit from the augend X and the subtraction Y.
Generate sd. 102 is an intermediate sum intermediate carry generation circuit, using a single-digit level redundant binary value (Zsd _{k + 1)} and the digit of the redundant binary value _{(Zsd k), Zsd k =} 2 · C k
According to + S _k , an intermediate carry C _k and an intermediate sum S _k are generated (where C _k and S _k are redundant binary numbers). Reference numeral 103 denotes a scan value generation circuit, which uses the intermediate sum S _k and the intermediate carry C _k-1 from the lower order, outputs 0 when C _k-1 + S _k = 0, and C _k-1 + S _k = 1 is output when other than 0. 104
Is a component for each digit of the preceding 1 detection circuit.

Next, a detailed description of the leading 1 detection circuit of FIG. 1 will be given. First, Table 1 shows a truth table of the redundant binary number generation circuit 101.

[0015]

[Table 1]

In Table 1, X _k and Y _k are the values of the minuend and the k-th digit of the subtraction, respectively, and the redundant binary value Zsd _k is generated by X _k −Y _k = Zsd _k . Next, the redundant binary number generation circuit
With numerical ZSD k + ₁ binary one digit higher redundancy redundant binary value ZSD _k generated by 101, is input to the intermediate sum intermediate carry generation circuit 102. Intermediate sum Intermediate carry generation circuit 102
Then, looking at the redundant binary value Zsd _{k + 1} , the redundant binary value Zs
From d _k , the intermediate sum S _k and the intermediate carry C according to the equation (1)
Generate _k (where C _k and S _k are redundant binary numbers).

[0017]

From the equation (1), the intermediate carry C _k and the intermediate sum S
_k is generated as in equation (2).

[0019]

As can be seen from the equation (2), the redundant binary value Zsd
when _k is "1" or "-1", intermediate carry C _k, that there are two ways a combination of intermediate sum S _k seen. Here, the combination of the intermediate sum and the intermediate carry shown in the equation (2) is distributed as shown in Table 2 below by looking at the redundant binary value Zsd _{k + 1} one digit higher. In Table 2, when the redundant binary value Zsd _{k + 1} with one digit higher is 1 or -1,
A combination is selected such that C _k = Zsd _k, and 1
When the redundant binary value Zsd _{k + 1 of the} upper digit is 0, Zsd _k
Is selected such that the intermediate carry C _k is “0”.

[0021]

[Table 2]

Next, using the intermediate sum S _k and intermediate carry C _k generated by the intermediate sum intermediate carry generation circuit 102, the scan value generation circuit 103 generates the value Z _k . Here, Z _k is generated by the logic shown in Table 3.

[0023]

[Table 3]

In Table 3, the scan value Z_kIs C_k-1 +
S_k = 0 when = 0, C_k-1 + S _k 1 other than = 0
It turns out that Then, it is composed of the above logic
By using the leading 1 detection circuit,
Explain that can be predicted.

First, by using the redundant binary value generation circuit 101, each digit is represented by − from the subtraction and the subtraction expressed in binary numbers.
A redundant binary value Zsd represented by 1, 0, 1 is generated. The redundant binary value Zsd represents a subtraction value for each digit. That is, that the redundant binary number Zsd is "1" means that the minuend of the digit is "1" and the divisor is "0".
That is, the redundant binary number Zsd is "-1", which means that the minuend of the digit is "0" and the divisor is "1".
The fact that the redundant binary number Zsd is "0" means that the minuend and the subtrahend of the digit have the same value. That is, expressing the subtrahend and the minuend with the redundant binary value Zsd has the same effect as executing the subtraction without propagating the borrow.

Here, the subtraction and the subtraction are set to the redundant binary value Zs.
By expressing with d, the following can be said. "If there are 0 or more consecutive numerical values" 0 "from the most significant digit of the redundant binary value Zsd, and if a numerical value other than" 0 "exists after that, the numerical value other than the numerical value other than" 0 "exists There is no highest significant digit in the upper digits.

For example, when viewed from the higher order of the redundant binary value Zsd, the first numerical value other than "0" is "1" and the case of "-1" are shown in equations (3) and (4). ..

[0028]

At this time, the expression (3) can take a value in the range as shown in the expression (5).

[0030]

That is, as can be seen from equation (5), (3)
When the redundant binary value Zsd shown in the formula is converted into a binary number, the most significant digit is higher than the digit in which the numerical value other than "0" exists in the most significant digit as viewed from the most significant digit of the redundant binary value Zsd. There is no significant figure.

Further, as shown in the expression (4), when the numerical value other than "0" which appears first is "-1" when viewed from the higher order of the redundant binary value Zsd, the expression (4) is changed to the expression (6). It takes a value in the range shown in the formula.

[0033]

All the numerical values shown in the equation (6) are negative numbers, and when they are converted into binary numbers, they become as shown in the equation (7).

[0035]

When the result of the subtraction is negative, the invalid digit is "1" continuing from the upper digit, and the most significant digit is the digit having a numerical value other than "1" in the most significant digit as viewed from the most significant digit. In other words, as can be seen from the equations (6) and (7), even when the subtraction result is negative, even if the higher digit of the redundant binary value Zsd is seen, it is higher than the digit having a numerical value other than “0” in the highest digit. It can be seen that there is no highest significant digit in the digit.

As described above, using the subtraction and the subtraction,
By generating the redundant binary value Zsd, the most significant significant digit position can be limited. Next, the generated redundant binary value Zsd is input to the intermediate sum intermediate carry generation circuit 102, decomposed into the intermediate sum S _k and the intermediate carry C _k , and then input to the scan value generation circuit 103. The scan value generation circuit 103 uses the intermediate sum S _k of the digit and the intermediate carry C _k−1 from the lower digit, and if the added value of them is “0”, the added value is “0”. Otherwise, the scan value Z _k of “1” is output. By using such a circuit, the most significant digit position can be predicted more accurately.

The following shows that the most significant significant digit position can be predicted more accurately. Here, an explanation will be given by taking an equation of the form shown in the following equation (8) as an example. In expression (8), an arbitrary redundant binary value (* &) continues from the lowest to the nth digit, and n + 1
The upper m digits from the first digit show the case where the numerical value "0" continues in succession (however, n and m are natural numbers).

[0039]

Here, from the lower order of the redundant binary value Zsd, n
Consider three digits of +1, n, n-1 digits. These three digits
It becomes as shown in equation (9).

[0041]

The equation (9) can be divided into the following three groups.

[0043]

Here, [1] is Zsd _n and Zsd _n-1 having the same sign, [2] is Zsd _n-1 is 0, and [3] is Zsd _n and Zsd _{n-. This} is the case where ₁ is a numerical value with a different sign.

First, consider the case of [1]. The highest significant digit position is the nth digit from the lower. Here, the scan value Z _k of a certain digit is “0” when the added value of the intermediate carry C _k−1 from the lower order and the intermediate sum S _k of that digit is “0”, and the added value is “0”. If it is other than "," it is defined as "1". Now, (Zsd _{n + 1} , Zsd _n , Zsd
Taking the case of ( _n-1 ) = (0,1,1) as an example, let us consider how to divide each digit into an intermediate sum and an intermediate carry. The combination of intermediate sum and intermediate carry is shown in equation (2). Zs
d _{n + 1} = 0 is (C, S) _{n + 1} = as a combination (interpreted as (C, S) _{n + 1} ) divided into an intermediate sum and an intermediate carry.
There is only (0,0). Further, in the case of Zsd _n = 1 there are two types of (C, S) _n = (0,1) and (1, T), but here (C, S) _n = (0,1) To adopt. This results in an intermediate carry C _n = 1 (C, S) _n
= (1, T) is adopted, when the scan value is obtained at the n + 1 digit, Z _{n + 1} = C _n + S _{n + 1} = 1 is obtained, and 1 is the highest in the scan value Z. The existing position (hereinafter referred to as the highest scan position 1 position) is
This is because it is one digit higher than the highest significant digit position. That is, if the value one digit higher is 0, and the value one digit lower is classified as intermediate sum intermediate carry, (C,
S) _n = (0,1) must be divided.

This time, (Zsd _n ,
Notice that Zsd _n-1 ) = (1,1). Zsd _n-1
When (C, S) _n-1 is generated from = 1, from equation (2), 2
May be on the street. That is, (C, S) _n-1 = (1,
T) and (0, 1). Now, the highest 1 position of the scan value must be the nth digit from the lower order (Z _n = 1). That is, C _n-1 + S _n ≠ 0 must be set. As described above, (C, S) _n = (0,
Therefore, no matter whether C _n-1 is 1 or 0, C _n-1 + S _n ≠ 0, and the scan value Z _n =
It becomes 1. Therefore, (Zsd _n , Zsd _n-1 ) =
In the case of (1,1), (C, S) _n-1 = (1, T),
It does not matter which of (0, 1) is adopted.

The above is summarized as follows.
When (C, S) _n-1 = (1, T)

[0048]

When (C, S) _n-1 = (0,1)

[0050]

The above is (Zsd_{n + 1} , Zsd_n ，
Zsd_n-1 ) = (0,1,1)
Solid, (Zsd_{n + 1} , Zsd_n , Zsd_n-1 ) =
The same applies to (0, T, T). But
From the above, (Zsd _{k + 1} , Zsd_k )watch the
In the case of a cigarette, split into intermediate carry intermediate sums as follows:
I understand that it is good.

[0052]

Next, consider the case of [2]. Highest significant digit position, if the value of the ZSD _n the same sign to lower digit than n-1 digit is present, the n-th digit. In the case where a number with a sign opposite to the ZSD _n lower digits than n-1 digit is present, the n-1 digit.

Below, the scan value highest position 1 is the highest position.
Consider an intermediate sum carry that is equal to the significant digit position.
It As an example, (Zsd_{n + 1} , Zsd_n , Zsd_n-1 )
Consider the case of = (0,1,0). (C, S)_n =
The fact that it is (0, 1) is as described above. Well
Zsd_n-1 = 0, so (C, S)
_n-1= (0,0). Therefore, the scan value Z_n 
= 1 (C_n-1 + S_n = 1), and the highest scan value is 1
The position is always the nth digit from the lower order. Therefore, n-1
When there is -1 in the lower side of the digit (below n-1 digit
Zsd in place_n If there is a number with the opposite sign to
), The highest 1 position of the scan value is 1 of the highest significant digit position.
It indicates the upper digit. The above is (Zsd_{n + 1} ，
Zsd_n , Zsd _n-1 ) = (0,1,0)
I thought, (Zsd_{n + 1} , Zsd_n , Zsd_n-1 ) =
The same applies to the case of (0, T, 0).

Further, consider the case [3]. The highest significant digit position is the position of the digit at which it is interrupted or the position one digit lower than that when the same number as Zsd _n-1 is continuously present in the _n- 2th digit and below.

Below, the highest scan value 1 position is the highest
Consider intermediate carry and carry to be equal to significant digit position
It As an example, (Zsd_{n + 1} , Zsd_n , Zsd_n-1 )
Consider the case of = (0,1, T). (Zsd_{n + 1} , Zs
d_n ) = (0,1), (C, S)_n = (0,1)
Is as described above. Then (Zsd
_n , Zsd_n-1 ) = (1, T), (C, S)_n-1 
Think about how to do. The most significant digit position is now
Since it is always a lower digit than the nth digit, the scan value of the nth digit
Zn = 0 must be set. That is,
Now S_n = 1 so C_n-1 = T (C,
S)_n Must be selected. Therefore Zsd
_n-1 = T because (C, S)_n-1 = (T, 1) is selected
To be done.

The above is summarized as follows.

[0058]

Furthermore, in the case of [3], Zsd
Consider the case where _n-2 = T. At this time, the highest significant digit becomes a lower digit than the (n-2) th digit, and therefore the scan value Z _{n- 1} = 0 must be set. Since S _n-1 = 1 now, it is necessary to select (C, S) _n-2 such that C _n-2 = T. Since Zsd _n-2 = T, (C, S) _n-2 = (T, 1) is selected. This is shown below.

[0060]

Therefore, in the case of [3],
When (Zsd _n-1 , Zsd _n-2 ) = (T, T),
(C, S) _n-2 = (T, 1) must be used. If (C, S) _n-2 = (0, T) is used, the most significant 1 position of the scan value and the most significant digit position are completely different.

The above is (Zsd_{n + 1} , Zsd_n , Z
sd_n-1 ) = (0,1, T)
(Zsd_{n + 1} , Zsd_n , Zsd_n-1 ) = (0, T,
The same applies to the case of 1). Therefore, the above
Therefore, any two digits (Zsd _{k + 1} , Zsd_k ) About
When viewed as follows, Zsd is as follows_k Intermediate carry
It turns out that it is sufficient to divide into sums.

[0063]

As described above, from [1] and [3], the same except 0
When numerical values continue ((Zsd _{k + 1}, Zsd_k ) =
In (1, 1), (T, T)) and [1], (C,
S) _k There were two ways to take. However, [3]
When the same numerical value other than 0 continues in the condition
(C, S)_k There is only one way to take
It That is, in [1], how to take (C, S)
Then, the method of [3] should be taken. You
That is, a value one digit higher than [1], [2], and [3]
The rules for generating intermediate sums and intermediate carry are as shown in Table 2.
It becomes a rule. And the rules as shown in Table 2
When the scan value Z is generated by using
The position is the same as the most significant digit position or one digit higher
Will be represented.

Therefore, as described above, by using the leading 1 detection circuit of the present embodiment, it is the same as the most significant digit position of the effective digit at the time of subtraction, or one digit higher position at high speed and related to the number of digits. Can be predicted without.

FIG. 2 shows an example of an actual leading 1 detection circuit assembled according to the above rules. In FIG. 2, the redundant binary number input value Zsd _{k + 1} from the upper digit shown in FIG.
And the intermediate carry C _k-1 from the lower digit are aggregated into the signals P _k , Zsd _k-1 in FIG. Where P _k is 1
It is a signal that the redundant binary value of the upper digit is "0". The circuit shown in FIG. 2 is composed of at most three gate delay stages regardless of the number of digits of the subtrahend and the subtrahend. That is, it can be seen that by using the leading 1 detection circuit of the present embodiment, the digit cancellation amount at the time of subtraction can be predicted much faster than the actual subtraction.

Next, FIG. 3 shows a block diagram of the mantissa operation part of the floating point addition / subtraction device of one embodiment using the leading 1 detection circuit of the present invention. The mantissa part, exponent part,
When the subtraction is performed on the two floating-point data X and Y including the sign part, the digit alignment process, the mantissa part addition / subtraction process, and the normalization process are performed in this order. The floating point adder / subtractor shown in FIG. 3 will be described below as an example.

First, the digit alignment processing is executed as follows. Two input operand exponents (Xe, Ye)
Is input to the subtraction circuit 305, the shift signal generation circuit 304, and the selector circuit 306. At the same time, the mantissa part of the operand (1.Xf or 0.Xf, 1.Yf or 0.Yf)
Is also input to the left / right one-digit shift circuit 301. At this time,
The subtraction circuit 305 subtracts the operand exponent values Xe and Ye to generate an absolute value (absolute value (Xe-Ye)) and a code value (code value (Xe-Ye)). At the same time, the shift signal generation circuit 304 detects whether or not each input operand is a normalized number, and the code value (X
s, Ys) and the subtraction execution signal sub are used to create a control signal that shifts the two input operand mantissa values to the left or right. In the left / right shift circuit 301, the shift signal generation circuit 304
Shift the two input operand mantissas to the right or left based on the control signal from. The output of the left / right shift circuit 301 is input to the swap circuit 302, where the input data is swapped based on the code value (code value (Xe-Ye)) output from the subtraction circuit 305, and the input data of the operand with a small exponent value is swapped. The mantissa value is input to the right barrel shift circuit 303, and the other operand mantissa value whose exponent value is not small is input to the adder / subtractor circuit 307. In the right barrel shift circuit 303,
The input value is shifted to the right by the absolute value (absolute value (Xe-Ye)) of the difference between the operand exponent values output from the subtraction circuit 305. In this way, the digit alignment process is executed.

Secondly, addition / subtraction processing and rounding processing are executed by the addition / subtraction circuit 307. The adder / subtractor circuit 307 outputs the absolute value of the calculation result. Regarding this, Japanese Patent Laid-Open No. 1-2053
No. 28 publication.

Thirdly, the normalization processing will be described. In parallel with the second addition / subtraction process and the rounding process, the digit loss prediction is executed by using the leading 1 detection circuit 311 and PE308. Then, the predicted amount of cancellation is output from PE308 as Zae.

The left shift circuit 309 uses the predicted digit cancellation amount Zae output from the PE 308, and uses the addition / subtraction circuit 307.
The output value of is shifted left and output. At the same time, the value of the first digit higher than the decimal point is output to the signal line L1. L1 is "0" if the value after left shift is not normalized, and becomes "1" if it is normalized. If L1 is "0", it means that the predicted digit cancellation amount Zae was smaller by 1, so it is necessary to shift left by one digit. This is done in the alignment circuit 312.

At the same time, the predicted digit loss Zae
Is also input to the subtraction circuit 310, and in the subtraction circuit 310,
Two subtractions Ze'-Zae and Ze'-Zae-1 are simultaneously executed and output to the data lines L2 and L3. Then, in the selector circuit 313, if the value of the signal line L1 is “0”, Ze ′
The subtraction result of -Zae-1 is output as the subtraction result Ze of Ze'-Zae when the value of the signal line L1 is "1", and the normalization processing is realized.

As described above, the fixed-point addition / subtraction apparatus according to the present embodiment obtains the addition / subtraction result of the mantissa part in parallel with the shift amount required for the normalization for the normalization processing of the subtraction result with the digit cancellation. Since it is possible to make an early prediction by using the leading 1 detection circuit 311 and the PE 308, the normalization processing can be executed earlier. Even if the alignment circuit 312 has to be used, the alignment circuit is fast, so that a high-speed floating-point number adder / subtractor can be realized as a whole.

[0074]

As described above, according to the present invention, the leading 1 detection circuit can predict the digit loss amount that occurs during subtraction in a constant time regardless of the number of digits of the operand. By constructing a floating-point addition / subtraction device using this, since the subtraction of the mantissa value and the prediction of the number of digits loss of the subtraction result can be executed in parallel at the time of the mantissa value subtraction, the floating-point addition / subtraction operation with a short calculation time The effect that the device can be obtained is obtained, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of a leading 1 detection circuit according to an embodiment of the present invention.

FIG. 2 is a logic diagram of the leading one detection circuit shown in FIG.

FIG. 3 is a block diagram showing an embodiment of a floating point addition / subtraction device using the leading 1 detection circuit of an embodiment of the present invention.

FIG. 4 is a block diagram of a conventional floating point addition / subtraction device.

[Explanation of symbols]

 101 Redundant binary number generation circuit 102 Intermediate sum Intermediate carry generation circuit 103 Scan value generation circuit 104 Components for each digit of leading 1 detection circuit 307 Addition / subtraction circuit 308 Priority encoder 309 Left barrel shift circuit 311 Leading 1 detection circuit 312 Alignment circuit X Subscript Y Y Subtraction Zsd Redundant Binary Value C Intermediate Carry S Intermediate Sum Z Scan Value

Claims (2)

[Claims] 1. A minuend X composed of an i-digit binary number and a subtraction Y composed of a j-digit binary number (i and j are natural numbers).
Is subtracted for each digit to generate a redundant binary value Zsd in which each digit is composed of (-1, 0, 1), and the k-th digit from the lower order of the redundant binary value Zsd. (K is a natural number)
Of the redundant binary value Zsdk and the redundant binary value Zsd _{k + 1} of the _{k +} 1th digit from the lower order, C _k = Zsd _k when Zsd _{k + 1} = “1” or “−1”, and Zsd
_{When k + 1} = “0”, the formula Z is set so that _Ck = 0.
According to sd _k = 2 · C _k + S _k , the intermediate carry C _k ,
Second means for generating an intermediate sum S _k, when intermediate carry C _k-1 and the addition result of each digit of the intermediate sum S _k from the lower digit is zero "0", when a non-zero A leading 1 detection circuit comprising a third means for generating a signal Z _k of "1". 2. A mantissa part operand, an exponent part operand,
A floating-point addition / subtraction device that adds or subtracts two operand data in a floating-point format having a sign part operand, and an adder / subtractor circuit to which the two mantissa operands after digit alignment processing are input, respectively. The preceding 1 detection circuit described above, the left barrel shift circuit into which the subtraction result obtained by performing the subtraction in the addition / subtraction circuit is input, and the numerical value output from the preceding 1 detection circuit is input to set the number of invalid digits from the highest rank. A floating point adder / subtractor configured to shift the subtraction result input to the left barrel shift circuit to the left by using the output of the priority encoder.