JPH0669333A - Manufacture of semiconductor device including process for filling groove - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with a high productivity by reducing the manufacturing time when a semiconductor device is manufactured by providing a process wherein grooves in a substrate are filled by a depositing means for etching and depositing at the same time. CONSTITUTION:A manufacture of semiconductor devices including a process for filling grooves 21-23 formed on a substrate 1 by a depositing means which etch and deposit at the same time, wherein after the grooves 21-23 are filled up, unnecessary filling materials 34-36 except the part in the grooves 21 to 23 are removed partly by using a depositing means under the condition that etching progresses in a horizontal direction, if it is necessary. After that, a film 4, the etching speed of whose side wall is high, is formed. A process for removing filling materials 34'-36' to be removed by using the film 4 as a mask 4' is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of filling a groove. INDUSTRIAL APPLICABILITY The present invention can be used as a method of manufacturing a semiconductor device that requires a step of filling a trench to form a trench isolation, a trench capacitor, a buried plug (embedded contact) of a groove, and other structures.

[0002]

2. Description of the Related Art With the miniaturization and high integration of semiconductor devices such as semiconductor integrated circuits, the element-to-element isolation method has replaced the conventional LOCOS method, which has a large dimensional conversion difference. For example, the shallow trench method is about to be used, and its practical application is an important issue.

In order to form such groove-type element isolation with good performance, a technique capable of satisfactorily filling grooves of various shapes is required. To this end, a deposition technique (bias ECR-CVD) in which etching and deposition are performed simultaneously is performed.
Method is typical) can be preferably used. Bias E
The CR-CVD method can form high-density plasma at low pressure, can achieve high-speed growth at low temperature, and by applying an RF bias to a substrate such as a semiconductor wafer, not only deposition but also simultaneous etching can be performed. Therefore, it is possible to satisfactorily embed a miniaturized trench (groove),
It can be said that this technology is indispensable for embedding fine grooves.

However, this technique has the following problems. That is, when the grooves 2a to 2c are filled by making use of the above-mentioned advantages, as shown in FIG. 2, the deposited shape to be formed is dependent on the underlying pattern. As shown in FIG. 2, on the wide area A of the substrate such as the Si substrate, the extra filling material 31 (SiO ₂ or the like) to be removed except the filling portion remains thick. This is because this method generally uses sputter etching of Ar ions for flattening, and the sputter etching has an angle dependence of the etching rate. Therefore, at the horizontal portion, the deposition rate> the etching rate. This is because

Therefore, it is necessary to remove the extra embedding material 31 formed outside the embedding portion. At least, to some extent, a margin for mask alignment is provided around the groove 2a, and therefore some removal is indispensable. In response to this request, the present inventor has invented a method of securing a margin for resist alignment by using so-called horizontal return etching, and then etching and removing an extra filling material (SiO ₂ etc.) to be removed. The horizontal return means that the deposition is performed under the condition that etching progresses in the horizontal direction (horizontal direction in the figure) and neither etching nor deposition progresses in the vertical direction (vertical direction in the figure).
1 is a technique for partially removing 1 (see Japanese Patent Application No. 1-277929 by the present applicant).

However, this horizontal return method requires a certain amount of time because of mask alignment for removing the extra filling material 31 over a wide area, and thus has a problem of poor production efficiency.

[0007]

It is an object of the present invention to solve the above problems and to reduce the manufacturing time when manufacturing a semiconductor device including a step of filling a groove on a substrate with a deposition means for simultaneously performing etching and deposition. An object of the present invention is to provide a manufacturing method capable of shortening and obtaining a semiconductor device with high productivity.

[0008]

The invention according to claim 1 of the present application provides a method of manufacturing a semiconductor device, which comprises a step of filling a groove formed on a substrate by a deposition means for simultaneously performing etching and deposition. After filling the groove,
A semiconductor device having a step of burying a groove, which comprises a step of forming a film having a high etching rate on a sidewall and using the film as a mask to remove a burying material to be removed formed in a portion other than the burying portion. And a method for producing the above-mentioned object. According to the invention of claim 2 of the present application, after the groove is filled, the depositing means is performed under the condition that the etching proceeds in the horizontal direction to partially remove the filling material formed in the portion other than the filling portion. A method of manufacturing a semiconductor device having a step of filling a groove according to claim 1, wherein the step of forming a film having a high etching rate on the side wall is performed after that, and the above object is achieved thereby.

The structure of the present invention will be briefly described below with reference to the example of FIG. 1 showing an embodiment described in detail later. As illustrated in FIG. 1B, the grooves 21 to 23 formed on the substrate 1 such as a semiconductor substrate are embedded by a deposition unit that simultaneously performs etching and deposition as illustrated in FIG. After burying the grooves 21 to 23, the deposition means is performed under the condition that the etching proceeds in the horizontal direction to partially remove the burying material 31 to be removed, which is formed in a portion other than the burying portion. The structure illustrated in (c) is used (the portion exposed by the removal at this time is denoted by reference numeral 1
It shows with 0a-10e. This step may be omitted), and then the film 4 having a high etching rate on the side wall is formed to form the film shown in FIG.
The structure shown in (d) is used, and a step of removing the embedding material 34 '(see FIG. 1 (d)) to be removed by using the film 4 as a mask is provided. The structure after the removal is shown in FIG.

The film 4 having a high etching rate on the side wall means
A portion 41 shown by a broken line in FIG. 1D is easily etched away. For example, P-SiN.
(Plasma silicon nitride) film, P-SiO film,
P-SiON film and P-PSG film are preferable, and P-
BPSG and P-BSG can also be used. Since these have a rough film quality, for example, in the case of wet etching, only the side wall portion to which the etching liquid is attached is easily removed by etching.

[0011]

According to the present invention, the horizontal return as shown in FIG. 1 (c) is performed for a very short time, or even if this step is omitted, the side wall shown in FIG. 1 (d) (e) is removed. Excess filling materials 34 to 36 other than the filling portions 31 to 33 are formed by etching using the film 4 having a high etching rate as a mask (see FIG.
After (c), 34'-36 ') are easily removed, and at least a sufficient margin for resist registration can be secured as shown by reference numeral 10 in FIG. 1 (e). Therefore, the time-consuming horizontal return can be made small or can be omitted, so that the process time can be shortened and the semiconductor device can be manufactured efficiently and with high productivity while reducing the manufacturing time.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the examples described below.

Embodiment 1 This embodiment is for manufacturing a miniaturized and integrated semiconductor device such as a VLSI device in which trenches having active regions of different widths are buried and planarized by using a bias ECR-CVD method. The present invention is applied to the case where the method includes the step of performing the above to form the trench isolation.
In particular, the conventional difficulty has been solved by devising the mask alignment method and the mask shape.

In the present embodiment, the substrate 1 which is a silicon substrate
A figure having trenches 21 to 23 in which a trench pattern is formed (having an etching stopper layer 41 such as a polysilicon film, and a SiO ₂ film which will be the etching stopper layer 42 when the polysilicon film is removed). The structure of 1 (a) is obtained. For patterning, a photolithography technique using a normal resist process and a silicon etching technique can be used. At this time, a wide area A and a narrow area B are formed in the active area.

Next, using bias ECR-CVD,
The grooves 21 to 23 are embedded and flattened. For example, deposition is performed under the following conditions and SiO ₂ is embedded. Gas system used: SiH ₄ / N ₂ O = 20/35 SCCM Pressure: 7 × 10 ⁻⁴ Torr RF bias: 500 W Microwave: 800 W As a result, the structure of FIG. 1B is obtained. Filling material embedded in the grooves 21 to 23 (in this example, SiO ₂ is denoted by reference numerals 31 to 33, and extra filling material deposited on portions other than the filling portion is denoted by reference numerals 34 to 36).

Next, horizontal return is performed. As a result,
The structure is (c). As shown in the figure, the excess filling material (here, SiO ₂ ) 34 to 36 to be removed is partially removed. Although the exposed portions are indicated by reference numerals 10a to 10e, this may be a very small portion and may be a small amount that is not necessary as much as a margin for mask alignment (in the figure, it is exaggerated for clarity). ). The conditions for horizontal return at this time can be set as follows, for example. Used gas system: SiH ₄ / N ₂ O = 7.5 / 35SCC
M Pressure: 7 × 10 ⁻⁴ Torr Microwave: 800W RF bias: 500W

Next, the film 4 having a high etching rate on the side wall is formed.
As a material, SiO ₂ which is a filling material and P-SiN which is a material having an etching rate ratio are subjected to CVD. PS
Formation of iN by CVD may be performed under normal conditions, for example, the following conditions can be adopted. Gas system used: SiH ₄ / NH ₃ / N ₂ = 180/50
0/720 SCCM Pressure: 0.3 Torr Temperature: 250 ° C. RF application: 900 W (380 KH _Z ) Electrode gap: 5 cm At this time, the quality of P-SiN attached to the SiO ₂ side wall, which is the extra filling material 34 ′, becomes rough. There is. Although the mechanism by which the film quality of the portion becomes rough is not always clear, as shown in FIG.
The portion corresponding to the side wall of No. 4 is not irradiated with the ions I, so that the film is not densified, whereas the other regions are irradiated with ions accelerated by the energy of the sheath or the plasma potential and the film is densified. It is presumed that this is due to In addition, as a technique utilizing such a property that the etching rate of the step portion is higher than that of other portions, “Nikkei Electronics”, Nikkei McGraw-Hill 1982 Mar.
There is one described on pages 93 to 94 of the 29th issue of the month, 10
The original document 1) is cited on page 0. Therefore, by utilizing this property, the side wall portion indicated by reference numeral 41 in FIG. 1D is removed by diluted HF or the like.

Next, the film 4 (P-
Using the SiN film) as a mask 4 ', an extra filling material 3
SiO ₂ which is 4'-36 'is removed. At this time, all of SiO ₂ may be removed by wet etching, or only the portion for mask alignment may be removed. For example, when etching with dilute HF, the selection ratio of SiN and SiO ₂ is 10
Since it is a rank, it is sufficient if the mask alignment quantile can be removed. As a result, the structure shown in FIG. 1E is obtained. In the figure, reference numeral 10 indicates a removed portion.

The following is phosphoric acid, which is the PS contained in the film 4.
iN is removed, and the resist is aligned to remove SiO ₂ .
Further, the SiO ₂ / poly-Si structures 41 and 42 are removed.
As a result, as shown in FIG. 6F, a structure having good pressure resistance can be obtained as element isolation in which the embedded portions 31 and 32 of the grooves 21 and 22 are slightly projected from the base 1.

According to this embodiment, after the trenches 21 to 23 are filled, the film 4 is formed on the trenches 21 to 23, and only the portion of the film 4 attached to the side wall of SiO ₂ which is the extra filling material 34 ′ to 36 ′ is attached. Is selectively removed, and excess SiO _{2 is used} as a mask.
Since all or part of the
By the VD method, a mask for removing an extra burying material portion (SiO ₂ ) can be formed, so that the horizontal return becomes unnecessary or the horizontal return time can be shortened.

[0021]

According to the present invention, when a semiconductor device is manufactured with a step of filling a groove on a substrate with a deposition means for simultaneously performing etching and deposition, the manufacturing time is shortened and the productivity is improved. A high semiconductor device can be obtained.

[Brief description of drawings]

1A to 1C are sectional views showing steps of Example 1 in order.

FIG. 2 is a diagram showing a problem.

FIG. 3 is an operation explanatory view.

[Explanation of symbols]

1 Substrate 21-23 Groove 34-36, 34'-36 ', 34 "Filling Material to be Removed 4 Film with High Sidewall Etching Rate 4'Mask

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[Procedure amendment]

[Submission date] June 8, 1993

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a step of filling a groove formed on a substrate by a deposition means that simultaneously performs etching and deposition, wherein a sidewall has a high etching rate after the groove is filled. A method of manufacturing a semiconductor device having a groove burying step, which comprises the step of forming a film and using the film as a mask to remove the burying material formed in a portion other than the burying portion to be removed. 2. After burying the groove, the depositing means is performed under the condition that the etching proceeds in the horizontal direction to partially remove the burying material to be removed formed in a portion other than the burying portion. The method of manufacturing a semiconductor device having a step of filling a groove according to claim 1, wherein the step of forming a film having a high etching rate on the side wall is performed.