JP3190144B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for forming an element isolation region having a trench structure.

[0002]

2. Description of the Related Art In a bipolar integrated circuit, trench isolation capable of reducing an isolation region and a parasitic capacitance is employed as an element isolation technique. This trench isolation forms a groove in the semiconductor substrate,
The element isolation is performed by embedding a polysilicon layer in the groove via an insulating film.
No. 25947.

[0003] On the other hand, element isolation in a CMOS integrated circuit does not require a deep isolation like a trench. Therefore, a field oxide film obtained by improving a selective oxidation method is usually used. Tend to adopt.

FIGS. 4 (a) to 4 (c) show a substrate (semiconductor wafer) in a main step of a method for forming an element isolation region when a conventional trench isolation is employed in a CMOS integrated circuit or a BiCMOS integrated circuit.
2 shows the cross-sectional structure of the device.

First, as shown in FIG. 4A, a thermal oxide film 51 is formed by thermally oxidizing the surface of a P-type silicon substrate 50, and then a silicon nitride film 52 is formed by a CVD (vapor phase growth) method. Formed CVD oxide films 53 are sequentially formed. This C
The VD oxide film 53 becomes a mask material when etching the substrate in a later step.

Next, a resist is applied on the CVD oxide film 53, and exposure and development are performed to form a resist pattern.
By etching the oxide film 53, the silicon nitride film 52, and the thermal oxide film 51, a position where a groove is to be formed is opened to form an opening.

Next, the resist pattern is removed,
Using the CVD oxide film 53 as a mask, a groove 54 is formed in the substrate 50 by anisotropic etching using RIE (Reactive Ion Etching). Next, after a thermal oxide film 55 is formed in the trench 54 by thermal oxidation, ions of a P-type impurity such as boron are implanted to form a P + diffusion layer 56 for a channel stopper at the bottom of the trench.

Next, polysilicon is deposited on the upper surface of the substrate so as to be thinner (for example, about 150 nm) than the width of the groove 54,
Of the polysilicon, the polysilicon 5 on the side of the groove 54
Etch back by anisotropic etching to leave 7.

Next, a portion of the diffusion layer 56 for a channel stopper is exposed on the bottom of the groove by removing the bottom of the groove of the thermal oxide film 55 by wet etching using ammonium fluoride or the like. As a result, the polysilicon deposited in the groove in the later step and the P + diffusion layer 5 are formed.
6 can be in contact with the exposed portion.

Next, as shown in FIG.
4 is filled with polysilicon 58 on the upper surface of the substrate.
μm is deposited. When a ground potential is applied to the polysilicon 58 in the groove, or when the polysilicon 58 in the groove is used for extracting an electrode from the substrate 50, the polysilicon 58 may contain a P-type impurity such as boron. Ions are implanted to make the polysilicon 58 conductive.

Next, the above-mentioned CVD is performed by a surface polishing method or the like.
The polysilicon 58 is exposed until the surface of the oxide film 53 is exposed.
To etch back. Further, the CVD oxide film 53 is removed by etching using ammonium fluoride or the like. As a result, the upper portion of the polysilicon 58 filling the groove 54 projects from the upper surface of the substrate. Further, the polysilicon 58 is removed again by surface polishing until the surface of the silicon nitride film 52 is exposed, so that the upper surface of the polysilicon 58 filling the trench 54 and the surface of the silicon nitride film 52 are removed. Becomes flat.

Next, a resist is applied to the upper surface of the substrate, exposed and developed to form a resist pattern 59, and the silicon nitride film 52 is etched and patterned using the resist pattern 59 as a mask. At this time, the distance S between the adjacent silicon nitride films 52 cannot be smaller than the minimum dimension determined by the exposure resolution.

Next, as shown in FIG. 4C, using the silicon nitride film 52 as a mask,
By performing thermal oxidation only to the thickness of the substrate, a field oxide film 60 for element isolation is formed at a predetermined position on the substrate, and an oxide film 61 for element isolation is formed on the groove. After that, the silicon nitride film 52 is removed.

By the way, the field oxide film 60 is
Although it is used as an isolation region of a CMOS transistor, a lateral oxidation called a bird's beak proceeds during its formation (at the time of field oxidation). Therefore, the width of the field oxide film 60 is smaller than the minimum dimension S determined by the exposure resolution. Has also become wide and hindered miniaturization of the element.

If there is a step on the surface of the substrate, the polysilicon 58 is planarized until the surface of the silicon nitride film 52 is exposed as described above. , And abnormal oxidation occurs when the element isolation oxide films 60 and 61 are formed in a later step, thereby lowering the manufacturing yield.

[0016]

As described above, according to the conventional method for manufacturing a semiconductor integrated circuit, the width of the field oxide film is wider than the minimum dimension determined by the resolution of exposure.
There is a problem that it hinders miniaturization of the element.

Further, the conventional method of manufacturing a semiconductor integrated circuit has a problem that, when a stepped portion exists on the substrate surface, abnormal oxidation occurs at the time of formation of an oxide film for element isolation, and the manufacturing yield is reduced. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In forming an element isolation region, an element isolation region formed by a field oxide film which is narrower than a minimum dimension determined by exposure resolution and a deep groove are formed. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit that can simultaneously form an element isolation region.

Further, according to the present invention, even if there is a step on the substrate surface, it is possible to prevent abnormal oxidation from occurring at the time of forming the oxide film for element isolation and to improve the production yield. An object of the present invention is to provide a method for manufacturing an integrated circuit.

[0020]

According to a method of manufacturing a semiconductor integrated circuit of the present invention, a first insulating film, an oxidation-resistant second insulating film, and a third insulating film formed by a CVD method are sequentially formed on a semiconductor substrate. Forming, forming a groove in the film at a position where a groove is to be formed, forming a groove in the semiconductor substrate by anisotropic etching using the third insulating film as an etching mask, Depositing a first polycrystalline semiconductor film on the upper surface of the substrate so as to be embedded in the groove, and planarizing the surface to the surface of the second insulating film; and depositing a second polycrystalline semiconductor film on the upper surface of the substrate When, on the second polycrystalline semiconductor film
A step of patterning so as to remain above the groove and on the element region of the substrate, a step of oxidizing the second polycrystalline semiconductor film to form an oxide film, and a step of oxidizing the second polycrystalline semiconductor film. Patterning the second insulating film using the oxide film of the semiconductor film as a mask, and forming the second insulating film patterned by this process.
Forming a field oxide film for device isolation at a predetermined position on the substrate by oxidizing the surface of the semiconductor substrate using the insulating film as a mask, and forming an oxide film for device isolation on the trench. It is characterized by the following.

Further, the method for manufacturing a semiconductor integrated circuit according to the present invention comprises the steps of: forming a first insulating film, an oxidation-resistant second insulating film, a first polycrystalline semiconductor film, an oxidation-resistant third film on a semiconductor substrate; Sequentially forming a fourth insulating film by a CVD method, a step of opening a position in each of the above films where a groove is to be formed, and anisotropically using the fourth insulating film as an etching mask. Forming a groove in the semiconductor substrate by etching; and depositing a second polycrystalline semiconductor film on the upper surface of the substrate so as to be embedded in the groove, and planarizing the surface to the surface of the second insulating film; Removing the third insulating film, exposing the surface of the polycrystalline semiconductor film, patterning the second polycrystalline semiconductor film, and oxidizing the second polycrystalline semiconductor film Forming a film, and forming an acid on the second polycrystalline semiconductor film. Patterning the second insulating film by using the film as a mask, and oxidizing the surface of the semiconductor substrate by using the second insulating film patterned by this process as a mask, thereby forming a device isolation element at a predetermined position on the substrate. Forming a field oxide film and forming an oxide film for element isolation on the trench.

[0022]

When forming an element isolation region, it is possible to simultaneously form an element isolation region of a field oxide film which is narrower than the minimum dimension determined by the resolution of exposure and a trench-shaped deep element isolation region. Further, it is possible to prevent abnormal oxidation from occurring at the time of forming the oxide film for element isolation, and to improve the production yield.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1A to 1D and FIGS. 2A to 2D show a first example of a method of manufacturing a semiconductor integrated circuit according to the present invention.
4 illustrates a cross-sectional structure of a semiconductor wafer in a main step of a method for forming an element isolation region according to an example.

First, as shown in FIG. 1A, a first insulating film (for example, a thermal oxide film 11), a polycrystalline semiconductor film (for example, a polysilicon film 12) on a semiconductor substrate (for example, a silicon substrate 10), An oxidation-resistant second insulating film (for example, a silicon nitride film 13) and a third insulating film (for example, C
A VD oxide film 14) is sequentially formed. The polysilicon film 12 on the thermal oxide film may be omitted.

Next, a resist film is applied on the CVD oxide film 14, exposed, developed, and patterned to form a resist pattern 25. Then, using the resist pattern 25 as a mask, the CVD oxide film 14, the silicon nitride film 13, the polysilicon film 12, and the thermal oxide film 1 are formed.
By etching 1, a position where a groove is to be formed is opened to form an opening 15.

Next, as shown in FIG. 1B, after the resist pattern 25 is removed, the CVD oxide film 14 is removed.
Is used as an etching mask to form a groove 16 in the semiconductor substrate 10 by anisotropic etching using RIE.

Next, an insulating structure required for element isolation is formed in the groove 16. In this case, an insulating film may be formed on at least the inner peripheral surface of the groove. In this example, polysilicon is buried in the groove 16 and the polysilicon is
It is assumed that the conductive material is used in order to use the zero electrode lead.

Therefore, first, a thermal oxide film 17 is formed in the trench 16 by thermal oxidation, and then ions of a P-type impurity such as boron are implanted, and a P + diffusion layer 18 for a channel stopper is formed at the bottom of the trench. Form. Next, a polysilicon film is deposited on the upper surface of the substrate so as to be thinner (for example, about 150 nm) than the width of the groove 16. Then, as shown in FIG.
Etch-back is performed by anisotropic etching to leave the polysilicon 19 on the side surface of the groove 16 in the polysilicon film.

Next, by removing the bottom portion of the groove of the thermal oxide film 17 by wet etching using ammonium fluoride or the like, the P for the channel stopper on the bottom surface of the groove is removed.
+ A part of the diffusion layer 18 is exposed. This makes it possible to make contact between the polysilicon deposited in the trench in a later step and the exposed portion (substrate) of the P + diffusion layer 18.

Next, as shown in FIG.
6, a first polycrystalline semiconductor film (for example, a polysilicon film 20) is deposited on the upper surface of the substrate to a thickness of about 2 μm. Then, ions of a P-type impurity such as boron are implanted into the polysilicon 20 to convert the polysilicon 20 into a conductor. Next, as shown in FIG. 2A, the upper surface of the polysilicon film 20 is planarized so as to coincide with the surface of the silicon nitride film 13.

At this time, first, the polysilicon film 20 is removed by a surface polishing method or the like until the surface of the CVD oxide film 14 is exposed. Further, the CVD oxide film 14 is removed by etching using ammonium fluoride or the like. In this state, the upper portion of the polysilicon 20 filling the groove 16 is in a state of protruding from the upper surface of the substrate. Further, the polysilicon film 20 is removed again by the surface polishing method until the surface of the silicon nitride film 13 is exposed, so that the upper surface of the polysilicon 20 filling the trench 16 and the surface of the silicon nitride film 13 are removed. Becomes flat.

Next, as shown in FIG. 2B, a second polycrystalline semiconductor film (for example, a polysilicon film 21) having a thickness of about 300 nm is deposited on the upper surface of the substrate. Then, a resist film (not shown) is applied on the polysilicon film 21, exposed and developed to be patterned, and the polysilicon film 21 is subjected to anisotropic etching using RIE using the resist pattern as a mask. Perform patterning.

Next, as shown in FIG. 2C, the polysilicon film 21 is oxidized to form an oxide film 22 having a thickness of about 900 nm. Then, the silicon nitride film 13 is patterned using the oxide film 22 as a mask. In this case, since the volume of the polysilicon film 21 increases when the polysilicon film 21 becomes the oxide film 22, the interval S 'between the adjacent silicon nitride films 13 can be made smaller than the minimum dimension determined by the exposure resolution. .

Next, as shown in FIG. 2D, using the patterned silicon nitride film 13 as a mask, the surface of the semiconductor
By performing thermal oxidation to a thickness of 00 nm, a field oxide film 23 for element isolation is formed at a predetermined position on the substrate, and an oxide film 24 for element isolation is formed on the trench.
After that, the silicon nitride film 13 is removed.

According to the method of manufacturing the element isolation region according to the first embodiment as described above, the element isolation region formed by the field oxide film 23 which is narrower than the minimum dimension S determined by the exposure resolution and the trench-shaped deep element isolation region. 24 can be formed simultaneously.

FIGS. 3A to 3C show cross-sectional structures of a semiconductor wafer in main steps of a method of forming an element isolation region according to a second embodiment of the method of manufacturing a semiconductor integrated circuit of the present invention. I have. In this step, a part of the steps described above with reference to FIGS. 1A to 1D and FIGS. 2A to 2D is modified as described below.

The step shown in FIG. 3A is performed by the steps shown in FIGS.
And (c). At this time, a first insulating film (for example, a thermal oxide film 11), a polysilicon film 12 (may be omitted), and an oxidation-resistant second insulating film (for example, on a semiconductor substrate (for example, a silicon substrate 30)). A first silicon nitride film 13), a first polycrystalline semiconductor film (for example, a first
Polysilicon film 31), an oxidation-resistant third insulating film (for example, a second silicon nitride film 32), and a fourth
Is changed so that the insulating film (for example, the CVD oxide film 14) is sequentially formed. Then, using the resist pattern as a mask, the CVD oxide film 14, the second silicon nitride film 32,
First polysilicon film 31, first silicon nitride film 1
3. By etching the polysilicon film 12 and the thermal oxide film 11, the position where the groove 16 is to be formed is changed to form an opening. Next, the step of FIG. 3B is performed according to the steps of FIG. 1D and FIGS. 2A and 2B.

At this time, after a second polysilicon film 33 is deposited on the upper surface of the substrate so as to fill the groove 16, the upper surface of the second polysilicon film 33 is covered with the second silicon nitride film 3.
The surface is flattened so as to coincide with the surface of No. 2. That is, first, the second polysilicon film 33 is removed until the surface of the CVD oxide film 14 is exposed. Further, the CVD oxide film 1
4 is removed. Next, the second polysilicon film 33 is removed until the surface of the second silicon nitride film 32 is exposed. As a result, the upper surface of the second polysilicon 33 filling the trench 16 and the surface of the second silicon nitride film 32 become flat.

Further, the second silicon nitride film 32 is removed to expose the surface of the first polysilicon film 31. Then, the first polysilicon film 31 is patterned.

Next, the step of FIG. 3 (c) is performed according to the steps of FIGS. 2 (c) and 2 (d). At this time, the first
The polysilicon film 31 is oxidized to form an oxide film 22,
Using the oxide film 22 as a mask, the first silicon nitride film 13 is patterned.

According to the method of manufacturing the element isolation region according to the second embodiment, similarly to the first embodiment, the element isolation region formed by the field oxide film, which is narrower than the minimum dimension S determined by the exposure resolution, and the groove type. A deep isolation region can be formed at the same time.

Further, as shown in FIG. 3A, even when the step A is present on the substrate surface, when the second polysilicon film 33 is planarized, the second silicon nitride Since the film 32 and the first polysilicon film 31 exist, no damage occurs to the underlying first silicon nitride film 13. Therefore, there is an advantage that abnormal production does not occur when an oxide film for element isolation is formed in a later step, and the production yield is improved.

[0044]

As described above, according to the method of manufacturing a semiconductor integrated circuit of the present invention, when forming an element isolation region, the element isolation region formed by a field oxide film that is narrower than the minimum dimension determined by the exposure resolution and the trench shape are formed. And an element isolation region having a large depth can be formed at the same time. Further, even when a stepped portion exists on the substrate surface, abnormal oxidation is prevented from occurring at the time of forming the oxide film for element isolation, and the production yield can be improved.

[Brief description of the drawings]

FIG. 1 is a view showing a cross-sectional structure of a semiconductor wafer in a step of a method of forming an element isolation region according to a first embodiment of a method of manufacturing a semiconductor integrated circuit of the present invention.

FIG. 2 is a view showing a cross-sectional structure of the semiconductor wafer in a step following the step of FIG. 1;

FIG. 3 is a view showing a cross-sectional structure of a semiconductor wafer in a step of a method of forming an element isolation region according to a second embodiment of the method of manufacturing a semiconductor integrated circuit of the present invention.

FIG. 4 is a cross-sectional view showing a cross-sectional structure of a semiconductor wafer in a main step of a conventional method for forming an element isolation region of a semiconductor integrated circuit.

[Explanation of symbols]

Reference numerals 10, 30: silicon substrate, 11: first insulating film (thermal oxide film), 13, 32: oxidation-resistant insulating film (silicon nitride film), 14: CVD oxide film, 15: opening, 16 ... groove,
17: thermal oxide film, 18: diffusion layer for channel stopper, 19: polysilicon on groove side face, 20: first polysilicon, 21: second polysilicon film, 22: oxide film,
Reference numeral 23 denotes a field oxide film, 24 denotes an oxide film for element isolation on a groove, 31 denotes a first polysilicon film, and 33 denotes a second polysilicon.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-188648 (JP, A) JP-A-2-54560 (JP, A) JP-A-63-25947 (JP, A) 177045 (JP, A) JP-A-61-107736 (JP, A) JP-A-60-54453 (JP, A) JP-A-60-10748 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 21/76 H01L 21/316

Claims (2)

(57) [Claims] A step of sequentially forming a first insulating film, an oxidation-resistant second insulating film, and a third insulating film by a CVD method on a semiconductor substrate; and forming a groove among the films. Opening a position; forming a groove in the semiconductor substrate by anisotropic etching using the third insulating film as an etching mask; and forming a first polycrystalline semiconductor film so as to be embedded in the groove. deposited on the upper surface of the substrate, planarizing to the surface of the second insulating film, depositing a second polycrystalline semiconductor film on the substrate top surface, said second polycrystalline semiconductor film above the groove upper and Of the above substrate
Patterning so as to remain on the element region; oxidizing the second polycrystalline semiconductor film to form an oxide film; and using the oxide film of the second polycrystalline semiconductor film as a mask to form the second polycrystalline semiconductor film. Patterning the insulating film, and oxidizing the surface of the semiconductor substrate using the second insulating film patterned in this step as a mask,
Forming a field oxide film for device isolation at a predetermined position on the substrate and forming an oxide film for device isolation on the trench. 2. A first insulating film, an oxidation-resistant second insulating film, a first polycrystalline semiconductor film, an oxidation-resistant third insulating film, and a fourth insulating film formed by a CVD method on a semiconductor substrate. A step of sequentially forming a film; a step of forming a hole in each of the films where a groove is to be formed; and a step of forming a groove in the semiconductor substrate by anisotropic etching using the fourth insulating film as an etching mask. Depositing a second polycrystalline semiconductor film on the upper surface of the substrate so as to be embedded in the trench, and planarizing the surface to the surface of the third insulating film; removing the third insulating film; Exposing a surface of the first polycrystalline semiconductor film; patterning the first polycrystalline semiconductor film; oxidizing the first polycrystalline semiconductor film to form an oxide film; The second insulating layer is formed using the oxide film of the first polycrystalline semiconductor film as a mask. A step of patterning the film, by oxidizing the surface of the semiconductor substrate and the second insulating film patterned by the process as a mask,
Forming a field oxide film for device isolation at a predetermined position on the substrate and forming an oxide film for device isolation on the trench.