JPH0662284A - Noise removing device - Google Patents

Abstract

PURPOSE:To remove noise in the case of superimposing fine noise by outputting any specified value from an adder corresponding to the absolute value of difference between median and (N+1)th signal levels. CONSTITUTION:The f-fold average value of the signal level of an input signal is outputted from a low-pass filter part 31, the median g-fold signal level is outputted from a median filter part 32, and the h-fold (N+1)th signal level is outputted from a signal processing part 33. An adder 34 adds these outputs. The adder 34 is set so as to output a smoothed value when the absolute value of difference between median and (N+1)th signal levels is smaller than a prescribed first level and so as to output median when it is larger than a second level. Thus, this device is operated as the low-pass filter to the fine noise of a small amplitude and operated as the median filter to the pulse signal of a large amplitude. Thus, noise can be removed even to a signal superimposed the fine noise of which level is periodically changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise eliminating device for eliminating noise contained in a signal such as a video signal.

[0002]

2. Description of the Related Art Conventionally, a median filter has been used to remove noise contained in a video signal.

As shown in FIG. 12, for example, the median filter delays an input terminal 51 and an input signal (assumed to be sampled at a predetermined cycle) by a time (T) equal to the sampling cycle. Unit delay circuits 52 and 53,
Input signal, signal obtained by delaying input signal by T time, and 2T
The median value selection circuit 54 which selects and outputs the signal having the second highest level from the three signals delayed by time.
And an output terminal 55.

The input terminal 51 of this median filter
When a signal as shown in FIG. 13A is input to
An output signal as shown in FIG. In the output signal, the pulse noise 56 of the input signal is removed, and the information of the edge portion 57 of the input signal is retained.

However, as shown in FIG. 14 (a), when a signal whose amplitude periodically changes between positive and negative is input, the signal having the second highest level is selected from the three adjacent signals as the median value. When selected by the circuit 54, the level of the output signal becomes flat as shown in FIG.

Therefore, in order to solve this problem, Japanese Patent Laid-Open No. 2-29020 discloses a noise eliminator in which the median filter is provided with an additional circuit 61 as shown in FIG.

The adding circuit 61 comprises a first subtracting circuit 62, an amplitude limiting circuit 63 and a second subtracting circuit 64. The voltage value of the signal delayed by the time T in the delay circuit 52 is S
And the voltage value of the output signal of the median value selection circuit 54 is M, the subtraction circuit 62 outputs a voltage of (S−M), and the amplitude limiting circuit 63 outputs a voltage of (S−M) to k (S−). The voltage is converted to a voltage of M) and output, and the subtraction circuit 64 outputs (Sk (S-
M)), that is, the voltage of (1-k) S + kM is output to the output terminal 55a.

When the above k is set in accordance with (SM) as shown in FIG. 16B, for example, the amplitude limiting circuit 63
1 of the output voltage k (S−M) of FIG.
6 (a).

That is, for regions 65 and 67 and 67 in which | SM is small, k is set to 1 so that the output from the output terminal 55a becomes M,
Small amplitude small noise and large amplitude pulse noise are removed. On the other hand, for areas 66 and 66 in which | SM is medium, the output terminal 5 is set by setting k to 0.
The output from 5a is set to S so that necessary signals are not lost.

[0010]

However, in the above noise eliminator, as shown in FIG. 17A, a signal 68 in which the level monotonously increases and a signal in which minute noise whose level changes periodically are superimposed are superimposed. When 69 is input, M is always output, so that the output signal 70 has a wave as shown in FIG. 7B, and there is a problem that noise cannot be sufficiently removed.

[0011]

In order to solve the above-mentioned problems, a noise elimination device according to the invention of claim 1 finds a smoothed value of a signal level for 2N + 1 input signals which are sequentially input, and A low-pass filter section that outputs f times, a median of a signal level, and a median filter section that outputs g times of the signal level, a signal processing section that calculates the signal level of the (N + 1) th signal and outputs h times thereof, and a low-pass filter. An adder for adding the output of the filter unit, the output of the median filter unit, and the output of the signal processing unit is provided, and the above multipliers f, g, and h are the difference between the signal level of the median and the signal level of the (N + 1) th signal. It is set according to the absolute value. When the absolute value is smaller than the predetermined first level, the adder outputs a smoothed value, and when the absolute value is larger than the second level, the adder outputs To output Dian, it is characterized in that it is set.

In order to solve the above-mentioned problems, a noise removing device according to a second aspect of the present invention inputs a delay circuit that delays an input signal for a predetermined time, and an input signal and all output signals of the delay circuit. In a noise elimination device having a median value selection circuit that outputs a median value from input signals, the input signal and the signal delayed by half the total delay amount of all the delay circuits are excluded. An average value output circuit that inputs the output signals of all the delay circuits and outputs an average value, a first arithmetic circuit that inputs and operates the input signals and the output signals of all the delay circuits, and an output of the first arithmetic circuit And a first multiplier variable multiplier having a nonlinear characteristic,
A second arithmetic circuit for inputting the signal delayed by half the total delay amount of all the delay circuits and the median value output from the median value selection circuit, and an output of the second arithmetic circuit are input. A second multiplier variable multiplier having a nonlinear characteristic, an adder for adding the output of the average value output circuit, the output of the first multiplier variable multiplier and the output of the second multiplier variable multiplier are provided. The multipliers of the first and second multiplier variable multipliers are determined by the control signal output from the second arithmetic circuit,
When the control signal is smaller than a predetermined first level, the adder outputs an average value, and when the absolute value is larger than the second level, the adder outputs a median. I am trying.

[0013]

According to the structure of claim 1, the multipliers f, g and h are
It is set according to the absolute value of the difference between the median and the signal level of the (N + 1) th signal. When the absolute value is smaller than the predetermined first level, the adder outputs a smoothed value and the absolute value is the second value. If it is larger than the level of, the adder is set to output the median, so it works as a low-pass filter for small amplitude small noise and a median filter for large amplitude pulsed noise. Work as. This makes it possible to remove noise even when a signal on which minute noise whose level changes periodically is superimposed is input.

According to the structure of claim 2, the first and second
The multiplier of the multiplier variable multiplier is determined by the control signal output from the second arithmetic circuit, and when the control signal is smaller than the predetermined first level, the adder outputs the average value and the absolute value is the second value. If it is larger than the level, the adder is set so as to output the median, and thus the adder operates similarly to claim 1.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.

The noise eliminator of this embodiment has a signal input terminal 1 as shown in FIG. The signal is a digital signal in which an analog signal such as a video signal is sampled at a predetermined sampling frequency and quantized into an appropriate number of bits.

The noise elimination device further includes delay circuits 2, 3
And a median filter 11 including the median selection circuit 4. The delay circuits 2 and 3 delay the input signal for a time (T) equal to the sampling period (the reciprocal of the sampling frequency).
Selects the signal having the second highest level from the three signals of the input signal, the signal obtained by delaying the input signal by T time, and the signal obtained by delaying the input signal by 2T time, and outputs the selected signal.

The noise elimination device further includes an average value output circuit 5, first and second arithmetic circuits 6 and 7, multipliers 8 (first multiplier variable multipliers) and 9 (first multiplier variable multipliers). vessel)
And an adder 10.

The average value output circuit 5, as shown in FIG.
It is composed of an adder 13 and a division circuit 14. Assuming that the input signal of the input terminal 1 and the output signals of the delay circuits 2 and 3 are X ₋₁ , X ₀ , and X ₊₁ at a certain time, X ₋₁ and X ₊₁ are input to the adder 13, (X _-1 + X ₊₁ ) is output. The division circuit 14 outputs (X ₋₁ + X ₊₁ ) / 2 to the adder 10.

As shown in FIG. 3, the arithmetic circuit 6 comprises subtractors 15 and 16, an adder 17, and a division circuit 18. X ₋₁ and X ₀ are input to the subtractor 15, and (X
_0- X _-1 ) is output. X ₀ and X ₊₁ are input to the subtractor 16, and (X ₀ −X ₊₁ ) is output. S1 from the subtractor 15 and S2 from the subtractor 16 are input to the adder 17, and (S1 + S2) is output. Where S1 =
(X ₀ -X _-1) and then, S2 = was (X ₀ -X _+1). The division circuit 18 outputs (S1 + S2) / 2 to the multiplier 8.

As shown in FIG. 4, the arithmetic circuit 7 comprises a subtractor 19 and an absolute value circuit 20. Subtractor 19
M from X ₀ and the median selection circuit 4 from the delay circuit 2 in
Is input, and (m−X ₀ ) is the absolute value circuit 20 and the multiplier 9
Is output to. Here, m is the second highest level of X _-1 , X ₀ , and X ₊₁ . The absolute value circuit 20 is | m
Output -X ₀ | to the multipliers 8 and 9.

In the multiplier 8, (S1 +
S2) / 2 and | m−X ₀ | from the arithmetic circuit 7 are input, and A (S1 + S2) / 2 is output to the adder 10. A
Is determined according to | m−X ₀ |, as described later.

In the multiplier 9, (m-X from the arithmetic circuit 7
₀ ) and | m−X ₀ | from the arithmetic circuit 7 are input, and B
(M−X ₀ ) is output to the adder 10. B is determined according to | m−X ₀ | as described later.

The adder 10 has (X _-1 + X ₊₁ ) / 2 from the average value output circuit 5 and A (S1 + S) from the multiplier 8.
2) / 2 and B (m−X ₀ ) from the multiplier 9 are input, and F is output from the output terminal 12. Here, F = A · (S1 + S2) / 2 + (X ₋₁ + X ₊₁ ) / 2 + B · (m−X ₀ ).

A method of determining the above A and B will be described with reference to FIG.

It is assumed that | m−X ₀ | output from the arithmetic circuit 7 is proportional to the noise level. And | m−X
_{When 0} | is smaller than a certain level (hereinafter, referred to as a first level), it is determined as small amplitude small noise, and | m−X ₀ | is a certain level (hereinafter, referred to as a second level) different from the first level. If it is larger than the level (1), it is determined to be large-amplitude pulse noise. A and B are determined according to the determination result.

As an example, graphs obtained by plotting A and B with respect to | m−X ₀ | are shown in FIGS. 5 (a) and 5 (b), respectively.

In the multiplier 8, A is set to 1/2 when | m−X ₀ | <M1, and A is set to 1 when | m−X ₀ |> M2. In the multiplier 9, | m−X ₀
| <M3, B is set to 0, and | m−X ₀ |>
When M4, B is set to 1. Mmax in the figure is
It is the maximum value of | m−X ₀ |. M1 corresponds to the above first level and M4 corresponds to the above second level.

M1, M2, M3 and M4 must satisfy the following conditions. That is, if the function between M1 and M2 is f (x) and the function of M3 and M4 is g (y), then M1 ≦ M2, M1 ≦ x ≦ M2, f (M1) = 1/2, f
(M2) = 1 M3 ≦ M4, M3 ≦ y ≦ M4, g (M3) = 0, g (M
4) = 1 M1 ≦ M2 <M3 ≦ M4 Therefore, when | m−X ₀ | <M1, it is determined to be a small amplitude small noise, and A = 1/2 and B = 0 are set. In this case, F = (S1 + S2) / 4 + (X -1 + X +1) / 2 = ((X 0 -X -1) + (X 0 -X +1)) / 4+ (X -1 + X +1) / 2 = (X _-1 + 2X ₀ + X ₊₁ ) / 4. Therefore, the noise elimination apparatus of the present embodiment is FIR
It operates as a (Finite-duration Impulse-Respons) type low-pass filter, and a signal obtained by smoothing the input signal is output from the output terminal 12.

When | m−X ₀ |> M4, it is determined to be large-amplitude pulse noise, and A = 1 and B = 1 are set.
In this case, F = (S1 + S2) / 2 + (X -1 + X +1) / 2 + (m-X 0) = ((X 0 -X -1) + (X 0 -X +1)) / 2+ (X ₋₁ + X ₊₁ ) / 2 + (m−X ₀ ) = m. Therefore, the noise eliminator of this embodiment operates as a conventional median filter, and a signal obtained by eliminating large-amplitude pulse noise from the input signal is output from the output terminal 12.

When M2 <| m−X ₀ | <M3, it is determined to be a signal component, and A = 1 and B = 0 are set. In this case, F = (S1 + S2) / 2 + (X -1 + X +1) / 2 = ((X 0 -X -1) + (X 0 -X +1)) / 2+ (X -1 + X +1) / 2 = X ₀ . Therefore, the input signal is output from the output terminal 12.

In the above noise eliminator, even if a signal 69 in which minute noise whose level changes periodically is superimposed is input to the signal 68 whose level monotonously increases as shown in FIG. As shown in FIG. 6B, it is possible to obtain the output signal 41 from which noise is almost removed.

The second embodiment of the present invention will be described below with reference to FIGS. 7 to 9. In addition,
For convenience of explanation, members having the same functions as the members shown in the drawings of the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In the noise eliminator of the present embodiment, as shown in FIG. 7, the configuration of the median value selection circuit 4a of the median filter 11a and the configuration of the first arithmetic circuit 6a are different from those of the previous embodiment.

As shown in FIG. 8, the median value selection circuit 4a is composed of arithmetic units 21 to 23, a selection logic 24, and a selector 25. X _{-1 in the} calculator 21
And X ₀ are input, and (X ₀ −X ₋₁ ) is output. X ₀ and X ₊₁ are input to the calculator 22, and (X ₀ −X ₊₁ ) is output. X ₋₁ and X ₊₁ are input to the calculator 23, and (X
₋₁ −X ₊₁ ) is output. In the select logic 24,
Output signals from the arithmetic units 21 to 23 are input, and a control signal of the selector 25 is output. X for selector 25
_-1 , X ₀ , X ₊₁ are input, and based on the control signal from the select logic 24, the median is selected from X _-1 , X ₀ , X ₊₁ and output.

The arithmetic circuit 6a is composed of an adder 26 and a division circuit 27 as shown in FIG. Adder 26
Is input with S1 (= X ₀ −X ₋₁ ) from the computing unit 21 and S2 (= X ₀ −X ₊₁ ) from the computing unit 22, and (S1
+ S2) is output. The division circuit 27 uses (S1 + S
2) / 2 is output to the multiplier 8.

As described above, in the present embodiment, S1 and S2 appearing in the middle of the arithmetic processing of the median selection circuit 4a are used, so that the arithmetic circuit 6 is compared with the above embodiment.
The configuration of a can be simplified. As a result, the cost of the noise eliminator can be reduced.

The third embodiment of the present invention will be described below with reference to FIGS. 10 and 11. For convenience of explanation, members having the same functions as those of the members shown in the drawings of the above-described embodiments are designated by the same reference numerals, and the description thereof will be omitted.

The noise eliminator of this embodiment is a generalization of the present invention, and differs from the above embodiment in that it selects and outputs the median of the signal level from the n signals.

As shown in FIG. 10, the noise eliminator comprises a low-pass filter section 31 and a median filter section 3.
2, a signal processing unit 33, and an adder 34. The low-pass filter unit 31 includes a smoothing circuit 31a and a first
Of the multiplier 31b. The median filter unit 32 includes a median filter 32a and a second multiplier 32b. The signal processing unit 33
The delay line 33a (delay circuit) and the second multiplier 3
2b.

The input terminal 1 of n _{signals, X - (n-1)} / 2, ···, X -1, X 0, X +1, ···, X
_{+ (n-1) / 2} is input to the smoothing circuit 31a, the median filter 32a, and the delay line 33a. However, n is an odd number.

The median filter 32a has n X
_{- (n-1) / 2} , ···, X -1, X 0, X +1, ···, X
_The (n + 1) / 2nd largest level (m) is selected from _{+ (n-1) / 2} and output to the multiplier 32b. In addition, the median filter 32a multiplies s by multipliers 31a to 31b.
Output to. Here, s = | m−X ₀ |. The multiplier 32b outputs g (s) · m to the adder 34. g
(S) is determined according to s as described later.

The smoothing circuit 31a outputs Σa _i X _i to the multiplier 31b. Here, − (n−1) / 2 ≦ i ≦
(N-1) / 2. a _i is a weighting factor set according to X _i , and Σa _i = 1. The multiplier 31b is
The f (s) · Σa _i X _i is output to the adder 34. f
(S) is determined according to s as described later.

The delay line 33a has n X
_{- (n-1) / 2} , ···, X -1, X 0, X +1, ···, X
_The (n + 1) / 2th X ₀ out of _{+ (n-1) / 2} is multiplied by the multiplier 3
Output to 3b. The multiplier 33b outputs h (s) · X ₀ to the adder 34. h (s) is s, as described later.
It is decided according to.

The output from the adder 34 is F = f (s) Σa _i X _i + g (s) m + h (s) X ₀

The above f (s), g (s), and h
A method of determining (s) will be described with reference to FIG.

It is assumed that s output from the median filter 32a is proportional to the noise level. If s is lower than a certain level (hereinafter, referred to as a first level), it is determined to be a small amplitude small noise, and s is higher than a certain level (hereinafter, referred to as a second level) different from the first level. If it is large, it is determined to be large-amplitude pulse noise. F (s), g (s), and h (s) are determined according to this determination result.

As an example, graphs in which f (s), g (s), and h (s) are plotted against s are shown in FIGS. 11 (a), (b), and (c), respectively.

In the multiplier 31b, when s <th1, f
(S) is set to 1, and when s> th1, f (s) is set to 0. In the multiplier 32b, g (s) is set to 0 when s <th2 and g (s) is set to 0 when s> th2.
(S) is set to 1. In the multiplier 33b, s <th
When 1, h (s) is set to 0 and th1 <s <th2
When h (s) is set to 1, when s> th2,
h (s) is set to 0. Note that th1 is the above first
, And th2 corresponds to the above second level.

That is, when s <th1, it is determined that the noise is of small amplitude and f (s) = 1, g (s) = 0, h
(S) = 0 is set. At this time, F = Σa _i X _i . Therefore, the noise elimination apparatus of the present embodiment is FIR
The output terminal 12 outputs a signal obtained by smoothing the input signal by operating as a low-pass filter of the type.

When th1 <s <th2, it is determined to be a signal component, and f (s) = 0, g (s) = 0, and h (s) = 1 are set. At this time, F = X ₀ . Therefore, the input signal is output from the output terminal 12.

When s> th2, f (s) = 0, g (s)
= 1 and h (s) = 0 are set. At this time, F = m. Therefore, the noise eliminator of this embodiment operates as a conventional median filter, and a signal obtained by eliminating large-amplitude pulse noise from the input signal is output from the output terminal 12.

[0053]

The noise eliminator according to the invention of claim 1
As described above, for the 2N + 1 input signals that are sequentially input, a low-pass filter unit that obtains the smoothed value of the signal level and outputs f times that, and a median filter that obtains the median of the signal level and outputs the median Department,
A signal processing unit that obtains the signal level of the N + 1th signal and outputs h times thereof, and an adder that adds the output of the low-pass filter unit, the output of the median filter unit, and the output of the signal processing unit are provided. The multipliers f, g, h of
It is set according to the absolute value of the difference between the median and the signal level of the (N + 1) th signal. When the absolute value is smaller than the predetermined first level, the adder outputs a smoothed value and the absolute value is the second value. If it is larger than the level of, the adder is set to output the median, so it works as a low-pass filter for small amplitude small noise and a median filter for large amplitude pulsed noise. Work as. As a result, it is possible to remove noise even when a signal on which minute noise whose level changes cyclically is superimposed is input.

As described above, the noise elimination device according to the second aspect of the present invention includes the output signals of all the delay circuits except the input signal and the signal delayed by half the total delay amount of all the delay circuits. Average value output circuit for inputting an average value and outputting an average value, a first arithmetic circuit for performing an arithmetic operation by inputting an input signal and output signals of all the delay circuits, and a non-linear characteristic by inputting an output of the first arithmetic circuit A first multiplier variable multiplier having: and a second arithmetic circuit that inputs a signal delayed by half the total delay amount of all the delay circuits and a median value output from the median value selection circuit to perform an operation. A second multiplier variable multiplier having a non-linear characteristic to which the output of the second arithmetic circuit is inputted, and an output of the average value output circuit, an output of the first multiplier variable multiplier and an output of the second multiplier variable multiplier are added. Is provided with an adder for Preliminary multiplier second multiplier variable multiplier,
If the control signal is determined by the control signal output from the second arithmetic circuit, and the control signal is smaller than the predetermined first level, the adder outputs an average value, and if the absolute value is larger than the second level, the adder outputs the average value. Since the median is set to be output, the same effect as that of claim 1 can be obtained.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention, and is a block diagram showing an overall configuration of a noise eliminator.

FIG. 2 is a block diagram showing a configuration of an average value output circuit of FIG.

3 is a block diagram showing a configuration of a first arithmetic circuit of FIG. 1. FIG.

4 is a block diagram showing a configuration of a second arithmetic circuit of FIG.

5 is a graph showing multipliers of the multiplier of FIG.

6 is an explanatory diagram showing an input signal and an output signal of the noise eliminator shown in FIG.

FIG. 7 shows a second embodiment of the present invention and is a block diagram showing an overall configuration of a noise eliminator.

8 is a block diagram showing a configuration of a median selection circuit of FIG.

9 is a block diagram showing a configuration of a first arithmetic circuit of FIG. 7. FIG.

FIG. 10 shows a third embodiment of the present invention and is a block diagram showing an overall configuration of a noise elimination device.

11 is a graph showing multipliers of the multiplier of FIG.

FIG. 12 is a block diagram showing a conventional median filter.

13 is an explanatory diagram showing the operation of the median filter of FIG.

FIG. 14 is an explanatory diagram showing an operation of the median filter of FIG.

FIG. 15 is a block diagram showing a conventional noise eliminator.

16 is a graph showing characteristics of the amplitude limiting circuit of FIG.

17 is an explanatory diagram showing an input signal and an output signal of the noise eliminator shown in FIG.

[Explanation of symbols]

 2 delay circuit 3 delay circuit 4 median selection circuit 5 average value output circuit 6 arithmetic circuit (first arithmetic circuit) 6a arithmetic circuit (first arithmetic circuit) 7 arithmetic circuit (second arithmetic circuit) 8 multiplier (first multiplier) Variable multiplier) 9 Multiplier (second multiplier variable multiplier) 10 Adder 11 Median filter 11a Median filter 31 Low pass filter section 31a Smoothing circuit 31b Multiplier 32 Median filter section 32a Median filter 32b Multiplier 33 Signal processing section 33a Delay line (delay circuit) 33b Multiplier 34 Adder 34

Claims (2)

[Claims] 1. A low-pass filter unit that obtains a smoothed value of a signal level for sequentially input 2N + 1 input signals and outputs f times that value, and a median filter that obtains a median of the signal level and outputs the median value thereof. Department and N
A signal processing unit that obtains the signal level of the + 1st signal and outputs h times thereof, and an adder that adds the output of the low-pass filter unit, the output of the median filter unit, and the output of the signal processing unit are provided. The multipliers f, g, and h are set according to the absolute value of the difference between the median and the signal level of the N + 1th signal, and when the absolute value is smaller than the predetermined first level, the adder outputs a smoothed value. , And the adder is set to output a median when the absolute value is larger than the second level. 2. A delay circuit for delaying an input signal for a predetermined time, and a median value selection circuit for inputting the input signal and all output signals of the delay circuit and outputting a median value from the input signals. An average value output circuit for inputting an input signal and an output signal of all delay circuits except a signal delayed by a delay amount of a half of the total delay amount of all the delay circuits, and outputting an average value. A first arithmetic circuit for performing an arithmetic operation by inputting an input signal and output signals of all the delay circuits; a first multiplier variable multiplier having an nonlinear characteristic by inputting the output of the first arithmetic circuit; Second arithmetic circuit for inputting a signal delayed by half the total delay amount of the delay circuit and the median value output from the median value selection circuit, and a non-linear circuit for inputting the output of the second arithmetic circuit Have the characteristics of A second variable multiplier,
An adder for adding the output of the average value output circuit, the output of the first multiplier variable multiplier, and the output of the second multiplier variable multiplier is provided, and the multipliers of the first and second multiplier variable multipliers are the second multiplier. If the control signal is determined by the control signal output from the arithmetic circuit, and the control signal is smaller than the predetermined first level, the adder outputs the average value, and if the absolute value is larger than the second level, the adder outputs the median. A noise canceller characterized by being set to output.