JPH0656857B2 - Method for manufacturing field effect transistor - Google Patents
Method for manufacturing field effect transistorInfo
- Publication number
- JPH0656857B2 JPH0656857B2 JP1125785A JP1125785A JPH0656857B2 JP H0656857 B2 JPH0656857 B2 JP H0656857B2 JP 1125785 A JP1125785 A JP 1125785A JP 1125785 A JP1125785 A JP 1125785A JP H0656857 B2 JPH0656857 B2 JP H0656857B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- insulating film
- opening
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title description 10
- 230000005669 field effect Effects 0.000 title description 6
- 238000000034 method Methods 0.000 title description 4
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、ヘテロ接合界面における高速電子を利用した
微細で、かつ寄生抵抗の小さい高性能電解効果トランジ
スタの製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a high-performance field effect transistor that uses fine electrons at a heterojunction interface and has a small size and a small parasitic resistance.
（従来技術とその問題点） GaAsとAlGaAsのヘテロ界面の高速な２次元電子チャネル
を用いた電解効果トランジスタ(FET)は、GaAs FETを越
える高速、高性能素子として、低雑音素子、および高速I
Cへの応用が盛んに研究されている。かかるFETをさらに
高性能化するためにはソース抵抗の低減が重要であり、
この一例として、第２図に断面構造で示すようにイオン
注入によってゲート外にn+領域を形成したものが報告さ
れている。アイトリプルイーエレクトロンデバイスレタ
ーズ（ＩＥ３Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｌｅｔ
ｔｅｒｓ）Vol.ＥＤＬ−５ ｐ１２９−１３１（１９８
４）参照。ここで５に高抵抗基板、４はアンドープGaAs
層、２はｎ型AlGaAs層よりなる第２の半導体層、８は耐
熱性のゲート電極、１１はn+層、９はソース電極、１０
はドレイン電極で、３は２次元電子チャンネルである。
このFETの製作工程は、ｎ−AlGaAs層上にＷ等の耐熱ゲ
ートを形成し、これをマスクとして例えばｎ型ドーパン
トとしてＳｉイオンを注入し、アニールを行ってn+領域
を形成した後、ソースおよびドレイン電極を形成するも
のである。しかしながら、第２の半導体層であるn-AlGa
As層の厚さが数100Åと薄いため、このような浅い所へ
の高ドースイオン注入は難しく、小さなシート抵抗すな
わち低ソース抵抗を得るのは困難であり、またシート抵
抗を小さくしようとして深く注入すればソース、ドレイ
ンのn+領域間距離が短い素子で、アンドープGaAs中への
注入電流が増大する結果、ドレインコンダクタンスの増
大やしきい値電圧のシフト等、いわゆる短チャネル効果
を起こしてしまう欠点がある。また高温でのアニール処
理を要するため、結晶品質の劣化を起こす欠点もある。
さらに、かかる耐熱ゲートは比較的抵抗が大きく、かつ
内部応力が大きいため、ゲート抵抗の増大や、信頼度の
低下などの恐れもあり、またかかるゲートは通常ドライ
エッチングによって形成されるが、サブミクロン化はま
だ難しく素子の微細化は困難な状況である。(Prior art and its problems) A field effect transistor (FET) that uses a high-speed two-dimensional electron channel at the hetero interface between GaAs and AlGaAs is a high-speed, high-performance device that surpasses GaAs FET, and is a low-noise device and a high-speed I
The application to C is being actively studied. In order to further improve the performance of such FET, it is important to reduce the source resistance.
As an example of this, it is reported that an n + region is formed outside the gate by ion implantation as shown in the sectional structure in FIG. Eye Triple E Electron Device Letters (IE 3 Electron Device Let)
ters) Vol.EDL-5 p129-131 (198)
See 4). Where 5 is a high resistance substrate and 4 is undoped GaAs
Layer, 2 is a second semiconductor layer made of an n-type AlGaAs layer, 8 is a heat-resistant gate electrode, 11 is an n + layer, 9 is a source electrode, 10
Is a drain electrode and 3 is a two-dimensional electron channel.
In the fabrication process of this FET, a heat resistant gate such as W is formed on the n-AlGaAs layer, Si ions are implanted as an n-type dopant using this as a mask, and annealing is performed to form an n + region. The drain electrode is formed. However, the second semiconductor layer, n-AlGa
Since the As layer is as thin as several hundred Å, it is difficult to implant high-dose ions in such a shallow place, it is difficult to obtain a small sheet resistance, that is, a low source resistance. For example, an element with a short distance between the source and drain n + regions has the drawback of causing so-called short channel effects such as increased drain conductance and threshold voltage shift, as a result of increased injection current into undoped GaAs. . Further, since annealing treatment at a high temperature is required, there is a drawback that crystal quality is deteriorated.
Furthermore, since such a heat-resistant gate has a relatively large resistance and a large internal stress, there is a risk that the gate resistance will increase and the reliability will decrease. In addition, such a gate is usually formed by dry etching. It is still difficult to miniaturize and it is difficult to miniaturize the device.
（発明の目的） 本発明は、ヘテロ界面における高速２次元電子を利用す
る電解効果トランジスタにおいて、以上のような従来技
術における素子構造および性能の限界を打破する微細か
つ高性能なトランジスタをセルフアラインで量産性良く
製造する方法を提供するものである。(Object of the Invention) The present invention is a field effect transistor utilizing high-speed two-dimensional electrons at a hetero interface, which is a self-aligned fine and high-performance transistor that breaks down the device structure and performance limit of the prior art as described above. It is intended to provide a method of manufacturing with high mass productivity.
（発明の構成） 本発明によれば高抵抗基板上に高純度の第１の半導体層
および該第１の半導体層より電子親和力のの小さいｎ型
の第２の半導体層を少くとも順次成長し、該成長層表面
にソースおよびドレイン領域を開口するマスクを形成
し、次いで該開口部の前記成長層をエッチングして、第
１の半導体層を露出させた後、該開口部にn+コンタクト
層を該マスク上面より高く、かつ側面がほぼ垂直になる
ように選択エピタキシャル成長し、該マスクを除去して
全面に絶縁膜を被着した後、垂直方向よりドライエッチ
ングを行って該n+コンタクト層側面のみに前記絶縁膜を
残置し、かつゲート開口部を形成し、次にソース−ドレ
イン領域間の前記絶縁膜開口にゲート電極を形成するこ
とを特徴とする電解効果トランジスタの製造方法が得ら
れる。(Structure of the Invention) According to the present invention, a high-purity first semiconductor layer and an n-type second semiconductor layer having an electron affinity lower than that of the first semiconductor layer are grown at least sequentially on a high-resistance substrate. Forming a mask for opening source and drain regions on the surface of the growth layer, etching the growth layer in the opening to expose the first semiconductor layer, and then forming an n + contact layer in the opening. Selective epitaxial growth is performed so that it is higher than the upper surface of the mask and the side surfaces thereof are substantially vertical, the mask is removed and an insulating film is deposited on the entire surface, and then dry etching is performed from the vertical direction to only the side surface of the n + contact layer. A method for manufacturing a field effect transistor, characterized in that the insulating film is left, a gate opening is formed, and then a gate electrode is formed in the insulating film opening between the source and drain regions.
（構成の詳細な説明） 以下第１図の断面構造を参照しつつ本発明の構成および
効果について記述する。(Detailed Description of Configuration) The configuration and effects of the present invention will be described below with reference to the sectional structure of FIG.
まず第１図(a)に示すように高抵抗基板５上に第１の半
導体層4,第２の半導体層２をMBEにて連続して積層した
（100）基板上にFETに流れる電流が（011）方向になる
ようにゲート部に絶縁膜を後から選択成長させるn+層の
第一の半導体層の表面からの高をｄとすると0.4d以上の
高さに形成しパターニングする。次に少なくとも２次元
電子ガスのチャネルが存在する深さまでエッチングを行
なう(b)。First, as shown in FIG. 1 (a), the first semiconductor layer 4 and the second semiconductor layer 2 are successively stacked on the high resistance substrate 5 by MBE. An insulating film is selectively grown on the gate portion so as to be in the (011) direction. If the height from the surface of the first semiconductor layer of the n + layer to be selectively grown later is d, it is formed to a height of 0.4d or more and patterned. Next, etching is performed to a depth where at least a two-dimensional electron gas channel exists (b).
次に(c)に示すように選択成長によりn+層を第一の半導
体層の表面からの高さがｄとなるように成長させ、その
後マスクの絶縁膜を除去する。Next, as shown in (c), the n + layer is grown by selective growth so that the height from the surface of the first semiconductor layer is d, and then the insulating film of the mask is removed.
これにより図１(c)のような垂直な側面をもつ選択成長
層が得られる。As a result, a selective growth layer having vertical side surfaces as shown in FIG. 1 (c) is obtained.
次に(d)に示すようにマスク絶縁膜を除去した後、全面
に絶縁膜を形成する。次に(e)に示すように垂直方向の
異方性エッチングにより絶縁膜をn+層側壁にのみ残して
除去する。次に(f)に示すように金属電極を付着する。
そして(g)に示すようにゲート部以外の金属を除去す
る。このときゲート金属はn+コンタクト層とは絶縁され
ている。この方法により耐熱性ゲート金属を用いなくと
もセルフアラインでさらに微細な寸法の耐圧のすぐれた
電解効果トランジスタを量産性よく製造することが可能
となった。Next, as shown in (d), after removing the mask insulating film, an insulating film is formed on the entire surface. Next, as shown in (e), the insulating film is removed by anisotropic etching in the vertical direction leaving only the side wall of the n + layer. Next, a metal electrode is attached as shown in (f).
Then, as shown in (g), the metal other than the gate portion is removed. At this time, the gate metal is insulated from the n + contact layer. With this method, it becomes possible to manufacture a field-effect transistor having a finer dimension and a higher withstand voltage by self-alignment with good mass productivity without using a heat-resistant gate metal.
（実施例１） 半絶縁性GaAs基板上にMBEにより第１の半導体層として
キャリア密度約１×1014cm-3,厚さ１μｍのPGaAs層を成
長し、さらに素子の安定化をはかるため第１の半導体層
であるGaAs層の界面から厚さ20ÅノンドープAl0.3Ga0.7
As層100Åのｎ型Al0.3Ga0.7As層、厚さ200ÅでAlとAsの
モル比が０．３から０へと変化している。nAlxGa1-xAs
層および厚さ200Åのｎ型GaAs層を順次成長させたウェ
ハを用い、絶縁膜として厚さ1000ÅのSiO2を用い電子ビ
ーム露光にてn+コンタクト間隔0.9μｍのマスクを形成
し、NaOH/H2O2系のウエットエッチングにより1000Å基
板をエッチングした後、ハイドライド系VPEで基板温度6
50℃にてn+GaAsキャリア密度約6×1018cm-3を約3000Å
ゲート端で垂直になるように成長させた。次にマスクを
除去し全面にSio2をn+コンタクト層側壁の厚さが0.2μ
ｍになるように付着させ、ＣＦ４の異方性ドライエッチ
によりn+層側壁にのみ絶縁膜を除し、その後Alを全面に
蒸着し、ゲート部以外のAlをエッチングでとり除きFETを
製作した。これにより比抵抗の小さいAlを用い、耐圧が
すぐれた選択エピn+コンタクトFETの電極間隔が同一の
選択エピ用パターニング寸法に対して短かくすぐれた特
性を示したものが量産性よく製作できた。Example 1 A PGaAs layer having a carrier density of about 1 × 10 14 cm −3 and a thickness of 1 μm was grown as a first semiconductor layer on a semi-insulating GaAs substrate by MBE to further stabilize the device. 20 Å non-doped Al0.3Ga0.7 from the interface of the GaAs layer which is the semiconductor layer of No. 1
The n-type Al0.3Ga0.7As layer of 100 Å As layer, the thickness of 200 Å, the molar ratio of Al and As changes from 0.3 to 0. nAlxGa 1-x As
The wafer having an n-type GaAs layer of the layer and the thickness of 200Å is successively grown, the mask of the n + contact spacing 0.9μm was formed by electron beam exposure using SiO 2 having a thickness of 1000Å as the insulating film, NaOH / H 2 After etching 1000Å substrate by O 2 system wet etching, substrate temperature 6 with hydride VPE
N + GaAs carrier density of approx. 6 × 10 18 cm -3 at 50 ° C approx.
It was grown to be vertical at the gate edge. Next, the mask is removed, and Sio 2 is applied to the entire surface to make the side wall of the n + contact layer 0.2 μm thick.
Then, the insulating film was removed only on the sidewalls of the n + layer by anisotropic dry etching of CF 4 , and then Al was vapor-deposited on the entire surface, and Al except for the gate portion was removed by etching to manufacture a FET. . As a result, it was possible to mass-produce a selective epi-type n + contact FET having a high withstand voltage and having a short and excellent characteristic with respect to the patterning dimension for the selective epi having the same electrode interval.
更に本実施例で製作されたFETの絶縁膜を除去しソース
−ゲート間及びゲート・ドレイン間の容量を減少させる
ことができる。これにより高速、高周波特性はさらに向
上した。Furthermore, the insulating film of the FET manufactured in this embodiment can be removed to reduce the capacitance between the source and gate and between the gate and drain. As a result, high speed and high frequency characteristics were further improved.
（発明の効果） 以上本発明によれば選択成長FET製作方法においてセル
フアラインでn+コンタクト層と絶縁された微細なゲート
電極を有するFETが容易に製造でき高性能化、量産化が
可能となった。As described above, according to the present invention, a FET having a fine gate electrode insulated from an n + contact layer by self-alignment can be easily manufactured in the selective growth FET manufacturing method, and high performance and mass production are possible. .
第１図は本発明による選択エピタキシャルｎ＋コンタク
トセルフアラインFETの製造工程を示す構造断面図であ
る。 ここで １：マスク、２：第２の半導体層 ３：２次元電子チャネル、４：第１の半導体層 ５：高抵抗基板、６：ｎ＋層 ７：絶縁膜、８：ゲート金属 ９：オーミック電極 第２図は従来イオン注入によってゲート外にｎ＋領域を
形成されたFETの断面構造図で、 ４：アンドープGaAs、５：高抵抗基板 ８：ゲート電極、９：ソース電極 １０：ドレイン電極、11：ｎ＋層FIG. 1 is a structural sectional view showing a manufacturing process of a selective epitaxial n + contact self-aligned FET according to the present invention. Here, 1: mask, 2: second semiconductor layer 3: two-dimensional electron channel, 4: first semiconductor layer 5: high resistance substrate, 6: n + layer 7: insulating film, 8: gate metal 9: ohmic electrode FIG. 2 is a cross-sectional structural view of an FET in which an n + region is formed outside the gate by conventional ion implantation, 4: undoped GaAs, 5: high resistance substrate 8: gate electrode, 9: source electrode 10: drain electrode, 11: n + layer
Claims (1)
よび該第１の半導体層より電子親和力の小さいｎ型の第
２の半導体層を少くとも順次成長し、該成長層表面にソ
ースおよびドレイン領域を開口するマスクを形成し、次
いで該開口部の前記成長層をエッチングして、第１の半
導体層を露出させた後、該開口部にｎ＋コンタクト層を
該マスク上面より高く、かつ側面がほぼ垂直になるよう
に選択エピタキシャル成長し、該マスクを除去して全面
に絶縁膜を被着した後、垂直方向よりドライエッチング
を行って該ｎ＋コンタクト層側面のみに前記絶縁膜を残
置し、かつゲート開口部を形成し、次にソース−ドレイ
ン領域間の前記絶縁膜開口にゲート電極を形成すること
を特徴とする電界効果トランジスタの製造方法。1. A high-purity first semiconductor layer and an n-type second semiconductor layer having an electron affinity lower than that of the first semiconductor layer are grown at least sequentially on a high-resistance substrate, and the growth layer surface is formed. After forming a mask for opening the source and drain regions and then etching the growth layer in the opening to expose the first semiconductor layer, an n + contact layer in the opening is higher than the mask top surface, Further, selective epitaxial growth is performed so that the side surface becomes almost vertical, the mask is removed, and an insulating film is deposited on the entire surface, and then dry etching is performed from the vertical direction to leave the insulating film only on the side surface of the n + contact layer. And a gate opening is formed, and then a gate electrode is formed in the insulating film opening between the source and drain regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1125785A JPH0656857B2 (en) | 1985-01-24 | 1985-01-24 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1125785A JPH0656857B2 (en) | 1985-01-24 | 1985-01-24 | Method for manufacturing field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61170072A JPS61170072A (en) | 1986-07-31 |
| JPH0656857B2 true JPH0656857B2 (en) | 1994-07-27 |
Family
ID=11772882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1125785A Expired - Lifetime JPH0656857B2 (en) | 1985-01-24 | 1985-01-24 | Method for manufacturing field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0656857B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2591162B2 (en) * | 1989-06-06 | 1997-03-19 | 富士通株式会社 | Method of manufacturing semiconductor device and semiconductor device manufactured thereby |
| JPH06244216A (en) * | 1992-12-21 | 1994-09-02 | Mitsubishi Electric Corp | Ipg transistor and manufacture thereof, and semiconductor integrated circuit device and manufacture thereof |
-
1985
- 1985-01-24 JP JP1125785A patent/JPH0656857B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61170072A (en) | 1986-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5373191A (en) | Semiconductor device and method of producing the same | |
| JPH11243058A (en) | Semiconductor device and manufacture thereof | |
| US5231040A (en) | Method of making a field effect transistor | |
| US4994868A (en) | Heterojunction confined channel FET | |
| US4962050A (en) | GaAs FET manufacturing process employing channel confining layers | |
| JPH0656857B2 (en) | Method for manufacturing field effect transistor | |
| US5274257A (en) | Floating channel field effect transistor and a fabricating method thereof | |
| JPH08330325A (en) | Fabrication of field effect transistor | |
| JPS60251671A (en) | Field-effect type transistor and manufacture thereof | |
| US5698871A (en) | Heterojunction bipolar transistor | |
| JPH0523497B2 (en) | ||
| JPH0789586B2 (en) | Semiconductor device | |
| JPS63232374A (en) | Semiconductor device | |
| JPS6115375A (en) | Hetero junction fet | |
| GB2239557A (en) | High electron mobility transistors | |
| JPH02189978A (en) | Fine wiring field effect transistor and manufacture thereof | |
| JP3077653B2 (en) | Field effect transistor and method of manufacturing the same | |
| JP2526492B2 (en) | Method for manufacturing semiconductor device | |
| JPS63287058A (en) | Manufacture of hetero-junction bipolar transistor | |
| JPS63228762A (en) | Manufacture of semiconductor device | |
| JPH0992816A (en) | Field-effect transistor and its manufacture | |
| KR950001167B1 (en) | Compound semiconductor device and manufacturing method thereof | |
| KR950001168B1 (en) | Compound semiconductor device and manufacturing method thereof | |
| JP2738690B2 (en) | Heterojunction field effect transistor | |
| JPH0758715B2 (en) | Method for manufacturing field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |