JPH0628305B2 - Master slice LSI - Google Patents

Description

The present invention relates to a master slice LSI, and more particularly to a master slice LSI capable of mounting logic cells such as memory cells at a high density.

[Prior Art] In a conventional master slice LSI, in particular, a so-called spread type master slice LSI in which basic cells made of active elements are spread over the entire surface of a chip, an arbitrary basic cell area is formed between logic cells such as memory cells. It was used as a wiring area. Such a spread-type master slice LSI is, for example, a Hideki Fuk.
uda et al. By 1982 Symposi
um on VLSI Technology Dig
est of Technical Papers p. 16-17 "A CMOS Pair-Tran
Sister Array Masterslice ”
Are disclosed in.

FIG. 2 is a wiring diagram showing an internal area of an example of such a conventional master slice LSI of the spreading method.

First, the configuration of the conventional spread master slice LSI shown in FIG. 2 will be described. In FIG.
A large number of basic cells 2 composed of bipolar transistors and resistors or MOS transistors are arranged in a plurality of columns over the entire surface of the semiconductor chip 1, and between adjacent columns of these plurality of columns, A gap 3 having a predetermined interval is formed. Furthermore, in any of these columns, the number of basic cells in that column constitutes various logic cells 4, such as memory cells. These logic cells 4 are connected to each other through a large number of through holes 7 by a large number of vertical Al1 layer wirings 5 and horizontal direction Al2 layer wirings 6 in a basic cell region where the logic cells 4 are not formed. .

Next, the operation of the conventional master slice LS1 shown in FIG. 2 will be described. In the master slice LS1 shown in FIG. 2, a logic cell 4 such as a memory cell is formed at a predetermined position of a predetermined basic cell row in the basic cell area according to a predetermined rule at the time of manufacturing, and another basic cell area is formed. May be used as a wiring area between logic cells. Therefore, as shown in the upper area of FIG. 2, by considering the layout so as to optimize the number of basic cell columns used as the wiring area, it is possible to use both the logic cells and the wiring areas in the basic cell area. It was possible to obtain a desired highly integrated master slice LSI without generating a wasteful personal use area that is not used.

[Problems to be Solved by the Invention] Since the conventional master-slice LSI of the spreading method is configured as described above, as shown in the lower region of FIG. 2, wiring such as a memory cell is performed. Even when a logic cell that requires an extremely small area is formed in the basic cell row, at least one entire basic cell area must be used as the wiring area, as indicated by A in FIG. However, the number of wires actually required is extremely smaller than the number of wires in one basic cell column, and a large unused area is generated in the basic cell area, which hinders high integration of the master slice LSI. there were.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a master slice LSI which realizes an improvement in the degree of integration without generating an unused wiring area.

[Means for Solving Problems] A master slice LSI according to the present invention has a plurality of basic cell regions in which a plurality of basic cells are formed in a row,
A gap having a predetermined interval is formed between adjacent columns of the columns of these basic cell regions, and a plurality of basic cells in a plurality of basic cell regions require a relatively large number of wirings between them. A first type logic cell is formed, and other arbitrary basic cells in a plurality of basic cell regions form a plurality of second type logic cells that require a relatively small number of wiring lines between them, Wiring regions for connecting the first type logic cells are formed in regions in which the first and second type logic cells are not formed in the plurality of basic cell regions, and the plurality of second type The wiring region for connecting the logic cells is configured to be formed in a region of a predetermined interval between adjacent ones of the plurality of basic cell regions on the semiconductor chip.

[Operation] In the master slice LSI according to the present invention, the area between the columns of the basic cell area is used as the wiring area in the portion where the logic cells are arranged so that the wiring area is extremely small, and the basic cell area is wired. In this portion, all the basic cells can be used as logic cells without being used as regions, and wiring between logic cells can be performed as usual.

[Embodiment of the Invention] FIG. 1 is a wiring diagram showing an internal area of an embodiment of a spread master slice LSI which is an embodiment of the present invention. The master slice LSI shown in FIG. 1 is a conventional master slice LSI shown in FIG. 2 except for the following points.
Is the same as. That is, in the embodiment shown in FIG. 1, as shown in the lower half area in FIG. 1, between the columns of the basic cell area in the periphery of the logic cell where the wiring area is extremely small. A plurality of fixed wiring areas B in the gap area
Is provided, and there is no basic cell area A dedicated as a wiring area as shown in FIG.

Therefore, in the upper half area of FIG. 1, by considering the layout so as to optimize the number of basic cell columns used as wiring areas, all the basic cell areas can be used as logic cells or wiring areas without waste. In the lower half area of FIG. 1 in which logic cells such as memory cells which are usable and mainly have a small wiring area are formed, the wiring between the logic cells (memory cells) can be performed without using the basic cell area. It is possible.

As described above, according to the present invention, the region between the columns of the basic cell region on the semiconductor chip is used as a fixed wiring region for wiring between logic cells. Even in the area where the logic cell of the wiring area is extremely small, it is not necessary to use the basic cell area as the wiring area, so that a large unused area does not occur in the basic cell area, and the semiconductor chip size is reduced. And high integration of the master slice LSI can be realized,
As a result, the cost of the LSI can be reduced.

[Brief description of drawings]

FIG. 1 shows a master slice L which is an embodiment of the present invention.
It is a wiring diagram which shows the internal region of SI. FIG. 2 is a wiring diagram showing an internal area of a conventional master slice LSI. In the figure, 1 is a semiconductor chip, 2 is a basic cell, 3 is a gap between basic cell regions, 4 is a logic cell, 5 is a vertical direction Al1.
Layer wiring, 6 is a lateral Al2 layer wiring, and 7 is a through hole.

Claims (4)

[Claims] 1. A master slice LSI having a plurality of basic cell regions formed in a row of a plurality of basic cells on a semiconductor chip at predetermined intervals, wherein By the basic cell,
A plurality of first-type logic cells that require a relatively large number of wirings between each other are configured, and a plurality of other basic cells in the plurality of basic cell regions that require a relatively small number of wirings between each other. Second
Different types of logic cells are formed, and the wiring regions for connecting the plurality of first type logic cells are formed with the first and second type logic cells in the plurality of basic cell regions. And a wiring region for connecting the plurality of second-type logic cells to each other, the wiring region being formed at a predetermined interval between adjacent ones of the plurality of basic cell regions on the semiconductor chip. A master slice LSI, which is formed into a. 2. The master slice LSI according to claim 1, wherein the basic cell includes a bipolar transistor and a resistor. 3. The master slice LSI according to claim 1, wherein the basic cell is composed of a MOS transistor. 4. The master slice LSI according to claim 1, wherein the second type logic cell is a memory cell.