JPS61225845A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61225845A JPS61225845A JP60066867A JP6686785A JPS61225845A JP S61225845 A JPS61225845 A JP S61225845A JP 60066867 A JP60066867 A JP 60066867A JP 6686785 A JP6686785 A JP 6686785A JP S61225845 A JPS61225845 A JP S61225845A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output buffer
- chip
- pad
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000872 buffer Substances 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 239000011295 pitch Substances 0.000 description 11
- 238000003491 array Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特にゲートアレーのパッド
数を増加させるのに適した構造を有するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to one having a structure suitable for increasing the number of pads in a gate array.
ゲートアレーは拡散工程までを終え、内部セル列及び入
出力バッファ等を形成しておき、後に例えば２層のＡＭ
配線を形成することにより完成品とするものである。従
来のゲートアレーのチップの一例を第３図に示す。The gate array has been completed up to the diffusion process, internal cell rows, input/output buffers, etc. have been formed, and later, for example, a two-layer AM
A completed product is created by forming wiring. An example of a conventional gate array chip is shown in FIG.
第３図において、チップ１の中央部には多数の内部セル
２が配列されており、その周囲の４辺には複数の入出力
バッファ３が配列されている。これら入出力バッファ３
の列の上方には絶縁膜を介して第２層のＡｎからなる電
源ライン４．５が設けられている。更に、チップｌの周
縁部には入出力バッファ３の列と平行して複数のパッド
６が配列されている。これら入出力バッファ３とパッド
６とは隣接するもの同士が１対１に対応して接続されて
いる。In FIG. 3, a large number of internal cells 2 are arranged in the center of a chip 1, and a plurality of input/output buffers 3 are arranged around the four sides. These input/output buffers 3
A power supply line 4.5 made of a second layer of An is provided above the column with an insulating film interposed therebetween. Furthermore, a plurality of pads 6 are arranged in parallel to the rows of input/output buffers 3 at the peripheral edge of the chip l. Adjacent input/output buffers 3 and pads 6 are connected in a one-to-one correspondence.
ゲートアレーおいては入出力バッファを全て同一の回路
構造としておき、後の配線形成によって異なる機能を持
たせ、入力回路としても出力回路としても用いることが
できるようにすれば、その配置について特に考慮する必
要がなく、配置可能な位置であればどの位置に配置して
もよい、こうした設計の効率上の観点から、一般的に全
ての入出力バッファ３は例えばＰチャネル及びＮチャネ
ルの各トランジスタを少なくとも１個づつ並びに入力保
護回路を設けた同一の構造としている。In a gate array, all input/output buffers have the same circuit structure, and if they are given different functions by later wiring formation so that they can be used as either input or output circuits, special consideration should be given to their placement. From the standpoint of design efficiency, all input/output buffers 3 typically include, for example, P-channel and N-channel transistors. They have the same structure with at least one input protection circuit provided.
近年、ゲートアレーの機能向上を図るために、パッドの
数を増加させることが要望されている。In recent years, in order to improve the functionality of gate arrays, it has been desired to increase the number of pads.
しかし、第３図に示すように、入出力バッファ３とパッ
ド６とを隣接するもの同士、１対ｌの対応で接続してい
る構造ではパッド６の数を増加させることはできない、
これは、チップｌのコーナー部（第３図中破線で囲まれ
た領域）には入力専用パッドや電源専用パッドを配置す
るには充分なスペースがあるが、入出力バッファ３を全
て同一構造とした場合には大きな面積を占めるので、チ
ップ１のコーナー部では増加された入出力バッファ３同
士が重なってしまうためである。However, as shown in FIG. 3, the number of pads 6 cannot be increased in a structure in which input/output buffers 3 and pads 6 are connected to each other in a 1:1 correspondence.
This is because there is enough space in the corner of chip 1 (area surrounded by broken lines in Figure 3) to place input-only pads and power-only pads, but all input/output buffers 3 have the same structure. This is because the increased input/output buffers 3 overlap each other in the corner portions of the chip 1, since this occupies a large area.
ハンドクラフト製品では、チップｌのコーナー部には不
定形のパターンを形成することによりチップ面積の有効
利用が可能である。しかし。In handcrafted products, the chip area can be effectively utilized by forming an irregular pattern at the corner portion of the chip l. but.
ゲートアレーではこのような手法を採用することは困難
であり、チップ面積が有効に利用されていない。It is difficult to employ such a technique in gate arrays, and the chip area is not used effectively.
本発明は上記事情を考慮してなされたものであり、チッ
プのコーナー部を有効に利用して、チップ面積を増加さ
せずにパッド数を増加させることができ、高い機能を有
するゲートアレー等の半導体装置を提供しようとするも
のである。The present invention has been made in consideration of the above circumstances, and enables the number of pads to be increased without increasing the chip area by effectively utilizing the corner portions of the chip, and is suitable for use in gate arrays etc. with high functionality. The purpose is to provide a semiconductor device.
リソグラフィー技術が進歩している現在では入出力バッ
ファのピッチを狭くして配列することができる。一方、
パッドはリードフレームの加工精度及びボンディングワ
イヤの直径等により制約を受けるため、パッドには１５
０〜２００ＪＬｍ程度のピッチが必要となるが、従来使
用されていなかったコーナー部に配置することは可能で
ある。Nowadays, as lithography technology advances, input/output buffers can be arranged at narrower pitches. on the other hand,
The pad is limited by the processing accuracy of the lead frame, the diameter of the bonding wire, etc., so the pad is
Although a pitch of about 0 to 200 JLm is required, it is possible to arrange it in a corner part that has not been used conventionally.
本発明は上述したような入出力バッファのピッチとパッ
ドのピッチとの相違を利用してなされたものである。す
なわち本発明の半導体装置は、パッドのピッチよりも入
出力バッファのピッチを小さくして入出力バッファのう
ち隣接する位置に対応するパッドを有しない余剰のもの
を形成するとともに、チップのコーナー部にパッドを設
け、該コーナー部のパッドと前記余剰の入出力バッファ
とを接続したことを特徴とするものである。The present invention is made by taking advantage of the difference between the pitch of the input/output buffer and the pitch of the pads as described above. In other words, in the semiconductor device of the present invention, the pitch of the input/output buffers is made smaller than the pitch of the pads to form surplus input/output buffers that do not have pads corresponding to adjacent positions, and the pitch of the input/output buffers is made smaller than that of the pads. The present invention is characterized in that a pad is provided, and the pad at the corner portion is connected to the surplus input/output buffer.
このような半導体装置によれば、全ての入出力バッファ
が例えばＰチャネル及びＮチャネルのＭＯＳトランジス
タを少なくとも１個づつ並びに入力保護回路を有するよ
うな大きな面積を占めるものであってもチップのコーナ
ー部を有効利用してチップ面積を増加させずにパッドの
数を増加することができる。According to such a semiconductor device, even if all the input/output buffers occupy a large area, such as having at least one P-channel MOS transistor and one N-channel MOS transistor and an input protection circuit, the corner portion of the chip The number of pads can be increased without increasing the chip area by making effective use of this.
なお、コーナー部のパッドと余剰の入出力バッファとは
、バッファを入力回路として用いる場合には入力保護抵
抗を介して接続し、出力回路として用いる場合には金属
配線を介して接続すればよい。Note that the corner pad and the surplus input/output buffer may be connected through an input protection resistor when the buffer is used as an input circuit, and through a metal wiring when the buffer is used as an output circuit.
以下１本発明の実施例を第１図を参照して説明する。な
お、第１図にはチップのコーナー部近傍を図示する。An embodiment of the present invention will be described below with reference to FIG. Note that FIG. 1 shows the vicinity of the corner portion of the chip.
第１図において、チップ１１の中央部には多数の内部セ
ル１２が配列されており、その周囲の４辺には複数の入
出力バッファ１３が配列されている。これら全ての入出
力バッファ１３はＰチャネル及びＮチャネルのＭＯＳト
ランジスタを少なくとも１個づつ並びに入力保護回路を
有する同一の構造となっている。これら人出力バッファ
１３の列の上方には絶縁膜を介して第２層のＡｉからな
る電源ライン（ｖＤＤライン及びＧＮＤライン）１４．
１５が設けられている。更に、チップ１１の周縁部には
入出力バッファ１３の列と平行して複数のパッド１６が
配列されている。In FIG. 1, a large number of internal cells 12 are arranged in the center of a chip 11, and a plurality of input/output buffers 13 are arranged around the four sides. All of these input/output buffers 13 have the same structure, including at least one P-channel MOS transistor and one N-channel MOS transistor, and an input protection circuit. Above the rows of these human output buffers 13 are power lines (vDD line and GND line) 14. made of second layer Ai with an insulating film interposed therebetween.
15 are provided. Furthermore, a plurality of pads 16 are arranged on the periphery of the chip 11 in parallel with the rows of input/output buffers 13.
前記入出力バッファ１３のピッチはパッド１６のピッチ
（１５０〜２００終ｍ）よりも狭く、入出力バッファ列
のうちには隣接する位置に対応するパッド１６を有しな
い余剰の入出力バッファ１３’が形成されている。また
、従来のゲートアレーでは使用されていなかったチップ
１１のコーナー部には新たにパッド１６′が合計８個形
成されている。The pitch of the input/output buffers 13 is narrower than the pitch of the pads 16 (150 to 200 m), and there are surplus input/output buffers 13' in the input/output buffer row that do not have pads 16 corresponding to adjacent positions. It is formed. Furthermore, a total of eight pads 16' are newly formed in the corner portions of the chip 11, which were not used in the conventional gate array.
前記入出力バッファ列の大部分とパッド列の大部分は互
いに隣接するもの同士が接続されている。そして、チッ
プ１１のコーナー部に設けられたパッド１６′と余剰の
入出力バッファ１３’とは多結晶シリコンからなる入力
保護抵抗１７及び第２層のＡｌ配線１８を介して接続さ
れている。Most of the input/output buffer rows and most of the pad rows are connected to each other adjacent to each other. Pads 16' provided at the corners of the chip 11 and surplus input/output buffers 13' are connected via an input protection resistor 17 made of polycrystalline silicon and a second layer Al wiring 18.
この場合、余剰の入出力バッファ１３′は入力回路とし
て用いられる。なお、第２層のＡｎからなる電源ライン
１４．１５の間は前記第２層のＡｎ配線１８を配置する
ためのスペースが設けられている。In this case, the surplus input/output buffer 13' is used as an input circuit. Note that a space is provided between the power lines 14 and 15 made of second layer An to arrange the second layer An wiring 18.
上記ゲートアレーでは１人出力バッファ列のピッチをパ
ッド列のピッチよりも狭くシ、入出力パッファ列のうち
、隣接する位置に対応するパッド１６を有しない余剰の
入出力バッファ１３’を形成するとともに、従来のゲー
トアレーでは使用されていなかったチップ１１のコーナ
ー部に新たにパッド１６′を形成し、これらを入力保護
抵抗１７及びＡｎ配線１８により接続している。このた
め、チップ面積の有効利用を図ることができ、チップ面
積を増大させることなくパッドの数を増加することがで
き、ゲートアレーの機能を向上することができる。In the above gate array, the pitch of the single output buffer row is narrower than the pitch of the pad row, and redundant input/output buffers 13' which do not have pads 16 corresponding to adjacent positions among the input/output buffer rows are formed. A new pad 16' is formed at a corner portion of the chip 11, which is not used in the conventional gate array, and these are connected by an input protection resistor 17 and an An wiring 18. Therefore, the chip area can be used effectively, the number of pads can be increased without increasing the chip area, and the function of the gate array can be improved.
なお、第１図図示のゲートアレーでは、チップ１１のコ
ーナー部に設けられたパッド１６′と余剰の入出力バッ
ファ１３’との接続は多結晶シリコンからなる入力保護
抵抗１７及び第２層のＡｉ配線１８を介して行なったが
、両者の接続方法はこれに限定されない０例えば、第２
図に示す如く、チップ１１のコーナー部に設けられたパ
ッド１６′と余剰の入出力バッファ１３’との接続を多
結晶シリコンからなる入力保護抵抗１９及び第１層のＡ
ｎ配線２０を介して行なってもよい、この場合、第１層
のＡ！；Ｌ配線２０は第３図中配線スペースとしての使
用頻度が非常に少ない一点鎖線で囲まれた領域を使用す
るように配置され、人出カバ７２７列の内側から余剰の
入出力バッファ１３′に接続される。In the gate array shown in FIG. 1, the pad 16' provided at the corner of the chip 11 and the surplus input/output buffer 13' are connected by an input protection resistor 17 made of polycrystalline silicon and a second layer of Ai. Although this is done via the wiring 18, the method of connecting the two is not limited to this. For example, the second
As shown in the figure, the connection between the pad 16' provided at the corner of the chip 11 and the surplus input/output buffer 13' is made using an input protection resistor 19 made of polycrystalline silicon and an A of the first layer.
This may be done via the n wiring 20. In this case, the first layer A! ; The L wiring 20 is arranged so as to use the area surrounded by a dashed line in FIG. Connected.
また、以上の説明では余剰の入出力バッファ１３′を入
力回路として用いる場合について説明したが、余剰の入
出力バッファ１３′を出力回路として用いてもよい゛、
この場合、入力保護抵抗１７．１９の代りに第１層のＡ
Ｍ配線を設ければよい。Further, in the above explanation, the case where the surplus input/output buffer 13' is used as an input circuit has been explained, but the surplus input/output buffer 13' may also be used as an output circuit.
In this case, instead of the input protection resistor 17.19, the first layer A
M wiring may be provided.
更に、以上の説明では１チツプあたりパッドが８個増加
する場合について説明したが、スペースの許す限り、パ
ッド等を増加することができることは勿論である。Further, in the above description, the case where the number of pads per chip is increased by 8 has been explained, but it goes without saying that the number of pads etc. can be increased as long as space allows.
以上詳述した如く本発明によれば、チップのコーナー部
を有効に利用して、チップ面積を増加させずにパッド数
を増加させることができ、高い機能を有するゲートアレ
ー等の半導体装置を提供できるものである。As detailed above, according to the present invention, the number of pads can be increased without increasing the chip area by effectively utilizing the corner portions of the chip, and a semiconductor device such as a gate array with high functionality is provided. It is possible.
第１図は本発明の実施例におけるゲートアレーのチップ
コーナー部近傍の平面図、第２図は本発明の他の実施例
におけるゲート７レーのチップコーナー部近傍の平面図
、第３図は従来のゲートアレーの平面図である。
１１・・・半導体チップ、１２・・・内部セル、１３・
・・入出力バッファ、１３′・・・余剰の入出力バッフ
ァ、１４．１５・・・電源ライン、１６．１６’・・・
パッド、１７．１９・・・入力保護抵抗、１８・・・第
２層のＡ交配線、２０・・・第１層のＡｎ配線。FIG. 1 is a plan view of the vicinity of a chip corner of a gate array according to an embodiment of the present invention, FIG. 2 is a plan view of the vicinity of a chip corner of a gate array according to another embodiment of the present invention, and FIG. 3 is a plan view of the vicinity of a chip corner of a gate array according to another embodiment of the present invention. FIG. 3 is a plan view of the gate array of FIG. 11... Semiconductor chip, 12... Internal cell, 13.
...I/O buffer, 13'... Surplus I/O buffer, 14.15... Power line, 16.16'...
Pad, 17.19... Input protection resistor, 18... A cross line of second layer, 20... An wiring of first layer.
Claims (4)
、該内部セル列の周囲に設けられた入出力バッファ列と
、チップ周縁部に入出力バッファ列と平行して設けられ
たパッド列とを有する半導体装置において、パッドのピ
ッチよりも入出力バッファのピッチを小さくして入出力
バッファのうち隣接する位置に対応するパッドを有しな
い余剰のものを形成するとともに、チップのコーナー部
にパッドを設け、該コーナー部のパッドと前記余剰の入
出力バッファとを接続したことを特徴とする半導体装置
。(1) An internal cell row provided in the center of the semiconductor chip, an input/output buffer row provided around the internal cell row, and a pad row provided in parallel with the input/output buffer row at the periphery of the chip. In a semiconductor device having an input/output buffer, the pitch of the input/output buffer is made smaller than the pitch of the pads to form a surplus input/output buffer that does not have a pad corresponding to an adjacent position, and a pad is placed at the corner of the chip. 1. A semiconductor device, wherein a pad at the corner portion is connected to the surplus input/output buffer.
ルのＭＯＳトランジスタを少なくとも１個づつ並びに入
力保護回路を有することを特徴とする特許請求の範囲第
１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein all input/output buffers include at least one P-channel MOS transistor and one N-channel MOS transistor, and an input protection circuit.
入力保護抵抗を介して接続したことを特徴とする特許請
求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the corner pad and the surplus input/output buffer are connected through an input protection resistor.
金属配線を介して接続したことを特徴とする特許請求範
囲第１項記載の半導体装置。(4) The semiconductor device according to claim 1, wherein the corner pad and the surplus input/output buffer are connected via metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60066867A JPS61225845A (en) | 1985-03-30 | 1985-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60066867A JPS61225845A (en) | 1985-03-30 | 1985-03-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61225845A true JPS61225845A (en) | 1986-10-07 |
Family
ID=13328240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60066867A Pending JPS61225845A (en) | 1985-03-30 | 1985-03-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61225845A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344734A (en) * | 1986-08-12 | 1988-02-25 | Fujitsu Ltd | Semiconductor device |
| JPH04328847A (en) * | 1991-04-26 | 1992-11-17 | Nec Corp | Integrated circuit and layout system thereof |
| JPH0621331A (en) * | 1992-07-06 | 1994-01-28 | Fujitsu Ltd | Semiconductor integrated circuit |
| JP2014022630A (en) * | 2012-07-20 | 2014-02-03 | Rohm Co Ltd | Semiconductor device |
-
1985
- 1985-03-30 JP JP60066867A patent/JPS61225845A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344734A (en) * | 1986-08-12 | 1988-02-25 | Fujitsu Ltd | Semiconductor device |
| JPH04328847A (en) * | 1991-04-26 | 1992-11-17 | Nec Corp | Integrated circuit and layout system thereof |
| JPH0621331A (en) * | 1992-07-06 | 1994-01-28 | Fujitsu Ltd | Semiconductor integrated circuit |
| JP2014022630A (en) * | 2012-07-20 | 2014-02-03 | Rohm Co Ltd | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6047441A (en) | Semiconductor integrated circuit | |
| JPH02177345A (en) | Semiconductor integrated circuit device | |
| JPH02219254A (en) | Semiconductor integrated circuit device | |
| JPH11121498A (en) | Semiconductor integrated circuit device | |
| JPS61225845A (en) | Semiconductor device | |
| JPH1098108A (en) | Semiconductor device | |
| JPS58116757A (en) | Master slice lsi | |
| JPH0542823B2 (en) | ||
| JPH01168042A (en) | Semiconductor integrated circuit device | |
| JPH03203363A (en) | Semiconductor device | |
| JPS59145542A (en) | Large-scale integrated circuit | |
| JPS6276735A (en) | Semiconductor integrated circuit device | |
| JPH09153286A (en) | Semiconductor memory device | |
| JP2752262B2 (en) | Manufacturing method of one-chip LSI | |
| JPS63273332A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH065782A (en) | Layout method at corner part of semiconductor and semiconductor integrated circuit device | |
| JPH0548054A (en) | Master slice type semiconductor integrated circuit device | |
| JPH05166932A (en) | Semiconductor integrated circuit device | |
| JPH02144936A (en) | Semiconductor integrated circuit device | |
| JPH0831524B2 (en) | Semiconductor integrated circuit device | |
| JPH0348668B2 (en) | ||
| JPH04186749A (en) | Semiconductor integrated circuit device | |
| JPS59167036A (en) | Semiconductor integrated circuit | |
| JPH0548048A (en) | Master slice tyep semiconductor integrated circuit device | |
| JPH09148545A (en) | Semiconductor device |